Hdlbits-＞circuits-＞shift registers

Shift4

Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.

• areset: Resets shift register to zero.
• load: Loads shift register with data[3:0] instead of shifting.
• ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).
• q: The contents of the shift register.

If both the load and ena inputs are asserted (1), the load input has higher priority.

Module Declaration

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 

Write your solution here

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    always@(posedge clk or posedge areset) begin
        if(areset) begin
            q <= 0;
        end
        else begin
            if (load)
                q <= data;
            else if(ena)
                q <= q >> 1;
        end
    end
endmodule

网页答案：

module top_module(
	input clk,
	input areset,
	input load,
	input ena,
	input [3:0] data,
	output reg [3:0] q);
	
	// Asynchronous reset: Notice the sensitivity list.
	// The shift register has four modes:
	//   reset
	//   load
	//   enable shift
	//   idle -- preserve q (i.e., DFFs)
	always @(posedge clk, posedge areset) begin
		if (areset)		// reset
			q <= 0;
		else if (load)	// load
			q <= data;
		else if (ena)	// shift is enabled
			q <= q[3:1];	// Use vector part select to express a shift.
	end
	
endmodule

Rotate100

Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.

• load: Loads shift register with data[99:0] instead of rotating.
• ena[1:0]: Chooses whether and which direction to rotate.
  • 2'b01 rotates right by one bit
  • 2'b10 rotates left by one bit
  • 2'b00 and 2'b11 do not rotate.
• q: The contents of the rotator.

Module Declaration

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 

Write your solution here

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
    always@(posedge clk) begin
        if(load) begin
            q <= data;
        end
        else begin
            case(ena) 
                2'b01:
                    q <= {q[0], q[99:1]};
                2'b10:
                    q <= {q[98:0], q[99]};
                default:
                    q <= q;
            endcase
        end
    end
endmodule

网页答案：

module top_module(
	input clk,
	input load,
	input [1:0] ena,
	input [99:0] data,
	output reg [99:0] q);
	
	// This rotator has 4 modes:
	//   load
	//   rotate left
	//   rotate right
	//   do nothing
	// I used vector part-select and concatenation to express a rotation.
	// Edge-sensitive always block: Use non-blocking assignments.
	always @(posedge clk) begin
		if (load)		// Load
			q <= data;
		else if (ena == 2'h1)	// Rotate right
			q <= {q[0], q[99:1]};
		else if (ena == 2'h2)	// Rotate left
			q <= {q[98:0], q[99]};
	end
endmodule

Shift18

Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.

An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.

There is no difference between logical and arithmetic left shifts.

• load: Loads shift register with data[63:0] instead of shifting.
• ena: Chooses whether to shift.
• amount: Chooses which direction and how much to shift.
  • 2'b00: shift left by 1 bit.
  • 2'b01: shift left by 8 bits.
  • 2'b10: shift right by 1 bit.
  • 2'b11: shift right by 8 bits.
• q: The contents of the shifter.

Module Declaration

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 

Hint...

A 5-bit number 11000 arithmetic right-shifted by 1 is 11100, while a logical right shift would produce 01100.

Similarly, a 5-bit number 01000 arithmetic right-shifted by 1 is 00100, and a logical right shift would produce the same result, because the original number was non-negative.

Write your solution here

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    always@(posedge clk) begin
        if (load) begin
            q <= data;
        end
        else if(ena) begin
            case(amount)
               	2'b00:
                    q <= q<<1;
                2'b01:
                    q <= q<<8;
                2'b10:
                    q <= {{2{q[63]}}, q[62:1]};
               	2'b11:
                    q <= {{9{q[63]}}, q[62:8]};
                default:
                    q <= q;
            endcase
        end
        else
            q <= q;
    end
endmodule

Lfsr5

A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through 2n-1 states before repeating (the all-zero state is never reached).

The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.

Build this LFSR. The reset should reset the LFSR to 1. 

Module Declaration

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
);

 Hint...

The first few states starting at 1 are 00001, 10100, 01010, 00101, ... The LFSR should cycle through 31 states before returning to 00001.

Write your solution here

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
    always@(posedge clk) begin
        if(reset) begin
            q <= 5'h1;
        end
        else begin
            q <= {q[0]^1'b0, q[4], q[3]^q[0], q[2], q[1]};
        end
    end

endmodule

 网站答案：

module top_module(
	input clk,
	input reset,
	output reg [4:0] q);
	
	reg [4:0] q_next;		// q_next is not a register

	// Convenience: Create a combinational block of logic that computes
	// what the next value should be. For shorter code, I first shift
	// all of the values and then override the two bit positions that have taps.
	// A logic synthesizer creates a circuit that behaves as if the code were
	// executed sequentially, so later assignments override earlier ones.
	// Combinational always block: Use blocking assignments.
	always @(*) begin
		q_next = q[4:1];	// Shift all the bits. This is incorrect for q_next[4] and q_next[2]
		q_next[4] = q[0];	// Give q_next[4] and q_next[2] their correct assignments
		q_next[2] = q[3] ^ q[0];
	end
	
	
	// This is just a set of DFFs. I chose to compute the connections between the
	// DFFs above in its own combinational always block, but you can combine them if you wish.
	// You'll get the same circuit either way.
	// Edge-triggered always block: Use non-blocking assignments.
	always @(posedge clk) begin
		if (reset)
			q <= 5'h1;
		else
			q <= q_next;
	end
	
endmodule

Mt2015 lfsr

Taken from 2015 midterm question 5. See also the first part of this question: mt2015_muxdff

Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], and L to KEY[1]. Connect the Q outputs to the red lights LEDR. 

Module Declaration

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q

 Hint...

This circuit is an example of a Linear Feedback Shift Register (LFSR). A maximum-period LFSR can be used to generate pseudorandom numbers, as it cycles through 2n-1 combinations before repeating. The all-zeros combination does not appear in this sequence.

Write your solution here

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
    
    always@(posedge KEY[0]) begin
        if(KEY[1])
            LEDR[0] <= SW[0];
        else
            LEDR[0] <= LEDR[2];
    end
    
    always@(posedge KEY[0]) begin
        if(KEY[1])
            LEDR[1] <= SW[1];
        else
            LEDR[1] <= LEDR[0];
    end
    
    always@(posedge KEY[0]) begin
        if(KEY[1])
            LEDR[2] <= SW[2];
        else
            LEDR[2] <= LEDR[1]^LEDR[2];
    end
endmodule

Lfsr32

See Lfsr5 for explanations.

Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.

Module Declaration

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
); 

 Hint...

This is long enough that you'd want to use vectors, not 32 instantiations of DFFs.

Write your solution here

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
); 
    always@(posedge clk) begin
        if(reset)
            q <= 32'h1;
        else
            q <= {q[0]^1'b0, q[31:23], q[0]^q[22], q[21:3], q[0]^q[2], q[0]^q[1]};
    end
endmodule

Exams/m2014 q4k

Implement the following circuit:

Module Declaration

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);

Write your solution here

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    reg t1,t2,t3;
    always@(posedge clk) begin
        if (!resetn)
            t1 <= 0;
        else begin
            t1 <= in;
        end
    end
    always@(posedge clk) begin
        if (!resetn)
            t2 <= 0;
        else begin
            t2 <= t1;
        end
    end
    always@(posedge clk) begin
        if (!resetn)
            t3 <= 0;
        else begin
            t3 <= t2;
        end
    end
    always@(posedge clk) begin
        if (!resetn)
            out <= 0;
        else begin
            out <= t3;
        end
    end
endmodule

网页答案：

module top_module (
	input clk,
	input resetn,
	input in,
	output out
);

	reg [3:0] sr;
	
	// Create a shift register named sr. It shifts in "in".
	always @(posedge clk) begin
		if (~resetn)		// Synchronous active-low reset
			sr <= 0;
		else 
			sr <= {sr[2:0], in};
	end
	
	assign out = sr[3];		// Output the final bit (sr[3])

endmodule

Exams/2014 q4b

Consider the n-bit shift register circuit shown below:

Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.

• Connect the R inputs to the SW switches,
• clk to KEY[0],
• E to KEY[1],
• L to KEY[2], and
• w to KEY[3].
• Connect the outputs to the red lights LEDR[3:0].

(Reuse your MUXDFF from exams/2014_q4a.)

Module Declaration

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); 

Write your solution here

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); //
    MUXDFF m1(KEY[0], KEY[1], KEY[2], KEY[3], SW[3], LEDR[3]);
    MUXDFF m2(KEY[0], KEY[1], KEY[2], LEDR[3], SW[2], LEDR[2]);
    MUXDFF m3(KEY[0], KEY[1], KEY[2], LEDR[2], SW[1], LEDR[1]);
    MUXDFF m4(KEY[0], KEY[1], KEY[2], LEDR[1], SW[0], LEDR[0]);
endmodule

module MUXDFF (
    input clk,
    input E, L, w, R, 
    output Q
);
    always@(posedge clk) begin
        Q <= L ? R : (E ? w : Q);
    end
endmodule

Exams/ece241 2013 q12

In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is "random access", as in a typical RAM. You will then use the circuit to realize a 3-input logic function.

First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit's behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).

Module Declaration

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 

Write your solution here

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    wire [7:0]Q;
    bits_shift bs(clk, S, enable, Q);
    always@(*) begin
        case({A,B,C})
            3'd0: Z = Q[0];
            3'd1: Z = Q[1];
            3'd2: Z = Q[2];
            3'd3: Z = Q[3];
            3'd4: Z = Q[4];
            3'd5: Z = Q[5];
            3'd6: Z = Q[6];
            3'd7: Z = Q[7];
        endcase
    end
endmodule

module bits_shift (
    input clk,
    input d,
    input enable,
    output [7:0] q
);
    always@(posedge clk) begin
        if (enable) begin
            q <= {q[6:0], d};
        end
        else begin
            q <= q;
        end
    end
endmodule

网页答案：

module top_module (
	input clk,
	input enable,
	input S,
	
	input A, B, C,
	output reg Z
);

	reg [7:0] q;
	
	// The final circuit is a shift register attached to a 8-to-1 mux.
	


	// Create a 8-to-1 mux that chooses one of the bits of q based on the three-bit number {A,B,C}:
	// There are many other ways you could write a 8-to-1 mux
	// (e.g., combinational always block -> case statement with 8 cases).
	assign Z = q[ {A, B, C} ];



	// Edge-triggered always block: This is a standard shift register (named q) with enable.
	// When enabled, shift to the left by 1 (discarding q[7] and and shifting in S).
	always @(posedge clk) begin
		if (enable)
			q <= {q[6:0], S};	
	end
	
	
	
endmodule

Rule90

Rule 90 is a one-dimensional cellular automaton with interesting properties.

The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neighbours. A more verbose way of expressing this rule is the following table, where a cell's next state is a function of itself and its two neighbours:

(The name "Rule 90" comes from reading the "next state" column: 01011010 is decimal 90.)
In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).

Module Declaration

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 

Hint...

For an initial state of q[511:0] = 1, the first few iterations are:

       1
      10
     101
    1000
   10100
  100010
 1010101
10000000

This forms half of a Sierpiński triangle.

Write your solution here

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    always@(posedge clk) begin
        if (load) begin
            q <= data;
        end
        else begin
            q <= {1'b0, q[511:1]} ^ {q[510:0], 1'b0};
        end
    end
endmodule

网页答案：

module top_module(
	input clk,
	input load,
	input [511:0] data,
	output reg [511:0] q);
	
	always @(posedge clk) begin
		if (load)
			q <= data;	// Load the DFFs with a value.
		else begin
			// At each clock, the DFF storing each bit position becomes the XOR of its left neighbour
			// and its right neighbour. Since the operation is the same for every
			// bit position, it can be written as a single operation on vectors.
			// The shifts are accomplished using part select and concatenation operators.
			
			//     left           right
			//  neighbour       neighbour
			q <= q[511:1] ^ {q[510:0], 1'b0} ;
		end
	end
endmodule

Rule110

Rule 110 is a one-dimensional cellular automaton with interesting properties (such as being Turing-complete).

There is a one-dimensional array of cells (on or off). At each time step, the state of each cell changes. In Rule 110, the next state of each cell depends only on itself and its two neighbours, according to the following table:

(The name "Rule 110" comes from reading the "next state" column: 01101110 is decimal 110.)

In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).

Module Declaration

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 

Hint...

For an initial state of q[511:0] = 1, the first few iterations are:

       1
      11
     111
    1101
   11111
  110001
 1110011
11010111

Write your solution here

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
    wire [511:0] left, right;
    assign left = {1'b0, q[511:1]};
    assign right = {q[510:0], 1'b0};
    always@(posedge clk) begin
        if(load)
            q <= data;
        else begin
            q <= (q^right) | (~left&right);
            q <= (q & ~right) | (~left & right) | (~q & right);
        end
    end
endmodule

Conwaylife

Conway's Game of Life is a two-dimensional cellular automaton.

The "game" is played on a two-dimensional grid of cells, where each cell is either 1 (alive) or 0 (dead). At each time step, each cell changes state depending on how many neighbours it has:

• 0-1 neighbour: Cell becomes 0.
• 2 neighbours: Cell state does not change.
• 3 neighbours: Cell becomes 1.
• 4+ neighbours: Cell becomes 0.

The game is formulated for an infinite grid. In this circuit, we will use a 16x16 grid. To make things more interesting, we will use a 16x16 toroid, where the sides wrap around to the other side of the grid. For example, the corner cell (0,0) has 8 neighbours: (15,1), (15,0), (15,15), (0,1), (0,15), (1,1), (1,0), and (1,15). The 16x16 grid is represented by a length 256 vector, where each row of 16 cells is represented by a sub-vector: q[15:0] is row 0, q[31:16] is row 1, etc. (This tool accepts SystemVerilog, so you may use 2D vectors if you wish.)

• load: Loads data into q at the next clock edge, for loading initial state.
• q: The 16x16 current state of the game, updated every clock cycle.

The game state should advance by one timestep every clock cycle.

John Conway, mathematician and creator of the Game of Life cellular automaton, passed away from COVID-19 on April 11, 2020.

Module Declaration

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output [255:0] q ); 

Hint...

A test case that's easily understandable and tests some boundary conditions is the blinker 256'h7. It is 3 cells in row 0 columns 0-2. It oscillates between a row of 3 cells and a column of 3 cells (in column 1, rows 15, 0, and 1).

Write your solution here

抄的网上的别人的答案

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output [255:0] q ); 
    
    reg [15:0] q_2d [15:0]; //2-d q
    reg [15:0] q_next [15:0]; //2-d q_next
    reg [3:0] sum;
    integer i,j;
    always@(*)begin
        for(i=0;i<16;i++)begin
            for(j=0;j<16;j++)begin
                if(i==0 && j==0)//左上角
                    sum=q_2d[15][1]+q_2d[15][0]+q_2d[15][15]+q_2d[0][1]+q_2d[0][15]+q_2d[1][0]+q_2d[1][1]+q_2d[1][15];
                else if(i==0 && j==15)//右上角
                    sum=q_2d[0][0]+q_2d[0][14]+q_2d[15][0]+q_2d[15][14]+q_2d[15][15]+q_2d[1][0]+q_2d[1][14]+q_2d[1][15];
                else if(i==15 && j==0)//左下角
                    sum=q_2d[15][1]+q_2d[15][15]+q_2d[14][0]+q_2d[14][15]+q_2d[14][1]+q_2d[0][0]+q_2d[0][1]+q_2d[0][15];
                else if(i==15 && j==15)//右下角
                    sum=q_2d[15][0]+q_2d[15][14]+q_2d[14][15]+q_2d[14][0]+q_2d[14][14]+q_2d[0][0]+q_2d[0][15]+q_2d[0][14];
                else if(i==0)//上边界
                    sum=q_2d[0][j-1]+q_2d[0][j+1]+q_2d[1][j-1]+q_2d[1][j]+q_2d[1][j+1]+q_2d[15][j-1]+q_2d[15][j]+q_2d[15][j+1];
                else if(i==15)//下边界
                    sum=q_2d[15][j-1]+q_2d[15][j+1]+q_2d[0][j-1]+q_2d[0][j]+q_2d[0][j+1]+q_2d[14][j-1]+q_2d[14][j]+q_2d[14][j+1];
                else if(j==0)//左边界
                    sum=q_2d[i][1]+q_2d[i][15]+q_2d[i-1][0]+q_2d[i-1][15]+q_2d[i-1][1]+q_2d[i+1][0]+q_2d[i+1][1]+q_2d[i+1][15];
                else if(j==15)//右边界
                    sum=q_2d[i][0]+q_2d[i][14]+q_2d[i-1][0]+q_2d[i-1][14]+q_2d[i-1][15]+q_2d[i+1][0]+q_2d[i+1][14]+q_2d[i+1][15];
                else  //中间元素
                    sum=q_2d[i-1][j]+q_2d[i-1][j-1]+q_2d[i-1][j+1]+q_2d[i][j-1]+q_2d[i][j+1]+q_2d[i+1][j]+q_2d[i+1][j-1]+q_2d[i+1][j+1];

                case(sum)
                    2:q_next[i][j]=q_2d[i][j];
                    3:q_next[i][j]=1'b1;
                    default:q_next[i][j]=0;
                endcase
                
                //q_2d = q_next;
                
        end
    end
end
    
  
    always@(posedge clk)begin
        if(load)begin
            for(i=0;i<16;i++)begin
                for(j=0;j<16;j++)begin
                	q_2d[i][j] <=data[i*16+j]; 
            end 
        end
    end
        else 
            q_2d <= q_next;    
    end
    
    
    genvar m,n;
    generate
        for(m = 0; m < 16; m = m + 1) begin : line_reverse
            for(n = 0; n < 16; n = n + 1) begin : list_reverse
                assign q[m*16+n] = q_2d[m][n];
        end
       end
        
    endgenerate

        
endmodule