8.1 review 2

【1.leetcode 171】

1.ASCII: _______________      ord（'A'）=65

2.python 和 verilog 遍历的区别/list[0]: _________

python list[0] 是最左边，左->右，verilog 是最右边

3.进制的算法 'BA' ? ____________

Y=（该位的数）*（加多少数引发进位？）**index

index: ________       左<- 右

【2.sv】

2.1: callback, 用法？ 1，2，3 _________

1.预留入口｜｜ 2.define callback function/class｜｜ 3.instantiate and add callback instance

2.2: 参数化的类, 举例 _______

class mailbox #（type T=int）

【3.async fifo的verilog】

1.fifo_men 

Input wrclk

input wren

input full

Input [DSIZE-1:0]wrdata 

Output [DSIZE-1:0]rdata

Input [ASIZE-1:0] waddr

Input [ASIZE-1:0] raddr

//DEPTH的定义: ______

localparam DEPTH=1<<ASIZE;//1000

//RAM的定义：_________

[DSIZE-1:0]Ram[DEPTH-1:0]

Assign rdata=______

Ram[raddr];

always @(posedge wrclk) begin

 If (wren&& !full)begin

        Ram[waddr]<=wrdata;

        end

end

2.module wptr_full

#(parameter ASIZE=4)

(

output：_______

[ASIZE:0]w_ptr;

input w_rstn;

Input w_en;

output reg full;

input [ASIZE:0]w_rptr;

output [ASIZE-1:0]waddr;

input wclk;

)

reg [ASIZE:0] bin_ptr, next_ptr, next_grey;

reg val_full;

assign next_grey= _________ 

         (next_ptr>>1)^next_ptr;

assign next_ptr=__________

        bin_ptr+w_en&&(~full);

assign val_full=___________

        ({~w_rptr[ASIZE:ASIZE-1],w_rptr[ASIZE-2:0]}==next_grey);

assign waddr=____________

        bin_ptr[ASIZE-1:0];

always @(posedge wclk or negedge w_rstn) begin

        If (!w_rstn) begin

                full<=0;

                w_ptr<=0;

                bin_ptr<=0;

        end

        else begin

                full<=val_full;

                w_ptr<=next_grey;

                bin_ptr<=next_ptr; 

        end

end