weixin_53877865的博客

下面是i的更新代码

//一个时钟周期卷积一行
always@(posedge clk or negedge rst_n) begin
    if(!rst_n) 
        i <= 8'b0;
    else if(i == (DATA_WIDTH-1))
        i <= 8'b0;
    else
        i <= i + 8'd1;
end

always@(posedge clk) begin
    if(!rst_n)
        init_begin <= 1'b0;
    else if(i==0)
        init_begin <= 1'b1;
    else
        init_begin <= init_begin;
end