基于Robeo EDA状态机--可乐机售卖

不爱吃水萝卜

已于 2024-01-26 16:43:19 修改

阅读量402

点赞数 9

文章标签： fpga开发

于 2024-01-26 16:36:03 首次发布

本文链接：https://blog.csdn.net/weixin_73538444/article/details/135862573

版权

这篇文章详细介绍了使用Verilog语言编写的简单有限状态机(simple_fsm)设计，包括输入输出端口声明、状态定义、状态转移逻辑以及时序控制。测试模块(simple_fsm_tb)展示了如何驱动状态机并观察输出变化。

摘要由CSDN通过智能技术生成

module simple_fsm(
	clk,
	reset,
	pi_money,
	po_cola);

	//---Ports declearation: generated by Robei---
	input clk;
	input reset;
	input pi_money;
	output po_cola;

	wire clk;
	wire reset;
	wire pi_money;
	reg po_cola;

	//----Code starts here: integrated by Robei-----
	//状态机
	parameter IDLE = 3'b001;
	parameter ONE = 3'b010;
	parameter TWO = 3'b100;
	//reg define
	reg [2:0]state;
	//时序逻辑--描述状态的转移
	always @(posedge clk or negedge reset)
	if(reset == 0)
	  state <= IDLE;
	else begin
			case (state)
	  IDLE:		if(pi_money == 1'b1)
															state <= ONE;
													else state <= IDLE;
	  ONE:  if(pi_money == 1'b1)
															state <= TWO;
													else state <= ONE;
	  TWO: if(pi_money == 1'b1)
															state <= IDLE;
													else state <= TWO;
	  default:state <= IDLE;
	  endcase
	end 
	//时序逻辑--描述输出信号
	always@(posedge clk or negedge reset)
	if(reset == 0) begin
	  po_cola <= 0;
	end
	else if(state == TWO && pi_money == 1) begin
	  po_cola <= 1'b1;   end
	else  begin
	  po_cola <= 1'b0;
	end
	
	
	
endmodule    //simple_fsm

module simple_fsm_tb();

	reg clk;
	reg reset;
	reg pi_money;
	wire po_cola;

	//----Code starts here: integrated by Robei-----
	initial 
	begin 
	clk = 1; 
	end
	always#1 clk = ~clk;
	initial begin
	reset = 0;
	pi_money = 0;
	#1
	reset = 1;
	#2
	pi_money = 1;
	#4;
	pi_money = 0;
	#6
	pi_money = 1;
	#2
	pi_money = 0;
	#2
	pi_money = 1;
	#2
	pi_money = 0;
	 $finish;
	end
	
	
	initial begin
		$dumpfile ("D:/Robei_project/Robei_study_simple_fsm/simple_fsm_tb.vcd");
		$dumpvars;
	end
	//---Module instantiation---
	simple_fsm simple_fsm1(
		.clk(clk),
		.reset(reset),
		.pi_money(pi_money),
		.po_cola(po_cola));

endmodule    //simple_fsm_tb