HDLBit（43-60）（106了，中间简单的都跳过了）

最新推荐文章于 2023-05-12 09:37:14 发布

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最新推荐文章于 2023-05-12 09:37:14 发布

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分类专栏： verilog FPGA 文章标签： verilog fpga

本文链接：https://blog.csdn.net/wu1337300866/article/details/117599791

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时序逻辑部分

43、DFF
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module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//
    always@(posedge clk)
		q <= d;
endmodule

44、DFF8

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk)
		q <= d;
endmodule

45、DFF8R
同步复位哦

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk) 
        if(reset)
            q<='d0;
    	else 
			q <= d;  

endmodule

46、dff8ar
Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk or posedge areset) begin
        if(areset)
            q <= 8'b0;
        else
    	    q <= d;
    end
endmodule

47、
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注意为 if……if格式

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always@(posedge clk)
        if(!resetn)
            q <= 'd0;
    else if(byteena[0]||byteena[1])begin
        if(byteena[0])
            q[7:0]<=d[7:0];    
        if(byteena[1])
            q[15:8]<=d[15:8];
        else ;
    end
    else ;
endmodule

48、
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module top_module (
    input clk,
    input in, 
    output out);
    always@(posedge clk)
        out <= out ^ in;
endmodule

49、
在这里插入图片描述
写出其中的子模块

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
	wire q_w;
    assign q_w = L? r_in:q_in;
    always@(posedge clk)
        Q <= q_w;
endmodule

50、
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module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    wire D0,D1;
    assign D0 = E? w:Q;
    assign D1 = L? R:D0;
    always@(posedge clk)
        Q <= D1;
endmodule

51、
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module top_module (
    input clk,
    input x,
    output z
); 
reg q1=0,q2=0,q3=0;
    always@(posedge clk)begin
        q1 <= x^q1;
    	q2 <= ~q2&x;
    	q3<= ~q3|x;
    end
    assign z = ~(q1|q2|q3);
endmodule

52、
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module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    always@(posedge clk)
        begin
            case({j,k})
                2'b00:Q<=Q;
                2'b01:Q <= 'b0;
                2'b10:Q <= 'b1;
                2'b11:Q <= ~Q;
            endcase
        end
endmodule

53、每一位上升沿检测
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module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0]in_r;
    always@(posedge clk)begin
        in_r <= in;
    	pedge <= ~in_r&in;
    end
endmodule

54、双沿检测

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
   reg [7:0]in_r;
    always@(posedge clk)begin
        in_r <= in;
    	anyedge <= in_r&~in|~in_r&in;
    end
endmodule

55、
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module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0]in_r;
    reg [31:0]neg_edge;
    always@(posedge clk)begin
		in_r <= in;
    end
    assign neg_edge = ~in&in_r;
    always@(posedge clk)
        if(reset)
            out<= 'b0;
    	else begin
            for(integer i = 0;i<32;i=i+1)begin
                if(neg_edge[i])
                    out[i] <= 'b1;
            end
        end
endmodule

56、
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module top_module (
    input clk,
    input d,
    output q
);
    
    reg q1, q2;

    //这里来实现clk的上升沿与下降沿
    assign q = clk?q1:q2;

    always @ (posedge clk)
        begin
            q1 <= d;
        end

    always @ (negedge clk)
        begin
           q2 <= d; 
        end

endmodule

57、计数器
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module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
    always@(posedge clk)
        if(reset)
            q <= 'b0;
    	else if(q < 'd9)
        	q <= q + 1'b1;
    	else q <= 'b0;
endmodule

58、
在这里插入图片描述
注意slownea为控制q变化的主要

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
always@(posedge clk)
    if(reset)
        q <= 'd0;
    else if(slowena)
        if(q >= 'd9)
        	q <= 'd0;
        else 
            q <= q + 'd1;
    else ; 
endmodule

59、1000_1
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module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
    wire [3:0]count1,count2,count3;
    assign c_enable = {count2 == 4'd9 && count1 == 4'd9, count1 == 4'd9, 1'b1};
    assign OneHertz = {count1 == 4'd9 && count2 == 4'd9 && count3 == 4'd9};
	bcdcount counter0 (clk, reset, c_enable[0],count1);
    bcdcount counter1 (clk, reset, c_enable[1],count2);
    bcdcount counter2 (clk, reset, c_enable[2],count3);
endmodule

59、各十百千
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module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
	
    counter10 counter1(.clk(clk),.reset(reset),.en_10(1'b1),.q_10(q[3:0]));
    counter10 counter2(.clk(clk),.reset(reset),.en_10(q[3:0] == 4'd9),.q_10(q[7:4]));
    counter10 counter3(.clk(clk),.reset(reset),.en_10(q[7:4] == 4'd9 && q[3:0] == 4'd9),.q_10(q[11:8]));
    counter10 counter4(.clk(clk),.reset(reset),.en_10(q[11:8] == 4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd9),.q_10(q[15:12]));
    assign ena = {q[11:8] == 4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd9,q[7:4] == 4'd9 && q[3:0] == 4'd9,q[3:0] == 4'd9};
endmodule

module counter10(
	input clk,
    input reset,
    input en_10,
    output [3:0]q_10
);
    always@(posedge clk)
        if(reset)
			q_10 <= 'd0;
    	else if(en_10)
            if(q_10 <9)
        		q_10 <= q_10 +1;
    		else q_10 <='d0;
    	else ;
endmodule

60、时钟（这玩意用了我老长时间调试了）
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module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    reg [7:0] h , m , s;
    reg p;
    counter10 counter1(.clk(clk),.reset(reset),.en_10(ena),.q_10(s[3:0]));
    counter6 counter2(.clk(clk),.reset(reset),.en_10(ena && s[3:0] == 4'd9),.q_10(s[7:4]));
    
    counter10 counter3(.clk(clk),.reset(reset),.en_10(s[3:0] == 4'd9 && s[7:4] == 4'd5),.q_10(m[3:0]));
    counter6 counter4(.clk(clk),.reset(reset),.en_10(s[3:0] == 4'd9 && s[7:4] == 4'd5 && m[3:0] == 4'd9),.q_10(m[7:4]));
always@(posedge clk)begin  
    if(reset)   //reset to 12:00:00 AM
    begin
        p <= 0;
        h <= 8'h12;

    end
    else if(s == 8'h59 && m == 8'h59)begin
        if(h == 8'h11)  //AM / PM 转换
            p = !p;
        if(h < 8'h12)
            begin
                if(h[3:0] < 4'h9)
                    h[3:0] <= h[3:0] + 1'h1;
                else
                    begin
                        h[3:0] <= 4'h0;
                        h[7:4] <= h[7:4] + 1'h1;
                    end
            end
        else begin //hour 12 -> 1
            h <=8'h1; 
        end
    end
end
    

assign pm = p;
assign hh = h;
assign mm = m;
assign ss = s;

endmodule

module counter10(
	input clk,
    input reset,
    input en_10,
    output [3:0]q_10
);
    always@(posedge clk)
        if(reset)
			q_10 <= 'd0;
    	else if(en_10)
            if(q_10 <'d9)
        		q_10 <= q_10 +1;
    		else q_10 <='d0;
    	else ;
endmodule   	
module counter6(
	input clk,
    input reset,
    input en_10,
    output [3:0]q_10
);
    always@(posedge clk)
        if(reset)
			q_10 <= 'd0;
    	else if(en_10)
            if(q_10 <'d5)
        		q_10 <= q_10 +1;
    		else q_10 <='d0;
    	else ;
endmodule