[DRC 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity. The signal plle2_u/clk_out1 on the plle2_u/pll_test_inst/CLKIN1 pin of plle2_u/pll_test_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.
The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. However in your case it looks like it chose this incorrectly as ZHOLD. When the clock input of PLL is coming from BUFG then the compensation factor should be BUF_IN.
The COMPENSATION attribute values are documented for informational purpose only. The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. Do not manually select a compensation value, leave the attribute at the default value.
Clock input compensation. Must be set to ZHOLD. Defines how the MMCM feedback is configured.
ZHOLD: Indicates the MMCM is configured to provide a negative hold time at the I/O registers.
EXTERNAL: Indicates a network external to the FPGA is being compensated.
INTERNAL: Indicates the MMCM is using its own internal feedback path so no delay is being compensated.
BUF_IN: Indicates that the configuration does not match with the other compensation modes and no delay will be compensated. This is the case if a clock input is driven by a BUFG/BUFH/BUFR or GTX/GTH/GTP.
Refer to page-86 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf