ise verilog语言在xc3s50 动态显示电路输入六位学号

module add(
clk        ,
rst        ,
//clklms     ,
seg        ,
sel
);
 
input                      clk          ;
input                      rst          ;

output    reg    [5:0]     sel          ; //数码管位选
output    reg    [3:0]     seg          ; //数码管段选
 
//parameter    sys_clk  =  50_000_000     ;
//localparam   cnt1_max =  24             ;  //仿真1MHZ,1us

reg       [3:0]    selcnt               ; //数码管位选计数器

 
 
always@(posedge clk /*or negedge rst*/)
begin
    if (!rst)
        selcnt <= 4'd0;
    
	 else if (selcnt == 4'd5)  
        selcnt <= 4'd0;       
    else
	    selcnt <= selcnt + 1'b1;
 end
  

always@(posedge clk)//数码管位选显示,如果5位！！！
begin
 if(!rst)
  begin sel[0] <= 1;sel[1] <= 1;sel[2] <= 1;sel[3] <= 1;sel[4] <= 1;sel[5] <= 1;end
 else begin
       
		  
 
		  case(selcnt) //数码管位选计数器
		  4'd0    :  begin   sel[0] <= 0; sel[5] <= 1; seg[3] <=0;seg[2] <=0;seg[1] <=0;seg[0] <=0;end
        4'd1    :  begin   sel[1] <= 0; sel[0] <= 1; seg[3] <=0;seg[2] <=0;seg[1] <=1;seg[0] <=0; end
        4'd2    :  begin   sel[2] <= 0; sel[1] <= 1; seg[3] <=0;seg[2] <=0;seg[1] <=0;seg[0] <=0;end  
        4'd3    :  begin   sel[3] <= 0; sel[2] <= 1; seg[3] <=0;seg[2] <=1;seg[1] <=1;seg[0] <=0;end
        4'd4    :  begin   sel[4] <= 0; sel[3] <= 1; seg[3] <=0;seg[2] <=0;seg[1] <=0;seg[0] <=0; end
        4'd5    :  begin   sel[5] <= 0; sel[4] <= 1; seg[3] <=0;seg[2] <=1;seg[1] <=0;seg[0] <=1; end
		 
		  
        default : begin sel[0] <= 0;sel[1] <= 0;sel[2] <= 0;sel[3] <= 0; end
        endcase
end
end
 endmodule

w1w2w3w4高电平有效，ABCD低电平有效。学号自行修改。

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