SV学习笔记（8）

学习目标：

实验2
SV绿皮书第六章：随机化

学习内容：

1.波形分析
实验1—4波形（数据空闲交替）

实验2----1波形（数据空闲交替）

实验2–1+波形（数据连续发送，加了接口时钟块延迟）----实验2–1/1+波形ready信号变化？----只于fifo满有关

实验2—2-----仿真结束（fork-join 的基本功能和使用方法）

initial  begin
	basic_test();
	burst_test();
	fifo_full_test();
	$display("*****************all of tests have been finished********************");
    $finish();
end

task  automatic  basic_test();
	chnl0_gen.initialize(0);		//chnl0_gen为generator例化---数据id，
	chnl1_gen.initialize(1);
	chnl2_gen.initialize(2);
	chnl0_init.set_name("chnl0_init");		//chnl0_init为发生器例化
    chnl1_init.set_name("chnl1_init");
    chnl2_init.set_name("chnl2_init");
    chnl0_init.set_idle_cycles($urandom_range(1, 3));
    chnl1_init.set_idle_cycles($urandom_range(1, 3));
    chnl2_init.set_idle_cycles($urandom_range(1, 3));
    $display("basic_test initialized components");
    wait (rstn === 1'b1);
    repeat(5) @(posedge clk);
    $display("basic_test started testing DUT");

	fork
		repeat(100)  chnl0_init.chnl_write(chnl0_gen.get_data());
		repeat(100) chnl1_init.chnl_write(chnl1_gen.get_data());
        repeat(100) chnl2_init.chnl_write(chnl2_gen.get_data());
    join
    fork
    	wait(chnl0_init.intf.ch_margin=='h20);    //6'd32='h20为fifo存储空间,等于0为写满
    	wait(chnl1_init.intf.ch_margin == 'h20);
        wait(chnl2_init.intf.ch_margin == 'h20);     //等通道fifo写满
    join
    $display("basic_test finished testing DUT");
endtask

task automatic burst_test();
    chnl0_gen.initialize(0);
    chnl1_gen.initialize(1);
    chnl2_gen.initialize(2);
    chnl0_init.set_name("chnl0_init");
    chnl1_init.set_name("chnl1_init");
    chnl2_init.set_name("chnl2_init");
    chnl0_init.set_idle_cycles(0);				//连续发送，空闲时间为0
    chnl1_init.set_idle_cycles(0);
    chnl2_init.set_idle_cycles(0);
    $display("basic_test initialized components");
    wait (rstn === 1'b1);
    repeat(5) @(posedge clk);
	fork
		begin
			repeat(500) chnl0_init.chnl_write(chnl0_gen.get_data());
			chnl0_init.chnl_idle();
	  	end
      	begin
	    	repeat(500) chnl1_init.chnl_write(chnl1_gen.get_data());
			chnl1_init.chnl_idle();
	 	 end
	 	 begin
	   		repeat(500) chnl2_init.chnl_write(chnl2_gen.get_data());
			chnl2_init.chnl_idle();
	  	end	
	join
	fork
      wait(chnl0_init.intf.ch_margin == 'h20);
      wait(chnl1_init.intf.ch_margin == 'h20);
      wait(chnl2_init.intf.ch_margin == 'h20);
    join
    $display("basic_test finished testing DUT");
  endtask

 task automatic fifo_full_test();
    // verification component initializationi
    chnl0_gen.initialize(0);
    chnl1_gen.initialize(1);
    chnl2_gen.initialize(2);
    chnl0_init.set_name("chnl0_init");
    chnl1_init.set_name("chnl1_init");
    chnl2_init.set_name("chnl2_init");
    chnl0_init.set_idle_cycles(0);
    chnl1_init.set_idle_cycles(0);
    chnl2_init.set_idle_cycles(0);
    $display("fifo_full_test started testing DUT");
    fork: fork_all_run
	  forever chnl0_init.chnl_write(chnl0_gen.get_data());
	  forever chnl1_init.chnl_write(chnl1_gen.get_data());
	  forever chnl2_init.chnl_write(chnl2_gen.get_data());
    join_none
    $display("fifo_full_test: 3 initiators running now");

    $display("fifo_full_test: waiting 3 channel fifos to be full");
    fork
      wait(chnl0_init.intf.ch_margin == 0);
      wait(chnl1_init.intf.ch_margin == 0);
      wait(chnl2_init.intf.ch_margin == 0);
    join
    $display("fifo_full_test: 3 channel fifos have reached full");

    $display("fifo_full_test: stop 3 initiators running");
    disable fork_all_run;
    $display("fifo_full_test: set and ensure all agents' initiator are idle state");
    fork
      chnl0_init.chnl_idle();
      chnl1_init.chnl_idle();
      chnl2_init.chnl_idle();
    join

    $display("fifo_full_test waiting DUT transfering all of data");
    fork
      wait(chnl0_init.intf.ch_margin == 'h20);
      wait(chnl1_init.intf.ch_margin == 'h20);
      wait(chnl2_init.intf.ch_margin == 'h20);
    join
    $display("fifo_full_test: 3 channel fifos have transferred all data");

    $display("fifo_full_test finished testing DUT");
  endtask

实验2—TB3：类的例化和类的成员（module全部换成类）

interface chnl_intf(input clk, input rstn);
  logic [31:0] ch_data;
  logic        ch_valid;
  logic        ch_ready;
  logic [ 5:0] ch_margin;
  clocking drv_ck @(posedge clk);
    default input #1ns output #1ns;
    output ch_data, ch_valid;
    input ch_ready, ch_margin;
  endclocking
endinterface

class chnl_trans;
	int  data;
	int  id;
	int	 num;
endclass

问题：

学习时间：

早：9-11.30
中：15-17