AM335x SPL

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最新推荐文章于 2022-07-16 15:55:00 发布

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AM335x SPL

一、

AM335x bootloader ：

1st stage：RBL （ROM）

2st stage：SPL （内部RAM：0x402f0400）

3st stage：U-Boot （一般外部DDR）

SPL是bootloader的第二部分，由RBL引导运行，主要目的就是引导U-Boot运行。

SPL也叫MLO，一般存放在SD或者Nand中。其中，在Nand中要求存放在从第一个block开始的4个block中，因为RBL会从第一个 block开始查找SPL，如果第一个失败后，会从第二个block开始继续查找，直到第四个block查找完毕，因此，SPL必须放在Nand从第一个 block开始的4个block中，SPL在Nand中的偏移地址分别为0x0, 0x20000, 0x40000 和 0x60000。U-Boot从第五个block开始存放，即0x80000。假设Nand的block size为128K，则分布图如下：

+------------+-->0x00000000-> SPL start (SPL copy on 1st block)
| |
| |-->0x0001FFFF-> SPL end
| |-->0x00020000-> SPL.backup1 start (SPL copy on 2nd block)
| |
| |-->0x0003FFFF-> SPL.backup1 end
| |-->0x00040000-> SPL.backup2 start (SPL copy on 3rd block)
| |
| |-->0x0005FFFF-> SPL.backup2 end
| |-->0x00060000-> SPL.backup3 start (SPL copy on 4th block)
| |
| |-->0x0007FFFF-> SPL.backup3 end
| |-->0x00080000-> U-Boot start
| |
| |-->0x002BFFFF-> U-Boot end
| |-->0x00260000-> ENV start
| |
| |
| |-->0x0027FFFF-> ENV end
| |-->0x00280000-> Linux Kernel start
| |
| |
| |
| |
| |-->0x0077FFFF-> Linux Kernel end
| |-->0x00780000-> File system start
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
+------------+-->0x10000000-> NAND end (Free end)

二、

SPL代码分析:

分析SPL代码,首先要看一下SPL目录下的Makefile文件,在Makefile中:

CONFIG_SPL_BUILD := y
export CONFIG_SPL_BUILD

这个宏定义用于打开U-boot代码里有关SPL部分的分支.

另外,Makefile还交代了SPL涉及到的相关代码文件:

主要有 u-boot-2011.09-psp04.06.00.08\arch\arm\cpu\armv7

u-boot-2011.09-psp04.06.00.08\arch\arm\lib

u-boot-2011.09-psp04.06.00.08\drivers

等.

除了通过Makefile分析SPL涉及到的相关代码文件外，还可以简单的通过在编译SPL时,在make 后加上O=am335x来将所有的.o文件归类在一起,在am335x/spl目录下：

通过上面的图，可以很清楚的了解SPL在编译时涉及到U-Boot中的代码文件

# Linker Script
ifdef CONFIG_SPL_LDSCRIPT
# need to strip off double quotes
LDSCRIPT := $(addprefix $(SRCTREE)/,$(subst ",,$(CONFIG_SPL_LDSCRIPT)))
endif

该处指定了SPL的链接脚本文件

CONFIG_SPL_LDSCRIPT 在 u-boot-2011.09-psp04.06.00.08\include\configs\Am335x_evm.h中定义：
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"

所以SPL的链接脚本是u-boot-2011.09-psp04.06.00.08\arch\arm\cpu\armv7\omap-common\u-boot-spl.lds

在u-boot-spl.lds中，空间分配如下：

MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }

其中，CONFIG_SPL_TEXT_BASE、CONFIG_SPL_MAX_SIZE、CONFIG_SPL_BSS_START_ADDR、CONFIG_SPL_BSS_MAX_SIZE都是在Am335x_evm.h定义：

#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (101 * 1024)

#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */

因此，实际的空间分配如下：

MEMORY { .sram : ORIGIN = 0x402F0400, LENGTH = (101 * 1024) }
MEMORY { .sdram : ORIGIN = 0x80000000, LENGTH = 0x80000 }

SRAM从0x402F0400开始用于存放.TEXT段、.rodata段、.data段内容

SDRAM从0x80000000开始用于存放.bss段内容

三、

由Makefile可知，SPL的入口在u-boot-2011.09-psp04.06.00.08\arch\arm\cpu\armv7\start.S中

SPL的功能无非是设置MPU的Clock、PLL，Power，DDR，Uart，Pin Mux，完成对U-Boot的引导的工作，所以SPL board port主要针对以上几点。

在start.S中：

cpu_init_crit

board_init_f

board_init_r

cpu_init_crit

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif

其中，CONFIG_SKIP_LOWLEVEL_INIT 在am335x_evm.h中定义：

/* Since SPL did all of this for us, we don't need to do it twice. */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

由此可知，cpu_init_crit 只在SPL中才进行编译，U-Boot中不编译，避免了同样的内容重复设置，比如DDR等。

cpu_init_crit

----> lowlevel_init (u-boot-2011.09-psp04.06.00.08\arch\arm\cpu\armv7\omap-common\lowlevel_init.S)

----> s_init (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Evm.c)

----> 关看门狗

----> pll_init(); //PLL和时钟设置

----> rtc32k_enable(); //使能RTC

----> 串口设置

----> init_timer();

----> preloader_console_init();

----> I2C0初始化，读EEPROM

----> DDR设置(DDR2\DDR3)

pll_init(); (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Pll.c)

----> mpu_pll_config(MPUPLL_M_500); (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Pll.c)

//设置MPU的频率为500MHz，可以修改

----> core_pll_config(); (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Pll.c)

//设置CORE频率为1GHz

----> per_pll_config(); (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Pll.c)

//设置外设频率为960MHz

----> interface_clocks_enable(); (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Pll.c)

//使能内部连接模块的时钟

----> power_domain_transition_enable(); (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Pll.c)

//使能模块电源

----> per_clocks_enable(); (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Pll.c)

//使能外设模块的时钟

在u-boot-2011.09-psp04.06.00.08\arch\arm\include\asm\arch-ti81xx\Clocks_am335x.h中，定义了所有时钟频率：

/* Put the pll config values over here */

#define OSC 24 /* 外部晶振为24MHz */

/* MAIN PLL Fdll = 1 GHZ, */
#define MPUPLL_M_500    500    /* 125 * n */
#define MPUPLL_M_550    550    /* 125 * n */
#define MPUPLL_M_600    600    /* 125 * n */
#define MPUPLL_M_720    720    /* 125 * n */

#define MPUPLL_N 23 /* (n -1 ) */
#define MPUPLL_M2 1

/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000 /* 125 * n */
#define COREPLL_N 23 /* (n -1 ) */

#define COREPLL_M4    10    /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5    8    /* CORE_CLKOUTM5 = 250 MHZ */
#define COREPLL_M6    4    /* CORE_CLKOUTM6 = 500 MHZ */

/*
* USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
* frequency needs to be set to 960 MHZ. Hence,
* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
*/
#define PERPLL_M    960
#define PERPLL_N    23
#define PERPLL_M2    5

/* DDR Freq is 266 MHZ for now*/
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
#define DDRPLL_M    266
#define DDRPLL_N    23
#define DDRPLL_M2    1

MPU PLL结构：

配置MPU PLL：

代码如下：

void mpu_pll_config(int mpupll_M)
{
u32 clkmode, clksel, div_m2;

    clkmode = readl(CM_CLKMODE_DPLL_MPU);
    clksel = readl(CM_CLKSEL_DPLL_MPU);
    div_m2 = readl(CM_DIV_M2_DPLL_MPU);

/* Set the PLL to bypass Mode */
writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_MPU);

while(readl(CM_IDLEST_DPLL_MPU) != 0x00000100);

    clksel = clksel & (~0x7ffff);
    clksel = clksel | ((mpupll_M << 0x8) | MPUPLL_N);
    writel(clksel, CM_CLKSEL_DPLL_MPU);

    div_m2 = div_m2 & ~0x1f;
    div_m2 = div_m2 | MPUPLL_M2;
    writel(div_m2, CM_DIV_M2_DPLL_MPU);

clkmode = clkmode | 0x7;
writel(clkmode, CM_CLKMODE_DPLL_MPU);

while(readl(CM_IDLEST_DPLL_MPU) != 0x1);
}

Core PLL 结构：

配置Core PLL：

代码如下：

static void core_pll_config(void)
{
u32 clkmode, clksel, div_m4, div_m5, div_m6;

    clkmode = readl(CM_CLKMODE_DPLL_CORE);
    clksel = readl(CM_CLKSEL_DPLL_CORE);
    div_m4 = readl(CM_DIV_M4_DPLL_CORE);
    div_m5 = readl(CM_DIV_M5_DPLL_CORE);
    div_m6 = readl(CM_DIV_M6_DPLL_CORE);

/* Set the PLL to bypass Mode */
writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_CORE);

while(readl(CM_IDLEST_DPLL_CORE) != 0x00000100);

    clksel = clksel & (~0x7ffff);
    clksel = clksel | ((COREPLL_M << 0x8) | COREPLL_N);
    writel(clksel, CM_CLKSEL_DPLL_CORE);

    div_m4 = div_m4 & ~0x1f;
    div_m4 = div_m4 | COREPLL_M4;
    writel(div_m4, CM_DIV_M4_DPLL_CORE);

    div_m5 = div_m5 & ~0x1f;
    div_m5 = div_m5 | COREPLL_M5;
    writel(div_m5, CM_DIV_M5_DPLL_CORE);

    div_m6 = div_m6 & ~0x1f;
    div_m6 = div_m6 | COREPLL_M6;
    writel(div_m6, CM_DIV_M6_DPLL_CORE);

clkmode = clkmode | 0x7;
writel(clkmode, CM_CLKMODE_DPLL_CORE);

while(readl(CM_IDLEST_DPLL_CORE) != 0x1);
}

Peripheral PLL 结构

配置Peripheral PLL：

代码如下：

static void per_pll_config(void)
{
u32 clkmode, clksel, div_m2;

    clkmode = readl(CM_CLKMODE_DPLL_PER);
    clksel = readl(CM_CLKSEL_DPLL_PER);
    div_m2 = readl(CM_DIV_M2_DPLL_PER);

/* Set the PLL to bypass Mode */
writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_PER);

while(readl(CM_IDLEST_DPLL_PER) != 0x00000100);

    clksel = clksel & (~0x7ffff);
    clksel = clksel | ((PERPLL_M << 0x8) | PERPLL_N);
    writel(clksel, CM_CLKSEL_DPLL_PER);

    div_m2 = div_m2 & ~0x7f;
    div_m2 = div_m2 | PERPLL_M2;
    writel(div_m2, CM_DIV_M2_DPLL_PER);

clkmode = clkmode | 0x7;
writel(clkmode, CM_CLKMODE_DPLL_PER);

while(readl(CM_IDLEST_DPLL_PER) != 0x1);
}

串口设置(u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Evm.c)

设置所使用串口的基地址、复位串口、关闭 smart idle。

u32 uart_base = DEFAULT_UART_BASE; // 默认使用的串口是UART0，基地址为 0x44E0_9000

enable_uart0_pin_mux(); // 配置uart0相关引脚为 UART模式

同样可以设置为其他串口，比如IA Motor Control Board就是使用的UART3，只要修改上面两步就可以了

init_timer(); (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Evm.c)

这里初始化的是timer2，在之前 pll_init();----> per_clocks_enable(); 中使能的也是timer2，使用24MHz OSC

preloader_console_init(); (u-boot-2011.09-psp04.06.00.08\arch\arm\cpu\armv7\omap-common\Spl.c)

主要是对串口波特率的设置，以及串口终端打印信息。BeagleBone板上使用的是USB转串口芯片，串口驱动drivers\serial\serial.c 、drivers\serial\ns16550.c

I2C0初始化，读EEPROM (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Evm.c)

i2c0接了一个eeprom ( CAT24C256W 256K *8 )，i2c读取eeprom的数据到 header 结构体，header 结构体原型为

struct am335x_baseboard_id {
    unsigned int magic;
    char name[8];
    char version[4];
    char serial[12];
    char config[32];
    char mac_addr[NO_OF_MAC_ADDR][ETH_ALEN];
};

BeagleBone开发板提供的eeprom信息如下：

enable_i2c0_pin_mux(); // 配置i2c0相关引脚为 I2C模式

i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);//i2c初始化，速度为标准速度100000，从设备

if (read_eeprom()) {

printf("read_eeprom() failure. continuing with ddr3\n");

} //读eeprom到 header 结构体，会判断magic是否为上表中提供的0xEE3355AA

DDR设置(DDR2\DDR3) (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Evm.c)

u32 is_ddr3 = 0;
if (!strncmp("A335X_SK", header.name, 8)) {
is_ddr3 = 1;

    /*
     * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
     * This is safe enough to do on older revs.
     */
    enable_gpio0_7_pin_mux();
    gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
    gpio_direction_output(GPIO_DDR_VTT_EN, 1);

//通过gpio0_7输出高电平来触发VTT稳压器，从而产生VTT_DDR电压
}

if(is_ddr3 == 1){
    ddr_pll_config(303);
    config_am335x_ddr3();
}
else {
    ddr_pll_config(266);
    config_am335x_ddr2();
}

在设置DDR之前，要先判断是DDR2（变量is_ddr3 = 0）还是DDR3（变量is_ddr3 = 1），TI推出的开发板目前只有A335X_StarterKit支持DDR3，其余的均是DDR2，包括BeagleBone

一开始默认为DDR2（设置is_ddr3 = 0），但是通过比对header.name是否为A335X_SK，来确定DDR3（设置is_ddr3 = 1）

根据不同的DDR来进行相应的DDR配置，主要有4个部分需要设置，如下：

DDR PLL 结构：

配置DDR PLL:

代码如下：

ddr_pll_config(); (u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Pll.c);

//配置ddr的时钟频率，DDR2为266MHz，DDR3为303MHz

void ddr_pll_config(unsigned int ddrpll_M)
{
u32 clkmode, clksel, div_m2;

    clkmode = readl(CM_CLKMODE_DPLL_DDR);
    clksel = readl(CM_CLKSEL_DPLL_DDR);
    div_m2 = readl(CM_DIV_M2_DPLL_DDR);

    /* Set the PLL to bypass Mode */
    clkmode = (clkmode & 0xfffffff8) | 0x00000004;
    writel(clkmode, CM_CLKMODE_DPLL_DDR);

while ((readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);

    clksel = clksel & (~0x7ffff);
    clksel = clksel | ((ddrpll_M << 0x8) | DDRPLL_N);
    writel(clksel, CM_CLKSEL_DPLL_DDR);

    div_m2 = div_m2 & 0xFFFFFFE0;
    div_m2 = div_m2 | DDRPLL_M2;
    writel(div_m2, CM_DIV_M2_DPLL_DDR);

clkmode = (clkmode & 0xfffffff8) | 0x7;
writel(clkmode, CM_CLKMODE_DPLL_DDR);

while ((readl(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x1);
}

config_am335x_ddr2();

四、

分类：嵌入式

board_init_f

【入口函数】start.s （u-boot-2011.09-psp04.06.00.08\arch\arm\cpu\armv7\start.S）

/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
    ldr    sp, =(CONFIG_SYS_INIT_SP_ADDR)
    bic    sp, sp, #7 /* 8-byte alignment for ABI compliance */
    ldr    r0,=0x00000000
    bl    board_init_f

设置栈指针，跳转到board_init_f

内部RAM分配如下：

1KB 0x402F0000 à

（保护） 0x402F03FFà

0x402F0400 à

SPL

（109KB）

0x4030B7FFà

SP 0x4030B800à

（10KB） 0x4030DFFFà

RBL 0x4030E000à

（8KB） 0x4030FFFFà

board_init_f （u-boot-2011.09-psp04.06.00.08\arch\arm\cpu\armv7\omap-common\Spl.c）

void board_init_f(ulong dummy)

{

* We call relocate_code() with relocation target same as the

* CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting

* skipped. Instead, only .bss initialization will happen. That's

* all we need

debug(">>board_init_f()\n");

relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);

}

代码重定位 relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);

其中3个变量分别对应r0,r1,r2：

r0 : CONFIG_SPL_STACK = 0x4030B7FC

r1 : &gdata

r2 : CONFIG_SPL_TEXT_BASE = 0x402F0400

relocate_code （u-boot-2011.09-psp04.06.00.08\arch\arm\cpu\armv7\start.S）

/*------------------------------------------------------------------------------*/

* void relocate_code (addr_sp, gd, addr_moni)

* This "function" does not return, instead it continues in RAM

* after relocating the monitor code.

.globl relocate_code

relocate_code:

mov r4, r0 /* save addr_sp */

mov r5, r1 /* save addr of gd */

mov r6, r2 /* save addr of destination */

/* Set up the stack */

stack_setup:

mov sp, r4

adr r0, _start

cmp r0, r6

moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */

beq clear_bss /* skip relocation */

mov r1, r6 /* r1 <- scratch for copy_loop */

ldr r3, _image_copy_end_ofs

add r2, r0, r3 /* r2 <- source end address */

copy_loop:

ldmia r0!, {r9-r10} /* copy from source address [r0] */

stmia r1!, {r9-r10} /* copy to target address [r1] */

cmp r0, r2 /* until source end address [r2] */

blo copy_loop

#ifndef CONFIG_SPL_BUILD

* fix .rel.dyn relocations

ldr r0, _TEXT_BASE /* r0 <- Text base */

sub r9, r6, r0 /* r9 <- relocation offset */

ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */

add r10, r10, r0 /* r10 <- sym table in FLASH */

ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

add r2, r2, r0 /* r2 <- rel dyn start in FLASH */

ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */

add r3, r3, r0 /* r3 <- rel dyn end in FLASH */

fixloop:

ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */

add r0, r0, r9 /* r0 <- location to fix up in RAM */

ldr r1, [r2, #4]

and r7, r1, #0xff

cmp r7, #23 /* relative fixup? */

beq fixrel

cmp r7, #2 /* absolute fixup? */

beq fixabs

/* ignore unknown type of fixup */

b fixnext

fixabs:

/* absolute fix: set location to (offset) symbol value */

mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */

add r1, r10, r1 /* r1 <- address of symbol in table */

ldr r1, [r1, #4] /* r1 <- symbol value */

add r1, r1, r9 /* r1 <- relocated sym addr */

b fixnext

fixrel:

/* relative fix: increase location by offset */

ldr r1, [r0]

add r1, r1, r9

fixnext:

str r1, [r0]

add r2, r2, #8 /* each rel.dyn entry is 8 bytes */

cmp r2, r3

blo fixloop

b clear_bss

_rel_dyn_start_ofs:

.word __rel_dyn_start - _start

_rel_dyn_end_ofs:

.word __rel_dyn_end - _start

_dynsym_start_ofs:

.word __dynsym_start - _start

#endif /* #ifndef CONFIG_SPL_BUILD */

board_init_r

【入口函数】start.s （u-boot-2011.09-psp04.06.00.08\arch\arm\cpu\armv7\start.S）

* We are done. Do not return, instead branch to second part of board

* initialization, now running from RAM.

jump_2_ram:

* If I-cache is enabled invalidate it

#ifndef CONFIG_SYS_ICACHE_OFF

mcr p15, 0, r0, c7, c5, 0 @ invalidate icache

mcr p15, 0, r0, c7, c10, 4 @ DSB

mcr p15, 0, r0, c7, c5, 4 @ ISB

#endif

ldr r0, _board_init_r_ofs

adr r1, _start

add lr, r0, r1

add lr, lr, r9

/* setup parameters for board_init_r */

mov r0, r5 /* gd_t */

mov r1, r6 /* dest_addr */

/* jump to it ... */

mov pc, lr

_board_init_r_ofs:

.word board_init_r - _start

跳转到内部RAM执行board_init_r

board_init_r （u-boot-2011.09-psp04.06.00.08\arch\arm\cpu\armv7\omap-common\Spl.c）

void board_init_r(gd_t *id, ulong dummy)

{

u32 boot_device;

debug(">>spl:board_init_r()\n");

mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,

CONFIG_SYS_SPL_MALLOC_SIZE);

timer_init();

i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

#ifdef CONFIG_SPL_BOARD_INIT //宏在Am335x_evm.h中打开

spl_board_init();

#endif

boot_device = omap_boot_device();

debug("boot device - %d\n", boot_device);

switch (boot_device) {

#ifdef CONFIG_SPL_MMC_SUPPORT

case BOOT_DEVICE_MMC1:

case BOOT_DEVICE_MMC2:

spl_mmc_load_image();

break;

#endif

#ifdef CONFIG_SPL_NAND_SUPPORT

case BOOT_DEVICE_NAND:

spl_nand_load_image();

break;

#endif

#ifdef CONFIG_SPL_YMODEM_SUPPORT

case BOOT_DEVICE_UART:

spl_ymodem_load_image();

break;

#endif

#ifdef CONFIG_SPL_SPI_SUPPORT

case BOOT_DEVICE_SPI:

spi_boot();

break;

#endif

#ifdef CONFIG_SPL_ETH_SUPPORT

case BOOT_DEVICE_CPGMAC:

spl_eth_load_image();

break;

#endif

default:

printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device);

hang();

break;

}

switch (spl_image.os) {

case IH_OS_U_BOOT:

debug("Jumping to U-Boot\n");

jump_to_image_no_args();

break;

default:

puts("Unsupported OS image.. Jumping nevertheless..\n");

jump_to_image_no_args();

}

board_init_r 流程

à mem_malloc_init //初始化内存，设为0，0x80208000开始，大小1MB

à timer_init(); //定时器初始化，使用timer2，外部时钟源24MHz

à i2c_init //i2c初始化，速度为标准速度100000，从设备

à spl_board_init(); //spl板级初始化

à boot_device = omap_boot_device(); //获取启动模式

à switch (boot_device)

à spl_mmc_load_image(); ? //mmc载入镜像

à spl_nand_load_image(); //nand载入镜像

à spl_ymodem_load_image(); //ymode载入镜像

à spi_boot(); //spi载入镜像

à spl_eth_load_image(); //以太网载入镜像

à hang(); //挂起

à jump_to_image_no_args(); //跳转到uboot的入口地址entry_point执行

spl_board_init(); （u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Evm.c）

void spl_board_init(void)

{

uchar pmic_status_reg;

/* init board_id, configure muxes */

board_init(); （u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Evm.c）

if (!strncmp("A335BONE", header.name, 8)) {

/* BeagleBone PMIC Code */

if (i2c_probe(TPS65217_CHIP_PM))

return;

if (tps65217_reg_read(STATUS, &pmic_status_reg))

return;

/* Increase USB current limit to 1300mA */

if (tps65217_reg_write(PROT_LEVEL_NONE, POWER_PATH,

USB_INPUT_CUR_LIMIT_1300MA,

USB_INPUT_CUR_LIMIT_MASK))

printf("tps65217_reg_write failure\n");

/* Only perform PMIC configurations if board rev > A1 */

if (!strncmp(header.version, "00A1", 4))

return;

/* Set DCDC2 (MPU) voltage to 1.275V */

if (tps65217_voltage_update(DEFDCDC2,

DCDC_VOLT_SEL_1275MV)) {

printf("tps65217_voltage_update failure\n");

return;

}

/* Set LDO3, LDO4 output voltage to 3.3V */

if (tps65217_reg_write(PROT_LEVEL_2, DEFLS1,

LDO_VOLTAGE_OUT_3_3, LDO_MASK))

printf("tps65217_reg_write failure\n");

if (tps65217_reg_write(PROT_LEVEL_2, DEFLS2,

LDO_VOLTAGE_OUT_3_3, LDO_MASK))

printf("tps65217_reg_write failure\n");

if (!(pmic_status_reg & PWR_SRC_AC_BITMASK)) {

printf("No AC power, disabling frequency switch\n");

return;

}

/* Set MPU Frequency to 720MHz */

mpu_pll_config(MPUPLL_M_720);

} else {

uchar buf[4];

* EVM PMIC code. All boards currently want an MPU voltage

* of 1.2625V and CORE voltage of 1.1375V to operate at

* 720MHz.

if (i2c_probe(PMIC_CTRL_I2C_ADDR))

return;

/* VDD1/2 voltage selection register access by control i/f */

if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))

return;

buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;

if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))

return;

if (!voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) &&

!voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3))

/* Frequency switching for OPP 120 */

mpu_pll_config(MPUPLL_M_720);

}

#endif

spl_board_init();

à board_init(); //板级初始化

à PMIC //电源管理

à AM335x BeagleBone TPS65217

à mpu_pll_config(MPUPLL_M_720); //设MPU频率为720MHz

à 其他板卡（TPS65910）

à mpu_pll_config(MPUPLL_M_720);

board_init(); （u-boot-2011.09-psp04.06.00.08\board\ti\am335x\Evm.c）

int board_init(void)

{

/* Configure the i2c0 pin mux */

enable_i2c0_pin_mux();

i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

if (read_eeprom())

goto err_out;

detect_daughter_board();

if (!strncmp("SKU#01", header.config, 6)) {

board_id = GP_BOARD;

detect_daughter_board_profile();

} else if (!strncmp("SKU#02", header.config, 6)) {

board_id = IA_BOARD;

detect_daughter_board_profile();

} else if (!strncmp("SKU#03", header.config, 6)) {

board_id = IPP_BOARD;

} else if (!strncmp("A335BONE", header.name, 8)) {

board_id = BONE_BOARD;

profile = 1; /* profile 0 is internally considered as 1 */

daughter_board_connected = 0;

} else if (!strncmp("A335X_SK", header.name, 8)) {

board_id = SK_BOARD;

profile = 1; /* profile 0 is internally considered as 1 */

daughter_board_connected = 0;

} else {

printf("Did not find a recognized configuration, "

"assuming General purpose EVM in Profile 0 with "

"Daughter board\n");

board_id = GP_BOARD;

profile = 1; /* profile 0 is internally considered as 1 */

daughter_board_connected = 1;

}

configure_evm_pin_mux(board_id, header.version, profile, daughter_board_connected);

#ifndef CONFIG_SPL_BUILD

board_evm_init();

#endif

gpmc_init();

return 0;

err_out:

* When we cannot use the EEPROM to determine what board we

* are we assume BeagleBone currently as we have not yet

* programmed the EEPROMs.

board_id = BONE_BOARD;

profile = 1; /* profile 0 is internally considered as 1 */

daughter_board_connected = 1;

configure_evm_pin_mux(board_id, header.version, profile, daughter_board_connected);

#ifndef CONFIG_SPL_BUILD

board_evm_init();

#endif

gpmc_init();

return 0;

}

board_init();

à设置、初始化I2C，读EEPROM

à有EEPROM

à根据读到的信息，判断板卡型号GP_BOARD、IA_BOARD、IPP_BOARD（板卡有两部分组成）

BONE_BOARD、SK_BOARD（板卡单独一个整体）

à根据不同型号，配置相应的引脚

configure_evm_pin_mux(board_id, header.version, profile, daughter_board_connected);

à gpmc_init(); //GPMC初始化，默认为8bit nand，起始地址和大小在Am335x_evm.h定义

à无EEPROM

à假设为有两部分组成的BONE_BOARD，并进行引脚配置

configure_evm_pin_mux(board_id, header.version, profile, daughter_board_connected);

à gpmc_init();

configure_evm_pin_mux(board_id, header.version, profile, daughter_board_connected); //引脚配置

代码给出的引脚配置有以下几种，分别对应不同的评估板：

beaglebone_pin_mux,

general_purpose_evm_pin_mux,

ia_motor_control_evm_pin_mux,

ip_phone_evm_pin_mux,

low_cost_evm_pin_mux,

sk_evm_pin_mux,

以beaglebone、starterkit为例：

static struct evm_pin_mux beaglebone_pin_mux[] = {

{uart0_pin_mux, PROFILE_ALL, DEV_ON_BASEBOARD},

{i2c1_pin_mux, PROFILE_ALL & ~PROFILE_2 & ~PROFILE_4, DEV_ON_BASEBOARD},

#ifdef CONFIG_NAND

{nand_pin_mux, PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3, DEV_ON_DGHTR_BRD},

#endif

#ifndef CONFIG_NO_ETH

{mii1_pin_mux, PROFILE_ALL, DEV_ON_BASEBOARD},

#endif

#ifdef CONFIG_MMC

{mmc0_pin_mux, PROFILE_ALL, DEV_ON_BASEBOARD},

{mmc1_pin_mux, PROFILE_ALL, DEV_ON_BASEBOARD},

#endif

#ifdef CONFIG_SPI

{spi0_pin_mux, PROFILE_2, DEV_ON_DGHTR_BRD},

#endif

{0},

};

Startkit没有nand，只有mmc，有两个千兆网

static struct evm_pin_mux sk_evm_pin_mux[] = {

{uart0_pin_mux, PROFILE_ALL, DEV_ON_BASEBOARD},

#ifdef CONFIG_MMC

{mmc0_sk_pin_mux, PROFILE_ALL, DEV_ON_BASEBOARD},

#endif

#ifndef CONFIG_NO_ETH

{rgmii1_pin_mux, PROFILE_ALL, DEV_ON_BASEBOARD},

{rgmii2_pin_mux, PROFILE_ALL, DEV_ON_BASEBOARD},

#endif

{0},

};

http://blog.chinaunix.NET/uid-12077574-id-3527521.html

jump_to_image_no_args();

跳转到uboot的入口地址entry_point执行，这个entry_point哪里来？是有u-boot.img头部信息提供。

至此，整个AM335x SPL代码全部分析完毕，主要还是这3个函数：

? cpu_init_crit //cpu级初始化

? board_init_f //代码重定位

? board_init_r //板级初始化，并执行最终u-boot

bian1029

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AM335x SPL

AM335x SPL一、AM335x bootloader ：1st stage：RBL （ROM）2st stage：SPL （内部RAM：0x402f0400）3st stage：U-Boot （一般外部DDR）SPL是bootloader的第二部分，由RBL引导运行，主要目的就是引导U-Boot运行。SPL也叫MLO，一般存放在SD
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