FPGA UART TX,简单的FPGA串口发送模块

串口资料大家网上找找,我也是个新手,欢迎交流.

//UART发送模块,波特率9600
//陈鹏
//20120118 	

module UART_TX	(
						sys_clk,//系统时钟输入
						reset_n,//异步复位输入
						Tx,//数据线
						TxData,//发送数据的数据线
						Tx_Start,//启动发送信号
						TX_STATE//发送器的状态
					);
					
				
					
	input		sys_clk,reset_n,Tx_Start;
	input [7 : 0] TxData;
	output	Tx,TX_STATE;
	reg 		Tx,TX_STATE;
	
	parameter SYS_CLK = 20000000;//系统时钟
	parameter Tx_CLK = 9600;//9600bps
	parameter TxDATA_W = 12;//波特率时钟发生器分频寄存器位宽
	parameter TXCLK_DATA = SYS_CLK / Tx_CLK - 1;//波特率分频器时钟分频值
	
	//波特率时钟发生器
	reg	[TxDATA_W-1 : 0] clk_cnt;
	reg	EN_TXCLK;//使能发送时钟
	wire	TX_CLK;//发送波特率时钟
	always @ (posedge sys_clk or negedge reset_n)
		if(!reset_n)
			clk_cnt <= 12'd0;	
		else if(!EN_TXCLK)//不需要使能时钟
			clk_cnt <= 12'd0;	
		else if(clk_cnt == TXCLK_DATA)
			clk_cnt <= 12'd0;
		else
			clk_cnt <= clk_cnt + 1'b1;
			
	assign TX_CLK = (clk_cnt == 0);//产生接收时钟
	
	
	//发送控制状态机
	reg [3 : 0] TxState;
	reg [7 : 0] TxTemp;//存放需要发送的数据
	
	always @ (posedge sys_clk or negedge reset_n)
		if(!reset_n) begin
			TxState = 4'd0;
			TxTemp = 8'd0;
			TX_STATE = 1'b0;
			EN_TXCLK = 1'b0;
			end
		else if ((TxState == 0) && (TX_STATE == 0) && Tx_Start) begin//总线空闲,并且有开始信号,那么开始发送数据
			EN_TXCLK <= 1'b1;//使能发送时钟
			TxState <= 4'd1;//开始发送的第一个状态
			TX_STATE <= 1'd1;//发送忙
			TxTemp <= TxData;//载入需要发送的数据
			end
		else if(TX_CLK) begin
			case (TxState) //synthesis full_case
				4'd1	:	begin //发送起始位					
							Tx <= 1'b0;
							TxState <= 4'd2;
							end
				4'd2	:	begin //发送bit0			
							Tx <= TxTemp[0];
							TxState <= 4'd3;
							end
				4'd3	:	begin //发送bit1			
							Tx <= TxTemp[1];
							TxState <= 4'd4;
							end			
				4'd4	:	begin //发送bit2						
							Tx <= TxTemp[2];
							TxState <= 4'd5;
							end
				4'd5	:	begin //发送bit3						
							Tx <= TxTemp[3];
							TxState <= 4'd6;
							end
				4'd6	:	begin //发送bit4						
							Tx <= TxTemp[4];
							TxState <= 4'd7;
							end
				4'd7	:	begin //发送bit5						
							Tx <= TxTemp[5];
							TxState <= 4'd8;
							end
				4'd8	:	begin //发送bit6						
							Tx <= TxTemp[6];
							TxState <= 4'd9;
							end
				4'd9	:	begin //发送bit7						
							Tx <= TxTemp[7];
							TxState <= 4'd10;
							end
				4'd10	:	begin //发送奇偶校验位,随便发					
							Tx <= 1'b0;
							TxState <= 4'd11;
							end
				4'd11	:	begin //发送停止位,高电平					
							Tx <= 1'b1;
							TxState <= 4'd0;//进入空闲状态
							EN_TXCLK <= 1'b0;//发送波特率时钟停在
							TX_STATE <= 1'd0;//发送逻辑空闲
							end
				endcase
		end //end else if
						
			
endmodule