#define EMIFA_GBLCTL 0X01800000
#define EMIFA_CE0CTL 0X01800008
#define EMIFA_SDCTL 0X01800018
#define EMIFA_SDTIM 0X0180001C
#define EMIFA_SDEXT 0X01800020
#define SDRAM_ADDR 0x80000024
#define address 0x80000000
typedef float f32;
typedef int s32;
typedef unsigned int u32;
typedef short s16;
typedef unsigned short u16;
typedef unsigned char u8;
typedef signed char s8;
#include <stdio.h>
//============ main program ========================
void set_EMIFA();
void Write_sdram();
void Read_sdram();
void main()
{
set_EMIFA();
Write_sdram();
Read_sdram();
}
void set_EMIFA()
{
*(volatile u32*)EMIFA_GBLCTL=(u32)0x000520A4;//0x00000010; //indicates that ECLKOUT1 is enabled to clock and used to clock the SDRAM
*(volatile u32*)EMIFA_CE0CTL=(u32)0xFFFFFFD3;//0xFFFFFFDF; MTYPE=1101b 64bit-wide SDRAM
*(volatile u32*)EMIFA_SDCTL =(u32)0x5b116000; //0x5b116000 !!!! 63spra433b 0x57119000
// *(volatile u32*)EMIFA_SDTIM =(u32)0x00000446;//a value of 0x446 should be written to the refresh period field in the EMIF SDRAM timing register
// *(volatile u32*)EMIFA_SDEXT =(u32)0x0005452B; //0x0005452B*/
/**(volatile u32*)EMIFA_GBLCTL=(u32)0x000520a4; //0x000520a4: 1/2 EMIFA Clock
*(volatile u32*)EMIFA_CE0CTL=(u32)0xFFFFFFDF;
*(volatile u32*)EMIFA_SDCTL =(u32)0x47116000; //0x5b116000
*(volatile u32*)EMIFA_SDTIM =(u32)0x00000446;//a value of 0x446 should be written to the refresh period field in the EMIF SDRAM timing register
*(volatile u32*)EMIFA_SDEXT =(u32)0x00054549; */
}
void Write_sdram()
{
int i;
for(i =0;i<100;i++)
{
*((volatile u32 *)address + i) = i;
}
}
void Read_sdram()
{
int j,k,counter;
counter=0;
for(j =0;j<100;j++)
{
k=*((volatile u32 *)address + j);
if(k!=j)
counter++;
}
if(counter>0)printf("error rate is %d",counter/100);
else printf("operate correctly");
}