MSP432开发板串口调试


拿到MSP432P401R评估板v1.0(这个请注意一下,目前在德州仪器官网上找到的硬件原理图是v2.0,v1.0的串口所在的引脚是RXD,TXD引脚),先将串口调试好,便于下一步工作的展开。首先,查看TI提供的代码例子,这个例子就在TI的MSPWare代码包内。注释如下:

 

//******************************************************************************

//  MSP432P401 Demo - eUSCI_A0 UART echo at 9600 baud using BRCLK = 12MHz

//

// Description: This demo echoes back characters received via a PC serialport.

//  SMCLK/DCO is used as a clock source and the device is put in LPM3

//  Theauto-clock enable feature is used by the eUSCI and SMCLK is turned off

//  when theUART is idle and turned on when a receive edge is detected.

//  Note thatlevel shifte

MSP432 低功耗高性能并存10.1 Digital I/O Introduction The digital I/O features include: • Independently programmable individual I/Os • Any combination of input or output • Individually configurable interrupts for ports (available for certain ports only) • Independent input and output data registers • Individually configurable pullup or pulldown resistors • Wake-up capability from ultra-low power modes (available for certain ports only) • Individually configurable high drive I/Os (available for certain I/Os only) Devices within the family may have up to eleven digital I/O ports implemented (P1 to P10 and PJ). Most ports contain eight I/O lines; however, some ports may contain less (see the device-specific data sheet for ports available). Each I/O line is individually configurable for input or output direction, and each can be individually read or written. Each I/O line is individually configurable for pullup or pulldown resistors. Certain ports have interrupt and wake-up capability from ultra-low power modes (see device specific data sheet for ports with interrupt and wake-up capability). Each interrupt can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal. All interrupts are fed into an encoded Interrupt Vector register, allowing the application to determine which sub-pin of a port has generated the event. Individual ports can be accessed as byte-wide ports or can be combined into half-word-wide ports. Port pairs P1 and P2, P3 and P4, P5 and P6, P7 and P8, and so on, are associated with the names PA, PB, PC, PD, and so on, respectively. All port registers are handled in this manner with this naming convention. The main exception are the interrupt vector registers, for example, interrupts for ports P1 and P2 must be handled through P1IV and P2IV, PAIV does not exist. When writing to port PA with half-word operations, all 16 bits are written to the port. When writing to the lower byte of port PA using byte operations, the upper byte remains unchanged. Similarly, writing to the upper byte of port PA using byte instructions leaves the lower byte unchanged. When writing to a port that contains less than the maximum number of bits possible, the unused bits are don't care. Ports PB, PC, PD, PE, and PF behave similarly.
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