verilator生成.fit文件GTKwave无法读取

.fst文件是verilator独有波形文件，GTKwave无法读取可能是因为文件损坏（波形生成

中断）

rm Vtop__ALL.verilator_deplist.tmp
make[1]: Leaving directory '/home/verilator/2/obj_dir'

编译时添加

--fst

生成.fst文件

我的编译规则如下

verilator -Wall top.v sim.cpp --cc --trace-fst --exe --build 

top.v为顶层文件

sim.v为仿真文件（把vcd改为fst）如下

#include "verilated_fst_c.h" 

VerilatedFstC* tfp = new VerilatedFstC; 

tfp->open("wave.fst");

编译成功如下

rm Vtop__ALL.verilator_deplist.tmp
make[1]: Leaving directory '/home/wym/verilator/my-ver-ys/2/obj_dir'

进行仿真

./obj_dir/Vtop 

结果如下

a = 0, b = 0, c = 1, d = 0, f = 0
a = 0, b = 0, c = 0, d = 1, f = 0
a = 0, b = 1, c = 1, d = 1, f = 1
a = 0, b = 1, c = 0, d = 1, f = 0
a = 0, b = 0, c = 1, d = 1, f = 1
a = 0, b = 1, c = 1, d = 0, f = 0
a = 0, b = 1, c = 0, d = 0, f = 0
a = 0, b = 1, c = 1, d = 1, f = 1
a = 1, b = 0, c = 1, d = 1, f = 1
a = 1, b = 1, c = 0, d = 1, f = 0
a = 0, b = 0, c = 1, d = 1, f = 1
a = 1, b = 1, c = 0, d = 1, f = 0^C

可以看到我最后用<ctrl>+C对仿真进行终止（这就是问题所在）

ls
Makefile  obj_dir  sim.cpp  top.v  wave.fst  wave.fst.hier  wave.vcd

可见wave.fst为所求文件，wave.fst.hier为结构文件正常应该是没有的，wave.vcd为同样流程生成的.vcd文件

用gtkwave尝试打开

.fst

gtkwave wave.fst
Gtk-Message: 18:32:43.955: Failed to load module "canberra-gtk-module"

GTKWave Analyzer v3.3.104 (w)1999-2020 BSI

GTKWAVE | Could not initialize 'wave.fst', exiting.

.vcd

gtkwave wave.vcd
Gtk-Message: 18:34:35.666: Failed to load module "canberra-gtk-module"

GTKWave Analyzer v3.3.104 (w)1999-2020 BSI

VCDLOAD | Time backtracking detected in VCD file!
Near byte 360458, Malformed VCD identifier
[0] start time.
[25514] end time.

.fst打开失败

.vcd打开成功

将左侧信号拖到右侧显示波形正常

这是因为.fst文件不可以随时中断

.vcd可以随时中断

正确方法为在仿真文件中写好终止

例：

#include <memory>
#include <verilated.h>
#include "Vtop.h"
#include "verilated_fst_c.h"

double sc_time_stamp() { return 0; }
int main(int argc, char **argv)
{
    if (false && argc && argv){}
    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
    contextp->debug(0);
    contextp->randReset(2);
    contextp->traceEverOn(true);
    contextp->commandArgs(argc, argv);
    const std::unique_ptr<Vtop> top{new Vtop{contextp.get(), "TOP"}};
    VerilatedFstC *tfp = new VerilatedFstC;
    top->trace(tfp, 0);
    tfp->open("wave.fst"); // 设置输出的文件wave.vcd
    top->rst_n = 0;
    top->clk = 0;
    top->a = 0;
    while (!contextp->gotFinish())
    {
        contextp->timeInc(1);
        top->clk = !top->clk;
        if (!top->clk)
        {
            if (contextp->time() > 1 && contextp->time() < 10)
            {
                top->rst_n = 0; // Assert reset
            }
            else
            {
                top->rst_n = 1; // Deassert reset
            }
            if (contextp->time() > 15 && contextp->time() < 20)
            {
                top->a = 0;
            }
            if (contextp->time() >= 20 && contextp->time() < 30)
            {
                top->a = 1;
            }
            if (contextp->time() >= 30 && contextp->time() < 40)
            {
                top->a = 0;
            }
            if (contextp->time() >= 60)
            {
                break;
            }
        }
        top->eval();
        tfp->dump(contextp->time()); // dump wave
        VL_PRINTF("[%" PRId64 "] clk=%x rst_n=%x a=%x rise=%x down=%x \n", contextp->time(), top->clk, top->rst_n, top->a, top->rise, top->down);
    }
    top->final();
    tfp->close();
    return 0;
}

重新生成如下

[57] clk=1 rst_n=1 a=0 rise=0 down=0 
[58] clk=0 rst_n=1 a=0 rise=0 down=0 
[59] clk=1 rst_n=1 a=0 rise=0 down=0 

ls
Makefile  obj_dir  sim.cpp  top.v  wave.fst

gtkwave wave.fst 
Gtk-Message: 18:52:30.944: Failed to load module "canberra-gtk-module"

GTKWave Analyzer v3.3.104 (w)1999-2020 BSI

FSTLOAD | Processing 11 facs.
FSTLOAD | Built 6 signals and 5 aliases.
FSTLOAD | Building facility hierarchy tree.
FSTLOAD | Sorting facility hierarchy tree.

成功打开

综上.fst仿真生成不能中断，需提前在仿真文件中写好终止。