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Adam_python

于 2022-11-29 15:27:49 发布

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本文链接：https://blog.csdn.net/Adam_python/article/details/128099016

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该博客介绍了如何用Verilog语言创建一个与7458芯片功能相同的模块。这个模块包含四个AND门和两个OR门，接受10个输入并提供2个输出。作者提供了两种实现方式，一种是直接使用assign语句驱动输出，另一种是通过内部信号线作为中间步骤。示例代码展示了具体实现细节。

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The 7458 is a chip with four AND gates and two OR gates. This problem is slightly more complex than 7420.

Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates. For extra practice, try it both ways. assign

module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
wire p2a_p2b;
wire p2c_p2d;
wire p1_acb;
wire p1_fed;
assign p2a_p2b = p2a && p2b;
assign p2c_p2d = p2c && p2d;
assign p2y = p2a_p2b || p2c_p2d;
assign p1_acb = (p1a && p1c && p1b);
assign p1_fed = (p1f && p1e && p1d);
assign p1y = (p1_acb|p1_fed);

endmodule