#define DLT(x,y) (((x)>(y))?((x)-(y)):((y)-(x)))
#define MIN(x,y) (((x)>(y))?(y):(x))
#define MAX(x,y) (((x)>(y))?(x):(y))
#define EQU(x,y) (DLT((x),(y))<MAX_DIFF)
#define BIT_N(n) (1<<(n))
#define SUCCESS (0)
#define FAIL (word)(-1) //0xFFFF
#define MAX_DELAY 0x8FFFFL
///
// cpu
#define GIE_ENABLE() _BIS_SR(GIE) //打开IE
#define GIE_DISABLE() _BIC_SR(GIE)
// tma
#define TMA_STOP TACTL &= ~MC_3
#define TMA_CONTINUE TACTL |= MC_2
#define TMA_UP TACTL |= MC_1
#define TMA_UPDN TACTL |= MC_3
#define TAR_CLEAR TACTL |= TACLR
// tmb
#define TMB_STOP TBCTL&= ~MC_3
#define TMB_CONTINUE TBCTL|= MC_2
#define TMB_UP TBCTL|= MC_1
#define TMB_UPDN TBCTL|= MC_3
#define TMB_CLEAR TBCTL|= TBCLR
// wdt
#define WDT_DISABLE() WDTCTL=WDTPW+WDTHOLD //关闭看门狗
// ADC
#define ADC_ENABLE() ADC12IE |= 0x2000 // Enable ADC12IFG.13
#define ADC_DISABLE() ADC12IE &=~0x2000 // Disable ADC12IFG.13
// DAC idac+xdac
#define MAX_CHLDAC 10
#define MAX_DAC 0x0FFF // 最大的DAC输出 单位DAC
#define CHL_DACA 0 // xDACA
#define CHL_DACB 1 // XDACB
#define CHL_DACC 2 // XDACC
#define CHL_DACD 3 // XDACD
#define CHL_DACE 4 // XDACE
#define CHL_DACF 5 // XDACF
#define CHL_DACG 6 // XDACG
#define CHL_DACH 7 // XDACH
#define CHL_DAC0 8 // iDAC0
#define CHL_DAC1 9 // iDAC1
#define CHL_ATW CHL_DAC0 // CHL_DAC0
#define CHL_VTW CHL_DAC1 // CHL_DAC1
#define CHL_DACI CHL_DACA
#define CHL_PWR CHL_DACB
#define CHL_V2THR CHL_DACC
#define CHL_DACV CHL_DACD
#define CHL_AREF CHL_DACE
#define CHL_VREF CHL_DACF
#define CHL_ATHR CHL_DACG
#define CHL_VTHR CHL_DACH
#define MIN(x,y) (((x)>(y))?(y):(x))
#define MAX(x,y) (((x)>(y))?(x):(y))
#define EQU(x,y) (DLT((x),(y))<MAX_DIFF)
#define BIT_N(n) (1<<(n))
#define SUCCESS (0)
#define FAIL (word)(-1) //0xFFFF
#define MAX_DELAY 0x8FFFFL
///
// cpu
#define GIE_ENABLE() _BIS_SR(GIE) //打开IE
#define GIE_DISABLE() _BIC_SR(GIE)
// tma
#define TMA_STOP TACTL &= ~MC_3
#define TMA_CONTINUE TACTL |= MC_2
#define TMA_UP TACTL |= MC_1
#define TMA_UPDN TACTL |= MC_3
#define TAR_CLEAR TACTL |= TACLR
// tmb
#define TMB_STOP TBCTL&= ~MC_3
#define TMB_CONTINUE TBCTL|= MC_2
#define TMB_UP TBCTL|= MC_1
#define TMB_UPDN TBCTL|= MC_3
#define TMB_CLEAR TBCTL|= TBCLR
// wdt
#define WDT_DISABLE() WDTCTL=WDTPW+WDTHOLD //关闭看门狗
// ADC
#define ADC_ENABLE() ADC12IE |= 0x2000 // Enable ADC12IFG.13
#define ADC_DISABLE() ADC12IE &=~0x2000 // Disable ADC12IFG.13
// DAC idac+xdac
#define MAX_CHLDAC 10
#define MAX_DAC 0x0FFF // 最大的DAC输出 单位DAC
#define CHL_DACA 0 // xDACA
#define CHL_DACB 1 // XDACB
#define CHL_DACC 2 // XDACC
#define CHL_DACD 3 // XDACD
#define CHL_DACE 4 // XDACE
#define CHL_DACF 5 // XDACF
#define CHL_DACG 6 // XDACG
#define CHL_DACH 7 // XDACH
#define CHL_DAC0 8 // iDAC0
#define CHL_DAC1 9 // iDAC1
#define CHL_ATW CHL_DAC0 // CHL_DAC0
#define CHL_VTW CHL_DAC1 // CHL_DAC1
#define CHL_DACI CHL_DACA
#define CHL_PWR CHL_DACB
#define CHL_V2THR CHL_DACC
#define CHL_DACV CHL_DACD
#define CHL_AREF CHL_DACE
#define CHL_VREF CHL_DACF
#define CHL_ATHR CHL_DACG
#define CHL_VTHR CHL_DACH