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reonv基于riscv的fpga代码
This is the ReonV project repository. ReonV is a modified version of the [Leon3](http://www.gaisler.com/index.php/products/processors/leon3), a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to implement the RISC-V RV32I ISA.
2018-12-03
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