#ifndef HC32L17XA_H_
#define HC32L17XA_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "core_cm0plus.h"
#include "system_hc32l17x.h"
#include <stdint.h>
#pragma region RCC
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR0; //---控制寄存器1 00
__IO uint32_t CR1; //---控制寄存器2 04
__IO uint32_t CR2; //---控制寄存器3 08
__IO uint32_t RCH; //---RCH控制寄存器 0C
__IO uint32_t XTH; //---XTH控制寄存器 10
__IO uint32_t RCL; //---RCL控制寄存器 14
__IO uint32_t XTL; //---XTL置位清零寄存器 18
__IO uint32_t RSTSR; //---复位标识 1C
__IO uint32_t PERENR0; //---外设时钟使能寄存器1 20
__IO uint32_t PERENR1; //---外设时钟使能寄存器2 24
__IO uint32_t PERRSTR0; //---外设时钟复位寄存器1 28
__IO uint32_t PERRSTR1; //---外设时钟复位寄存器2 2C
uint32_t RESERVED[3]; //---保留 30 34 38
__IO uint32_t PLL; //---PLL控制寄存器 3C
} RCC_TypeDef;
//===>>>系统控制寄存器0的的功能
#define RCC_CR0_WAKEUP_BYRCH_POS 15
#define RCC_CR0_WAKEUP_BYRCH_MASK (0x01UL<<RCC_CR0_WAKEUP_BYRCH_POS)
#define RCC_CR0_WAKEUP_BYRCH RCC_CR0_WAKEUP_BYRCH_MASK
//===PCLK的时钟来源选择
#define RCC_CR0_PCLK_PRS_POS 11
#define RCC_CR0_PCLK_PRS_MASK (0x03UL<<RCC_CR0_PCLK_PRS_POS)
#define RCC_CR0_PCLK_PRS RCC_CR0_PCLK_PRS_MASK
//===PCLK的时钟分频数
#define RCC_CR0_PCLK_PRS_1 (0x00UL<<RCC_CR0_PCLK_PRS_POS)
#define RCC_CR0_PCLK_PRS_2 (0x01UL<<RCC_CR0_PCLK_PRS_POS)
#define RCC_CR0_PCLK_PRS_4 (0x02UL<<RCC_CR0_PCLK_PRS_POS)
#define RCC_CR0_PCLK_PRS_8 (0x03UL<<RCC_CR0_PCLK_PRS_POS)
//===HCLK的时钟来源选择
#define RCC_CR0_HCLK_PRS_POS 8
#define RCC_CR0_HCLK_PRS_MASK (0x07UL<<RCC_CR0_HCLK_PRS_POS)
#define RCC_CR0_HCLK_PRS RCC_CR0_HCLK_PRS_MASK
//===HCLK的时钟分频数
#define RCC_CR0_HCLK_PRS_1 (0x00UL<<RCC_CR0_HCLK_PRS_POS)
#define RCC_CR0_HCLK_PRS_2 (0x01UL<<RCC_CR0_HCLK_PRS_POS)
#define RCC_CR0_HCLK_PRS_4 (0x02UL<<RCC_CR0_HCLK_PRS_POS)
#define RCC_CR0_HCLK_PRS_8 (0x03UL<<RCC_CR0_HCLK_PRS_POS)
#define RCC_CR0_HCLK_PRS_16 (0x04UL<<RCC_CR0_HCLK_PRS_POS)
#define RCC_CR0_HCLK_PRS_32 (0x05UL<<RCC_CR0_HCLK_PRS_POS)
#define RCC_CR0_HCLK_PRS_64 (0x06UL<<RCC_CR0_HCLK_PRS_POS)
#define RCC_CR0_HCLK_PRS_128 (0x07UL<<RCC_CR0_HCLK_PRS_POS)
//===系统时钟的来源的时钟来源选择
#define RCC_CR0_CLKSW_POS 5
#define RCC_CR0_CLKSW_MASK (0x07UL<<RCC_CR0_CLKSW_POS)
#define RCC_CR0_CLKSW RCC_CR0_CLKSW_MASK
#define RCC_CR0_CLKSW_RCH (0x00UL<<RCC_CR0_CLKSW_POS)
#define RCC_CR0_CLKSW_XTH (0x01UL<<RCC_CR0_CLKSW_POS)
#define RCC_CR0_CLKSW_RCL (0x02UL<<RCC_CR0_CLKSW_POS)
#define RCC_CR0_CLKSW_XTL (0x03UL<<RCC_CR0_CLKSW_POS)
#define RCC_CR0_CLKSW_PLL (0x04UL<<RCC_CR0_CLKSW_POS)
//===PLL使能控制
#define RCC_CR0_PLLEN_POS 4
#define RCC_CR0_PLLEN_MASK (0x01UL<<RCC_CR0_PLLEN_POS)
#define RCC_CR0_PLLEN RCC_CR0_PLLEN_MASK
//===XTL使能控制
#define RCC_CR0_XTLEN_POS 3
#define RCC_CR0_XTLEN_MASK (0x01UL<<RCC_CR0_XTLEN_POS)
#define RCC_CR0_XTLEN RCC_CR0_XTLEN_MASK
//===RCL使能控制
#define RCC_CR0_RCLEN_POS 2
#define RCC_CR0_RCLEN_MASK (0x01UL<<RCC_CR0_RCLEN_POS)
#define RCC_CR0_RCLEN RCC_CR0_RCLEN_MASK
//===XTH使能控制
#define RCC_CR0_XTHEN_POS 1
#define RCC_CR0_XTHEN_MASK (0x01UL<<RCC_CR0_XTHEN_POS)
#define RCC_CR0_XTHEN RCC_CR0_XTHEN_MASK
//===RCH使能控制
#define RCC_CR0_RCHEN_POS 0
#define RCC_CR0_RCHEN_MASK (0x01UL<<RCC_CR0_RCHEN_POS)
#define RCC_CR0_RCHEN RCC_CR0_RCHEN_MASK
//===<<<系统控制寄存器0的功能
//===>>>系统控制寄存器1的的功能
//===RTC高速补偿时钟使能控制
#define RCC_CR1_RTC_FREQ_ADJ_POS 9
#define RCC_CR1_RTC_FREQ_ADJ_MASK (0x07UL<<RCC_CR1_RTC_FREQ_ADJ_POS)
#define RCC_CR1_RTC_FREQ_ADJ RCC_CR1_RTC_FREQ_ADJ_MASK
#define RCC_CR1_RTC_FREQ_ADJ_4M (0x00UL<<RCC_CR1_RTC_FREQ_ADJ_POS)
#define RCC_CR1_RTC_FREQ_ADJ_6M (0x01UL<<RCC_CR1_RTC_FREQ_ADJ_POS)
#define RCC_CR1_RTC_FREQ_ADJ_8M (0x02UL<<RCC_CR1_RTC_FREQ_ADJ_POS)
#define RCC_CR1_RTC_FREQ_ADJ_12M (0x03UL<<RCC_CR1_RTC_FREQ_ADJ_POS)
#define RCC_CR1_RTC_FREQ_ADJ_16M (0x04UL<<RCC_CR1_RTC_FREQ_ADJ_POS)
#define RCC_CR1_RTC_FREQ_ADJ_20M (0x05UL<<RCC_CR1_RTC_FREQ_ADJ_POS)
#define RCC_CR1_RTC_FREQ_ADJ_24M (0x06UL<<RCC_CR1_RTC_FREQ_ADJ_POS)
#define RCC_CR1_RTC_FREQ_ADJ_32M (0x07UL<<RCC_CR1_RTC_FREQ_ADJ_POS)
//===SWD端口功能
#define RCC_CR1_SWD_AF_POS 8
#define RCC_CR1_SWD_AF_MASK (0x01UL<<RCC_CR1_SWD_AF_POS)
#define RCC_CR1_SWD_AF RCC_CR1_SWD_AF_MASK
//===锁定功能
#define RCC_CR1_LOCK_UP_POS 6
#define RCC_CR1_LOCK_UP_MASK (0x01UL<<RCC_CR1_LOCK_UP_POS)
#define RCC_CR1_LOCK_UP RCC_CR1_LOCK_UP_MASK
//===RTC低功耗模式
#define RCC_CR1_RTC_LPW_POS 5
#define RCC_CR1_RTC_LPW_MASK (0x01UL<<RCC_CR1_RTC_LPW_POS)
#define RCC_CR1_RTC_LPW RCC_CR1_RTC_LPW_MASK
//===RTC低功耗模式
#define RCC_CR1_XTL_ON_POS 3
#define RCC_CR1_XTL_ON_MASK (0x01UL<<RCC_CR1_XTL_ON_POS)
#define RCC_CR1_XTL_ON RCC_CR1_XTL_ON_MASK
//===外部XTL时钟输入控制
#define RCC_CR1_EXTL_EN_POS 2
#define RCC_CR1_EXTL_EN_MASK (0x01UL<<RCC_CR1_EXTL_EN_POS)
#define RCC_CR1_EXTL_EN RCC_CR1_EXTL_EN_MASK
//===外部XTH时钟输入控制
#define RCC_CR1_EXTH_EN_POS 1
#define RCC_CR1_EXTH_EN_MASK (0x01UL<<RCC_CR1_EXTH_EN_POS)
#define RCC_CR1_EXTH_EN RCC_CR1_EXTH_EN_MASK
//===<<<系统控制寄存器1的功能
//===>>>系统控制寄存器2的的功能
//===<<<系统控制寄存器2的功能
//===>>>RCH控制寄存器的的功能
#define RCC_RCH_STABLE_POS 11
#define RCC_RCH_STABLE_MASK (0x01UL<<RCC_RCH_STABLE_POS)
#define RCC_RCH_STABLE RCC_RCH_STABLE_MASK
#define RCC_RCH_TRIM_POS 0
#define RCC_RCH_TRIM_MASK (0x3FFUL<<RCC_RCH_TRIM_POS)
#define RCC_RCH_TRIM RCC_RCH_TRIM_MASK
//===内置频率的校准值
#ifndef USE_SIMULATOR
#define RCC_RCH_TRIM_4M (*((volatile uint16_t*) (0x00100C08ul)))
#define RCC_RCH_TRIM_8M (*((volatile uint16_t*) (0x00100C06ul)))
#define RCC_RCH_TRIM_16M (*((volatile uint16_t*) (0x00100C04ul)))
#define RCC_RCH_TRIM_22M12 (*((volatile uint16_t*) (0x00100C02ul)))
#define RCC_RCH_TRIM_24M (*((volatile uint16_t*) (0x00100C00ul)))
#else
#define RCC_RCH_TRIM_4M (0x100)
#define RCC_RCH_TRIM_8M (0x100)
#define RCC_RCH_TRIM_16M (0x100)
#define RCC_RCH_TRIM_22M12 (0x100)
#define RCC_RCH_TRIM_24M (0x100)
#endif
//===<<<RCH控制寄存器的的功能
//===>>>XTH控制寄存器的的功能
#define RCC_XTH_STABLE_POS 6
#define RCC_XTH_STABLE_MASK (0x01UL<<RCC_XTH_STABLE_POS)
#define RCC_XTH_STABLE RCC_XTH_STABLE_MASK
#define RCC_XTH_STARTUP_POS 4
#define RCC_XTH_STARTUP_MASK (0x03UL<<RCC_XTH_STARTUP_POS)
#define RCC_XTH_STARTUP RCC_XTH_STARTUP_MASK
#define RCC_XTH_STARTUP_256_CLK (0x00UL<<RCC_XTH_STARTUP_POS)
#define RCC_XTH_STARTUP_1024_CLK (0x01UL<<RCC_XTH_STARTUP_POS)
#define RCC_XTH_STARTUP_4096_CLK (0x02UL<<RCC_XTH_STARTUP_POS)
#define RCC_XTH_STARTUP_16384_CLK (0x03UL<<RCC_XTH_STARTUP_POS)
#define RCC_XTH_FREQ_POS 2
#define RCC_XTH_FREQ_MASK (0x03UL<<RCC_XTH_FREQ_POS)
#define RCC_XTH_FREQ RCC_XTH_FREQ_MASK
#define RCC_XTH_FREQ_24M_32M (0x03UL<<RCC_XTH_FREQ_POS)
#define RCC_XTH_FREQ_16M_24M (0x02UL<<RCC_XTH_FREQ_POS)
#define RCC_XTH_FREQ_8M_16M (0x01UL<<RCC_XTH_FREQ_POS)
#define RCC_XTH_FREQ_4M_8M (0x00UL<<RCC_XTH_FREQ_POS)
#define RCC_XTH_DRIVER_POS 0
#define RCC_XTH_DRIVER_MASK (0x03UL<<RCC_XTH_DRIVER_POS)
#define RCC_XTH_DRIVER RCC_XTH_DRIVER_MASK
#define RCC_XTH_DRIVER_HIGH (0x03UL<<RCC_XTH_DRIVER_POS)
#define RCC_XTH_DRIVER_NORMAL (0x02UL<<RCC_XTH_DRIVER_POS)
#define RCC_XTH_DRIVER_LOW (0x01UL<<RCC_XTH_DRIVER_POS)
#define RCC_XTH_DRIVER_VERY_LOW (0x00UL<<RCC_XTH_DRIVER_POS)
//===<<<XTH控制寄存器的的功能
//===>>>RCL控制寄存器的的功能
#define RCC_RCL_STABLE_POS 12
#define RCC_RCL_STABLE_MASK (0x01UL<<RCC_RCL_STABLE_POS)
#define RCC_RCL_STABLE RCC_RCL_STABLE_MASK
#define RCC_RCL_STARTUP_POS 10
#define RCC_RCL_STARTUP_MASK (0x03UL<<RCC_RCL_STARTUP_POS)
#define RCC_RCL_STARTUP RCC_RCL_STARTUP_MASK
#define RCC_RCL_STARTUP_256_CLK (0x03UL<<RCC_RCL_STARTUP_POS)
#define RCC_RCL_STARTUP_64_CLK (0x02UL<<RCC_RCL_STARTUP_POS)
#define RCC_RCL_STARTUP_16_CLK (0x01UL<<RCC_RCL_STARTUP_POS)
#define RCC_RCL_STARTUP_4_CLK (0x00UL<<RCC_RCL_STARTUP_POS)
#define RCC_RCL_TRIM_POS 0
#define RCC_RCL_TRIM_MASK (0x1FFUL<<RCC_RCL_TRIM_POS)
#define RCC_RCL_TRIM RCC_RCL_TRIM_MASK
//===内置RCL频率的校准值
#ifndef USE_SIMULATOR
#define RCC_RCL_TRIM_38K4 (*((volatile uint16_t*) (0x00100C20ul)))
#define RCC_RCL_TRIM_32K768 (*((volatile uint16_t*) (0x00100C22ul)))
#else
#define RCC_RCL_TRIM_38K4 (0x100)
#define RCC_RCL_TRIM_32K768 (0x100)
#endif
//===<<<RCL控制寄存器的的功能
//===>>>XTL控制寄存器的的功能
#define RCC_XTL_STABLE_POS 6
#define RCC_XTL_STABLE_MASK (0x01UL<<RCC_XTL_STABLE_POS)
#define RCC_XTL_STABLE RCC_XTL_STABLE_MASK
#define RCC_XTL_STARTUP_POS 4
#define RCC_XTL_STARTUP_MASK (0x03UL<<RCC_XTL_STARTUP_POS)
#define RCC_XTL_STARTUP RCC_XTL_STARTUP_MASK
#define RCC_XTL_STARTUP_256_CLK (0x00UL<<RCC_XTL_STARTUP_POS)
#define RCC_XTL_STARTUP_1024_CLK (0x01UL<<RCC_XTL_STARTUP_POS)
#define RCC_XTL_STARTUP_4096_CLK (0x02UL<<RCC_XTL_STARTUP_POS)
#define RCC_XTL_STARTUP_16384_CLK (0x03UL<<RCC_XTL_STARTUP_POS)
#define RCC_XTL_AMP_POS 2
#define RCC_XTL_AMP_MASK (0x03UL<<RCC_XTL_AMP_POS)
#define RCC_XTL_AMP RCC_XTL_AMP_MASK
#define RCC_XTL_AMP_VERY_HIGH (0x03UL<<RCC_XTL_AMP_POS)
#define RCC_XTL_AMP_HIGH (0x02UL<<RCC_XTL_AMP_POS)
#define RCC_XTL_AMP_NORMAL (0x01UL<<RCC_XTL_AMP_POS)
#define RCC_XTL_AMP_LOW (0x00UL<<RCC_XTL_AMP_POS)
#define RCC_XTL_DRIVER_POS 0
#define RCC_XTL_DRIVER_MASK (0x03UL<<RCC_XTL_DRIVER_POS)
#define RCC_XTL_DRIVER RCC_XTL_DRIVER_MASK
#define RCC_XTL_DRIVER_VERY_HIGH (0x03UL<<RCC_XTL_DRIVER_POS)
#define RCC_XTL_DRIVER_HIGH (0x02UL<<RCC_XTL_DRIVER_POS)
#define RCC_XTL_DRIVER_NORMAL (0x01UL<<RCC_XTL_DRIVER_POS)
#define RCC_XTL_DRIVER_LOW (0x00UL<<RCC_XTL_DRIVER_POS)
//===<<<XTL控制寄存器的的功能
//===>>>复位标识寄存器的功能
#define RCC_RSTSR_RST_POS 7
#define RCC_RSTSR_RST_MASK (0x01UL<<RCC_RSTSR_RST_POS)
#define RCC_RSTSR_RST RCC_RSTSR_RST_MASK
#define RCC_RSTSR_SYSREQ_POS 6
#define RCC_RSTSR_SYSREQ_MASK (0x01UL<<RCC_RSTSR_SYSREQ_POS)
#define RCC_RSTSR_SYSREQ RCC_RSTSR_SYSREQ_MASK
#define RCC_RSTSR_LOCKUP_POS 5
#define RCC_RSTSR_LOCKUP_MASK (0x01UL<<RCC_RSTSR_LOCKUP_POS)
#define RCC_RSTSR_LOCKUP RCC_RSTSR_LOCKUP_MASK
#define RCC_RSTSR_PCA_POS 4
#define RCC_RSTSR_PCA_MASK (0x01UL<<RCC_RSTSR_PCA_POS)
#define RCC_RSTSR_PCA RCC_RSTSR_PCA_MASK
#define RCC_RSTSR_WDT_POS 3
#define RCC_RSTSR_WDT_MASK (0x01UL<<RCC_RSTSR_WDT_POS)
#define RCC_RSTSR_WDT RCC_RSTSR_WDT_MASK
#define RCC_RSTSR_LVD_POS 2
#define RCC_RSTSR_LVD_MASK (0x01UL<<RCC_RSTSR_LVD_POS)
#define RCC_RSTSR_LVD RCC_RSTSR_LVD_MASK
#define RCC_RSTSR_PORVCAP_POS 1
#define RCC_RSTSR_PORVCAP_MASK (0x01UL<<RCC_RSTSR_PORVCAP_POS)
#define RCC_RSTSR_PORVCAP RCC_RSTSR_PORVCAP_MASK
#define RCC_RSTSR_PORVCC_POS 0
#define RCC_RSTSR_PORVCC_MASK (0x01UL<<RCC_RSTSR_PORVCC_POS)
#define RCC_RSTSR_PORVCC RCC_RSTSR_PORVCC_MASK
//===<<<复位标识寄存器的功能
//===>>>外围模块时钟控制寄存器0的功能
#define RCC_PER0ENR_UART0EN_POS 0
#define RCC_PER0ENR_UART0EN_MASK (0x01UL<<RCC_PER0ENR_UART0EN_POS)
#define RCC_PER0ENR_UART0EN RCC_PER0ENR_UART0EN_MASK
#define RCC_PER0ENR_UART1EN_POS 1
#define RCC_PER0ENR_UART1EN_MASK (0x01UL<<RCC_PER0ENR_UART1EN_POS)
#define RCC_PER0ENR_UART1EN RCC_PER0ENR_UART1EN_MASK
#define RCC_PER0ENR_LPUART0EN_POS 2
#define RCC_PER0ENR_LPUART0EN_MASK (0x01UL<<RCC_PER0ENR_LPUART0EN_POS)
#define RCC_PER0ENR_LPUART0EN RCC_PER0ENR_LPUART0EN_MASK
#define RCC_PER0ENR_LPUART1EN_POS 3
#define RCC_PER0ENR_LPUART1EN_MASK (0x01UL<<RCC_PER0ENR_LPUART1EN_POS)
#define RCC_PER0ENR_LPUART1EN RCC_PER0ENR_LPUART1EN_MASK
#define RCC_PER0ENR_I2C0EN_POS 4
#define RCC_PER0ENR_I2C0EN_MASK (0x01UL<<RCC_PER0ENR_I2C0EN_POS)
#define RCC_PER0ENR_I2C0EN RCC_PER0ENR_I2C0EN_MASK
#define RCC_PER0ENR_I2C1EN_POS 5
#define RCC_PER0ENR_I2C1EN_MASK (0x01UL<<RCC_PER0ENR_I2C1EN_POS)
#define RCC_PER0ENR_I2C1EN RCC_PER0ENR_I2C1EN_MASK
#define RCC_PER0ENR_SPI0EN_POS 6
#define RCC_PER0ENR_SPI0EN_MASK (0x01UL<<RCC_PER0ENR_SPI0EN_POS)
#define RCC_PER0ENR_SPI0EN RCC_PER0ENR_SPI0EN_MASK
#define RCC_PER0ENR_SPI1EN_POS 7
#define RCC_PER0ENR_SPI1EN_MASK (0x01UL<<RCC_PER0ENR_SPI1EN_POS)
#define RCC_PER0ENR_SPI1EN RCC_PER0ENR_SPI1EN_MASK
#define RCC_PER0ENR_TIM0EN_POS 8
#define RCC_PER0ENR_TIM0EN_MASK (0x01UL<<RCC_PER0ENR_TIM0EN_POS)
#define RCC_PER0ENR_TIM0EN RCC_PER0ENR_TIM0EN_MASK
#define RCC_PER0ENR_TIM1EN_POS 8
#define RCC_PER0ENR_TIM1EN_MASK (0x01UL<<RCC_PER0ENR_TIM1EN_POS)
#define RCC_PER0ENR_TIM1EN RCC_PER0ENR_TIM1EN_MASK
#define RCC_PER0ENR_TIM2EN_POS 8
#define RCC_PER0ENR_TIM2EN_MASK (0x01UL<<RCC_PER0ENR_TIM2EN_POS)
#define RCC_PER0ENR_TIM2EN RCC_PER0ENR_TIM2EN_MASK
#define RCC_PER0ENR_LPTIM0EN_POS 9
#define RCC_PER0ENR_LPTIM0EN_MASK (0x01UL<<RCC_PER0ENR_LPTIM0EN_POS)
#define RCC_PER0ENR_LPTIM0EN RCC_PER0ENR_LPTIM0EN_MASK
#define RCC_PER0ENR_TIM4EN_POS 10
#define RCC_PER0ENR_TIM4EN_MASK (0x01UL<<RCC_PER0ENR_TIM4EN_POS)
#define RCC_PER0ENR_TIM4EN RCC_PER0ENR_TIM4EN_MASK
#define RCC_PER0ENR_TIM5EN_POS 10
#define RCC_PER0ENR_TIM5EN_MASK (0x01UL<<RCC_PER0ENR_TIM5EN_POS)
#define RCC_PER0ENR_TIM5EN RCC_PER0ENR_TIM5EN_MASK
#define RCC_PER0ENR_TIM6EN_POS 10
#define RCC_PER0ENR_TIM6EN_MASK (0x01UL<<RCC_PER0ENR_TIM6EN_POS)
#define RCC_PER0ENR_TIM6EN RCC_PER0ENR_TIM6EN_MASK
#define RCC_PER0ENR_TIM3EN_POS 11
#define RCC_PER0ENR_TIM3EN_MASK (0x01UL<<RCC_PER0ENR_TIM3EN_POS)
#define RCC_PER0ENR_TIM3EN RCC_PER0ENR_TIM3EN_MASK
#define RCC_PER0ENR_OPAEN_POS 13
#define RCC_PER0ENR_OPAEN_MASK (0x01UL<<RCC_PER0ENR_OPAEN_POS)
#define RCC_PER0ENR_OPAEN RCC_PER0ENR_OPAEN_MASK
#define RCC_PER0ENR_PCAEN_POS 14
#define RCC_PER0ENR_PCAEN_MASK (0x01UL<<RCC_PER0ENR_PCAEN_POS)
#define RCC_PER0ENR_PCAEN RCC_PER0ENR_PCAEN_MASK
#define RCC_PER0ENR_WDTEN_POS 15
#define RCC_PER0ENR_WDTEN_MASK (0x01UL<<RCC_PER0ENR_WDTEN_POS)
#define RCC_PER0ENR_WDTEN RCC_PER0ENR_WDTEN_MASK
#define RCC_PER0ENR_ADCEN_POS 16
#define RCC_PER0ENR_ADCEN_MASK (0x01UL<<RCC_PER0ENR_ADCEN_POS)
#define RCC_PER0ENR_ADCEN RCC_PER0ENR_ADCEN_MASK
#define RCC_PER0ENR_VCEN_POS 17
#define RCC_PER0ENR_VCEN_MASK (0x01UL<<RCC_PER0ENR_VCEN_POS)
#define RCC_PER0ENR_VCEN RCC_PER0ENR_VCEN_MASK
#define RCC_PER0ENR_RNGEN_POS 18
#define RCC_PER0ENR_RNGEN_MASK (0x01UL<<RCC_PER0ENR_RNGEN_POS)
#define RCC_PER0ENR_RNGEN RCC_PER0ENR_RNGEN_MASK
#define RCC_PER0ENR_PCNTEN_POS 19
#define RCC_PER0ENR_PCNTEN_MASK (0x01UL<<RCC_PER0ENR_PCNTEN_POS)
#define RCC_PER0ENR_PCNTEN RCC_PER0ENR_PCNTEN_MASK
#define RCC_PER0ENR_RTCEN_POS 20
#define RCC_PER0ENR_RTCEN_MASK (0x01UL<<RCC_PER0ENR_RTCEN_POS)
#define RCC_PER0ENR_RTCEN RCC_PER0ENR_RTCEN_MASK
#define RCC_PER0ENR_TRIMEN_POS 21
#define RCC_PER0ENR_TRIMEN_MASK (0x01UL<<RCC_PER0ENR_TRIMEN_POS)
#define RCC_PER0ENR_TRIMEN RCC_PER0ENR_TRIMEN_MASK
#define RCC_PER0ENR_LCDEN_POS 22
#define RCC_PER0ENR_LCDEN_MASK (0x01UL<<RCC_PER0ENR_LCDEN_POS)
#define RCC_PER0ENR_LCDEN RCC_PER0ENR_LCDEN_MASK
#define RCC_PER0ENR_TICKEN_POS 24
#define RCC_PER0ENR_TICKEN_MASK (0x01UL<<RCC_PER0ENR_TICKEN_POS)
#define RCC_PER0ENR_TICKEN RCC_PER0ENR_TICKEN_MASK
#define RCC_PER0ENR_SWDEN_POS 25
#define RCC_PER0ENR_SWDEN_MASK (0x01UL<<RCC_PER0ENR_SWDEN_POS)
#define RCC_PER0ENR_SWDEN RCC_PER0ENR_SWDEN_MASK
#define RCC_PER0ENR_CRCEN_POS 26
#define RCC_PER0ENR_CRCEN_MASK (0x01UL<<RCC_PER0ENR_CRCEN_POS)
#define RCC_PER0ENR_CRCEN RCC_PER0ENR_CRCEN_MASK
#define RCC_PER0ENR_AESEN_POS 27
#define RCC_PER0ENR_AESEN_MASK (0x01UL<<RCC_PER0ENR_AESEN_POS)
#define RCC_PER0ENR_AESEN RCC_PER0ENR_AESEN_MASK
#define RCC_PER0ENR_GPIOEN_POS 28
#define RCC_PER0ENR_GPIOEN_MASK (0x01UL<<RCC_PER0ENR_GPIOEN_POS)
#define RCC_PER0ENR_GPIOEN RCC_PER0ENR_GPIOEN_MASK
#define RCC_PER0ENR_DMAEN_POS 29
#define RCC_PER0ENR_DMAEN_MASK (0x01UL<<RCC_PER0ENR_DMAEN_POS)
#define RCC_PER0ENR_DMAEN RCC_PER0ENR_DMAEN_MASK
#define RCC_PER0ENR_FLASHEN_POS 31
#define RCC_PER0ENR_FLASHEN_MASK (0x01UL<<RCC_PER0ENR_FLASHEN_POS)
#define RCC_PER0ENR_FLASHEN RCC_PER0ENR_FLASHEN_MASK
//===<<<外围模块时钟控制寄存器0的功能
//===>>>外围模块时钟控制寄存器1的功能
#define RCC_PER1ENR_DACEN_POS 3
#define RCC_PER1ENR_DACEN_MASK (0x01UL<<RCC_PER1ENR_DACEN_POS)
#define RCC_PER1ENR_DACEN RCC_PER1ENR_DACEN_MASK
#define RCC_PER1ENR_LPTIM1EN_POS 4
#define RCC_PER1ENR_LPTIM1EN_MASK (0x01UL<<RCC_PER1ENR_LPTIM1EN_POS)
#define RCC_PER1ENR_LPTIM1EN RCC_PER1ENR_LPTIM1EN_POS
#define RCC_PER1ENR_UART2EN_POS 8
#define RCC_PER1ENR_UART2EN_MASK (0x01UL<<RCC_PER1ENR_UART2EN_POS)
#define RCC_PER1ENR_UART2EN RCC_PER1ENR_UART2EN_MASK
#define RCC_PER1ENR_UART3EN_POS 9
#define RCC_PER1ENR_UART3EN_MASK (0x01UL<<RCC_PER1ENR_UART3EN_POS)
#define RCC_PER1ENR_UART3EN RCC_PER1ENR_UART3EN_MASK
//===<<<外围模块时钟控制寄存器1的功能
//
//===>>>外围模块时钟复位寄存器0的功能
#define RCC_PER0RSTR_UART0RST_POS 0
#define RCC_PER0RSTR_UART0RST_MASK (0x01UL<<RCC_PER0RSTR_UART0RST_POS)
#define RCC_PER0RSTR_UART0RST RCC_PER0RSTR_UART0RST_MASK
#define RCC_PER0RSTR_UART1RST_POS 1
#define RCC_PER0RSTR_UART1RST_MASK (0x01UL<<RCC_PER0RSTR_UART1RST_POS)
#define RCC_PER0RSTR_UART1RST RCC_PER0RSTR_UART1RST_MASK
#define RCC_PER0RSTR_LPUART0RST_POS 2
#define RCC_PER0RSTR_LPUART0RST_MASK (0x01UL<<RCC_PER0RSTR_LPUART0RST_POS)
#define RCC_PER0RSTR_LPUART0RST RCC_PER0RSTR_LPUART0RST_MASK
#define RCC_PER0RSTR_LPUART1RST_POS 3
#define RCC_PER0RSTR_LPUART1RST_MASK (0x01UL<<RCC_PER0RSTR_LPUART1RST_POS)
#define RCC_PER0RSTR_LPUART1RST RCC_PER0RSTR_LPUART1RST_MASK
#define RCC_PER0RSTR_I2C0RST_POS 4
#define RCC_PER0RSTR_I2C0RST_MASK (0x01UL<<RCC_PER0RSTR_I2C0RST_POS)
#define RCC_PER0RSTR_I2C0RST RCC_PER0RSTR_I2C0RST_MASK
#define RCC_PER0RSTR_I2C1RST_POS 5
#define RCC_PER0RSTR_I2C1RST_MASK (0x01UL<<RCC_PER0RSTR_I2C1RST_POS)
#define RCC_PER0RSTR_I2C1RST RCC_PER0RSTR_I2C1RST_MASK
#define RCC_PER0RSTR_SPI0RST_POS 6
#define RCC_PER0RSTR_SPI0RST_MASK (0x01UL<<RCC_PER0RSTR_SPI0RST_POS)
#define RCC_PER0RSTR_SPI0RST RCC_PER0RSTR_SPI0RST_MASK
#define RCC_PER0RSTR_SPI1RST_POS 7
#define RCC_PER0RSTR_SPI1RST_MASK (0x01UL<<RCC_PER0RSTR_SPI1RST_POS)
#define RCC_PER0RSTR_SPI1RST RCC_PER0RSTR_SPI1RST_MASK
#define RCC_PER0RSTR_TIM0RST_POS 8
#define RCC_PER0RSTR_TIM0RST_MASK (0x01UL<<RCC_PER0RSTR_TIM0RST_POS)
#define RCC_PER0RSTR_TIM0RST RCC_PER0RSTR_TIM0RST_MASK
#define RCC_PER0RSTR_TIM1RST_POS 8
#define RCC_PER0RSTR_TIM1RST_MASK (0x01UL<<RCC_PER0RSTR_TIM1RST_POS)
#define RCC_PER0RSTR_TIM1RST RCC_PER0RSTR_TIM1RST_MASK
#define RCC_PER0RSTR_TIM2RST_POS 8
#define RCC_PER0RSTR_TIM2RST_MASK (0x01UL<<RCC_PER0RSTR_TIM2RST_POS)
#define RCC_PER0RSTR_TIM2RST RCC_PER0RSTR_TIM2RST_MASK
#define RCC_PER0RSTR_LPTIM0RST_POS 9
#define RCC_PER0RSTR_LPTIM0RST_MASK (0x01UL<<RCC_PER0RSTR_LPTIM0RST_POS)
#define RCC_PER0RSTR_LPTIM0RST RCC_PER0RSTR_LPTIM0RST_MASK
#define RCC_PER0RSTR_TIM4RST_POS 10
#define RCC_PER0RSTR_TIM4RST_MASK (0x01UL<<RCC_PER0RSTR_TIM4RST_POS)
#define RCC_PER0RSTR_TIM4RST RCC_PER0RSTR_TIM4RST_MASK
#define RCC_PER0RSTR_TIM5RST_POS 10
#define RCC_PER0RSTR_TIM5RST_MASK (0x01UL<<RCC_PER0RSTR_TIM5RST_POS)
#define RCC_PER0RSTR_TIM5RST RCC_PER0RSTR_TIM5RST_MASK
#define RCC_PER0RSTR_TIM6RST_POS 10
#define RCC_PER0RSTR_TIM6RST_MASK (0x01UL<<RCC_PER0RSTR_TIM6RST_POS)
#define RCC_PER0RSTR_TIM6RST RCC_PER0RSTR_TIM6RST_MASK
#define RCC_PER0RSTR_TIM3RST_POS 11
#define RCC_PER0RSTR_TIM3RST_MASK (0x01UL<<RCC_PER0RSTR_TIM3RST_POS)
#define RCC_PER0RSTR_TIM3RST RCC_PER0RSTR_TIM3RST_MASK
#define RCC_PER0RSTR_OPARST_POS 13
#define RCC_PER0RSTR_OPARST_MASK (0x01UL<<RCC_PER0RSTR_OPARST_POS)
#define RCC_PER0RSTR_OPARST RCC_PER0RSTR_OPARST_MASK
#define RCC_PER0RSTR_PCARST_POS 14
#define RCC_PER0RSTR_PCARST_MASK (0x01UL<<RCC_PER0RSTR_PCARST_POS)
#define RCC_PER0RSTR_PCARST RCC_PER0RSTR_PCARST_MASK
#define RCC_PER0RSTR_ADCRST_POS 16
#define RCC_PER0RSTR_ADCRST_MASK (0x01UL<<RCC_PER0RSTR_ADCRST_POS)
#define RCC_PER0RSTR_ADCRST RCC_PER0RSTR_ADCRST_MASK
#define RCC_PER0RSTR_VCRST_POS 17
#define RCC_PER0RSTR_VCRST_MASK (0x01UL<<RCC_PER0RSTR_VCRST_POS)
#define RCC_PER0RSTR_VCRST RCC_PER0RSTR_VCRST_MASK
#define RCC_PER0RSTR_RNGRST_POS 18
#define RCC_PER0RSTR_RNGRST_MASK (0x01UL<<RCC_PER0RSTR_RNGRST_POS)
#define RCC_PER0RSTR_RNGRST RCC_PER0RSTR_RNGRST_MASK
#define RCC_PER0RSTR_PCNTRST_POS 19
#define RCC_PER0RSTR_PCNTRST_MASK (0x01UL<<RCC_PER0RSTR_PCNTRST_POS)
#define RCC_PER0RSTR_PCNTRST RCC_PER0RSTR_PCNTRST_MASK
#define RCC_PER0RSTR_RTCRST_POS 20
#define RCC_PER0RSTR_RTCRST_MASK (0x01UL<<RCC_PER0RSTR_RTCRST_POS)
#define RCC_PER0RSTR_RTCRST RCC_PER0RSTR_RTCRST_MASK
#define RCC_PER0RSTR_TRIMRST_POS 21
#define RCC_PER0RSTR_TRIMRST_MASK (0x01UL<<RCC_PER0RSTR_TRIMRST_POS)
#define RCC_PER0RSTR_TRIMRST RCC_PER0RSTR_TRIMRST_MASK
#define RCC_PER0RSTR_LCDRST_POS 22
#define RCC_PER0RSTR_LCDRST_MASK (0x01UL<<RCC_PER0RSTR_LCDRST_POS)
#define RCC_PER0RSTR_LCDRST RCC_PER0RSTR_LCDRST_MASK
#define RCC_PER0RSTR_TICKRST_POS 24
#define RCC_PER0RSTR_TICKRST_MASK (0x01UL<<RCC_PER0RSTR_TICKRST_POS)
#define RCC_PER0RSTR_TICKRST RCC_PER0RSTR_TICKRST_MASK
#define RCC_PER0RSTR_SWDRST_POS 25
#define RCC_PER0RSTR_SWDRST_MASK (0x01UL<<RCC_PER0RSTR_SWDRST_POS)
#define RCC_PER0RSTR_SWDRST RCC_PER0RSTR_SWDRST_MASK
#define RCC_PER0RSTR_CRCRST_POS 26
#define RCC_PER0RSTR_CRCRST_MASK (0x01UL<<RCC_PER0RSTR_CRCRST_POS)
#define RCC_PER0RSTR_CRCRST RCC_PER0RSTR_CRCRST_MASK
#define RCC_PER0RSTR_AESRST_POS 27
#define RCC_PER0RSTR_AESRST_MASK (0x01UL<<RCC_PER0RSTR_AESRST_POS)
#define RCC_PER0RSTR_AESRST RCC_PER0RSTR_AESRST_MASK
#define RCC_PER0RSTR_GPIORST_POS 28
#define RCC_PER0RSTR_GPIORST_MASK (0x01UL<<RCC_PER0RSTR_GPIORST_POS)
#define RCC_PER0RSTR_GPIORST RCC_PER0RSTR_GPIORST_MASK
#define RCC_PER0RSTR_DMARST_POS 29
#define RCC_PER0RSTR_DMARST_MASK (0x01UL<<RCC_PER0RSTR_DMARST_POS)
#define RCC_PER0RSTR_DMARST RCC_PER0RSTR_DMARST_MASK
#define RCC_PER0RSTR_ALL (uint32_t)0xFFFFFFFFU
//===<<<外围模块时钟复位寄存器0的功能
//===>>>外围模块时钟控制寄存器1的功能
#define RCC_PER1RSTR_DACRST_POS 3
#define RCC_PER1RSTR_DACRST_MASK (0x01UL<<RCC_PER1RSTR_DACRST_POS)
#define RCC_PER1RSTR_DACRST RCC_PER1RSTR_DACRST_MASK
#define RCC_PER1RSTR_LPTIM1RST_POS 4
#define RCC_PER1RSTR_LPTIM1RST_MASK (0x01UL<<RCC_PER1RSTR_LPTIM1RST_POS)
#define RCC_PER1RSTR_LPTIM1RST RCC_PER1RSTR_LPTIM1RST_POS
#define RCC_PER1RSTR_UART2RST_POS 8
#define RCC_PER1RSTR_UART2RST_MASK (0x01UL<<RCC_PER1RSTR_UART2RST_POS)
#define RCC_PER1RSTR_UART2RST RCC_PER1RSTR_UART2RST_MASK
#define RCC_PER1RSTR_UART3RST_POS 9
#define RCC_PER1RSTR_UART3RST_MASK (0x01UL<<RCC_PER1RSTR_UART3RST_POS)
#define RCC_PER1RSTR_UART3RST RCC_PER1RSTR_UART3RST_MASK
#define RCC_PER1RSTR_ALL (uint32_t)0xFFFFFFFFU
//===<<<外围模块时钟控制寄存器1的功能
//===>>>XTL控制寄存器的的功能
#define RCC_PLL_STABLE_POS 18
#define RCC_PLL_STABLE_MASK (0x01UL<<RCC_PLL_STABLE_POS)
#define RCC_PLL_STABLE RCC_PLL_STABLE_MASK
#define RCC_PLL_STARTUP_POS 15
#define RCC_PLL_STARTUP_MASK (0x07UL<<RCC_PLL_STARTUP_POS)
#define RCC_PLL_STARTUP RCC_PLL_STARTUP_MASK
#define RCC_PLL_STARTUP_128_CLK (0x00UL<<RCC_PLL_STARTUP_POS)
#define RCC_PLL_STARTUP_256_CLK (0x01UL<<RCC_PLL_STARTUP_POS)
#define RCC_PLL_STARTUP_512_CLK (0x02UL<<RCC_PLL_STARTUP_POS)
#define RCC_PLL_STARTUP_1024_CLK (0x03UL<<RCC_PLL_STARTUP_POS)
#define RCC_PLL_STARTUP_2048_CLK (0x04UL<<RCC_PLL_STARTUP_POS)
#define RCC_PLL_STARTUP_4096_CLK (0x05UL<<RCC_PLL_STARTUP_POS)
#define RCC_PLL_STARTUP_8192_CLK (0x06UL<<RCC_PLL_STARTUP_POS)
#define RCC_PLL_STARTUP_16384_CLK (0x07UL<<RCC_PLL_STARTUP_POS)
//===PLL输入频率
#define RCC_PLL_IN_FREQ_POS 13
#define RCC_PLL_IN_FREQ_MASK (0x03UL<<RCC_PLL_IN_FREQ_POS)
#define RCC_PLL_IN_FREQ RCC_PLL_IN_FREQ_MASK
#define RCC_PLL_IN_FREQ_20M_24M (0x03UL<<RCC_PLL_IN_FREQ_POS)
#define RCC_PLL_IN_FREQ_12M_20M (0x02UL<<RCC_PLL_IN_FREQ_POS)
#define RCC_PLL_IN_FREQ_6M_12M (0x01UL<<RCC_PLL_IN_FREQ_POS)
#define RCC_PLL_IN_FREQ_4M_6M (0x00UL<<RCC_PLL_IN_FREQ_POS)
//===PLL倍频
#define RCC_PLL_DIVN_POS 5
#define RCC_PLL_DIVN_MASK (0x0FUL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN RCC_PLL_DIVN_MASK
#define RCC_PLL_DIVN_2 (0x02UL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN_3 (0x03UL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN_4 (0x04UL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN_5 (0x05UL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN_6 (0x06UL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN_7 (0x07UL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN_8 (0x08UL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN_9 (0x09UL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN_10 (0x0AUL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN_11 (0x0BUL<<RCC_PLL_DIVN_POS)
#define RCC_PLL_DIVN_12 (0x0CUL<<RCC_PLL_DIVN_POS)
//===PLL输出频率
#define RCC_PLL_OUT_FREQ_POS 2
#define RCC_PLL_OUT_FREQ_MASK (0x07UL<<RCC_PLL_OUT_FREQ_POS)
#define RCC_PLL_OUT_FREQ RCC_PLL_OUT_FREQ_MASK
#define RCC_PLL_OUT_FREQ_8M_12M (0x00UL<<RCC_PLL_OUT_FREQ_POS)
#define RCC_PLL_OUT_FREQ_12M_18M (0x01UL<<RCC_PLL_OUT_FREQ_POS)
#define RCC_PLL_OUT_FREQ_18M_24M (0x02UL<<RCC_PLL_OUT_FREQ_POS)
#define RCC_PLL_OUT_FREQ_24M_36M (0x03UL<<RCC_PLL_OUT_FREQ_POS)
#define RCC_PLL_OUT_FREQ_36M_48M (0x04UL<<RCC_PLL_OUT_FREQ_POS)
//===输入时钟选择
#define RCC_PLL_REF_POS 0
#define RCC_PLL_REF_MASK (0x07UL<<RCC_PLL_REF_POS)
#define RCC_PLL_REF RCC_PLL_REF_MASK
#define RCC_PLL_REF_XTH (0x00UL<<RCC_PLL_REF_POS)
#define RCC_PLL_REF_BYPASS (0x01UL<<RCC_PLL_REF_POS)
#define RCC_PLL_REF_RCH (0x03UL<<RCC_PLL_REF_POS)
//===<<<XTL控制寄存器的的功能
#pragma endregion
#pragma region GPIO
//===端口复用功能配置寄存器
typedef struct
{
__IO uint32_t SEL[16]; //---端口选择功能
/*
__IO uint32_t SEL01; //---端口选择功能
__IO uint32_t SEL02; //---端口选择功能
__IO uint32_t SEL03; //---端口选择功能
__IO uint32_t SEL04; //---端口选择功能
__IO uint32_t SEL05; //---端口选择功能
__IO uint32_t SEL06; //---端口选择功能
__IO uint32_t SEL07; //---端口选择功能
__IO uint32_t SEL08; //---端口选择功能
__IO uint32_t SEL09; //---端口选择功能
__IO uint32_t SEL10; //---端口选择功能
__IO uint32_t SEL11; //---端口选择功能
__IO uint32_t SEL12; //---端口选择功能
__IO uint32_t SEL13; //---端口选择功能
__IO uint32_t SEL14; //---端口选择功能
__IO uint32_t SEL15; //---端口选择功能
*/
} GPIO_AF_TypeDef;
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t DIR; //---配置输入输出模式模式 00
__IO uint32_t IDR; //---输入数据寄存器 04
__IO uint32_t ODR; //---输出数据寄存器 08
__IO uint32_t ADS; //---数模配置寄存器 0c
__IO uint32_t BSET; //---置位寄存器 10
__IO uint32_t BCLR; //---清零寄存器 14
__IO uint32_t BSETCLR; //---置位清零寄存器 18
__IO uint32_t DRIVER; //---驱动能力寄存器 1c
__IO uint32_t PU; //---上拉使能寄存器 20
__IO uint32_t PD; //---下拉使能寄存器 24
uint32_t RESERVED; //---保留字节
__IO uint32_t OD; //---开漏输出寄存器 2c
} GPIO_TypeDef;
//===端口辅助功能配置寄存器
typedef struct
{
__IO uint32_t CTRL1; //---端口辅助功能配置寄存器1 04
__IO uint32_t CTRL2; //---端口辅助功能配置寄存器1 08
__IO uint32_t TIMGS; //---端口辅助定时器门控选择 0c
__IO uint32_t TIMES; //---端口辅助定时器ETR控选择 10
__IO uint32_t TIMCPS; //---端口辅助定时器输入捕获选择 14
__IO uint32_t PCAS; //---端口辅助PCA捕获选择 18
__IO uint32_t PCNTS; //---端口辅助PCNT脉冲输入选择 1c
} GPIO_Sub_TypeDef;
#define GPIO_AF_CTRL1_IR_POS 14
#define GPIO_AF_CTRL1_IR_MASK (0x01UL<<GPIO_AF_CTRL1_IR_POS)
#define GPIO_AF_CTRL1_IR GPIO_AF_CTRL1_IR_MASK
#define GPIO_AF_CTRL1_HCLK_EN_POS 13
#define GPIO_AF_CTRL1_HCLK_EN_MASK (0x01UL<<GPIO_AF_CTRL1_HCLK_EN_POS)
#define GPIO_AF_CTRL1_HCLK_EN GPIO_AF_CTRL1_HCLK_EN_MASK
#define GPIO_AF_CTRL1_PCLK_EN_POS 13
#define GPIO_AF_CTRL1_PCLK_EN_MASK (0x01UL<<GPIO_AF_CTRL1_PCLK_EN_POS)
#define GPIO_AF_CTRL1_PCLK_EN GPIO_AF_CTRL1_PCLK_EN_MASK
#define GPIO_AF_CTRL1_HCLK_SEL_POS 10
#define GPIO_AF_CTRL1_HCLK_SEL_MASK (0x03UL<<GPIO_AF_CTRL1_HCLK_SEL_POS)
#define GPIO_AF_CTRL1_HCLK_SEL GPIO_AF_CTRL1_HCLK_SEL_MASK
#define GPIO_AF_CTRL1_HCLK_PRS_1 (0x00UL<<GPIO_AF_CTRL1_HCLK_SEL_POS)
#define GPIO_AF_CTRL1_HCLK_PRS_2 (0x01UL<<GPIO_AF_CTRL1_HCLK_SEL_POS)
#define GPIO_AF_CTRL1_HCLK_PRS_4 (0x02UL<<GPIO_AF_CTRL1_HCLK_SEL_POS)
#define GPIO_AF_CTRL1_HCLK_PRS_8 (0x03UL<<GPIO_AF_CTRL1_HCLK_SEL_POS)
#define GPIO_AF_CTRL1_PCLK_SEL_POS 8
#define GPIO_AF_CTRL1_PCLK_SEL_MASK (0x03UL<<GPIO_AF_CTRL1_PCLK_SEL_POS)
#define GPIO_AF_CTRL1_PCLK_SEL GPIO_AF_CTRL1_PCLK_SEL_MASK
#define GPIO_AF_CTRL1_PCLK_PRS_1 (0x00UL<<GPIO_AF_CTRL1_PCLK_SEL_POS)
#define GPIO_AF_CTRL1_PCLK_PRS_2 (0x01UL<<GPIO_AF_CTRL1_PCLK_SEL_POS)
#define GPIO_AF_CTRL1_PCLK_PRS_4 (0x02UL<<GPIO_AF_CTRL1_PCLK_SEL_POS)
#define GPIO_AF_CTRL1_PCLK_PRS_8 (0x03UL<<GPIO_AF_CTRL1_PCLK_SEL_POS)
#define GPIO_AF_CTRL1_SPI0_SS_POS 4
#define GPIO_AF_CTRL1_SPI0_SS_MASK (0x0FUL<<GPIO_AF_CTRL1_SPI0_SS_POS)
#define GPIO_AF_CTRL1_SPI0_SS GPIO_AF_CTRL1_SPI0_SS_MASK
#define GPIO_AF_CTRL1_EXT_CLK_POS 0
#define GPIO_AF_CTRL1_EXT_CLK_MASK (0x0FUL<<GPIO_AF_CTRL1_EXT_CLK_POS)
#define GPIO_AF_CTRL1_EXT_CLK GPIO_AF_CTRL1_EXT_CLK_MASK
#define GPIO_AF_CTRL2_AHB_POS 15
#define GPIO_AF_CTRL2_AHB_MASK (0x01UL<<GPIO_AF_CTRL2_AHB_POS)
#define GPIO_AF_CTRL2_AHB GPIO_AF_CTRL2_AHB_MASK
#define GPIO_AF_CTRL2_TCLK_DIV_POS 6
#define GPIO_AF_CTRL2_TCLK_DIV_MASK (0x03UL<<GPIO_AF_CTRL2_TCLK_DIV_POS)
#define GPIO_AF_CTRL2_TCLK_DIV GPIO_AF_CTRL2_TCLK_DIV_MASK
#define GPIO_AF_CTRL2_TCLK_SEL_POS 4
#define GPIO_AF_CTRL2_TCLK_SEL_MASK (0x03UL<<GPIO_AF_CTRL2_TCLK_SEL_POS)
#define GPIO_AF_CTRL2_TCLK_SEL GPIO_AF_CTRL2_TCLK_SEL_MASK
#define GPIO_AF_CTRL2_SPI1_SS_POS 0
#define GPIO_AF_CTRL2_SPI1_SS_MASK (0x0FUL<<GPIO_AF_CTRL2_SPI1_SS_POS)
#define GPIO_AF_CTRL2_SPI1_SS GPIO_AF_CTRL2_SPI1_SS_MASK
//===端口定时器门控选择
#define GPIO_AF_TIMGS_LPTIM0_POS 12
#define GPIO_AF_TIMGS_LPTIM0_MASK (0x07UL<<GPIO_AF_TIMGS_LPTIM0_POS)
#define GPIO_AF_TIMGS_LPTIM0 GPIO_AF_TIMGS_LPTIM0_MASK
#define GPIO_AF_TIMGS_TIM3_POS 9
#define GPIO_AF_TIMGS_TIM3_MASK (0x07UL<<GPIO_AF_TIMGS_TIM3_POS)
#define GPIO_AF_TIMGS_TIM3 GPIO_AF_TIMGS_TIM3_MASK
#define GPIO_AF_TIMGS_TIM2_POS 6
#define GPIO_AF_TIMGS_TIM2_MASK (0x07UL<<GPIO_AF_TIMGS_TIM2_POS)
#define GPIO_AF_TIMGS_TIM2 GPIO_AF_TIMGS_TIM2_MASK
#define GPIO_AF_TIMGS_TIM1_POS 3
#define GPIO_AF_TIMGS_TIM1_MASK (0x07UL<<GPIO_AF_TIMGS_TIM1_POS)
#define GPIO_AF_TIMGS_TIM1 GPIO_AF_TIMGS_TIM1_MASK
#define GPIO_AF_TIMGS_TIM0_POS 0
#define GPIO_AF_TIMGS_TIM0_MASK (0x07UL<<GPIO_AF_TIMGS_TIM0_POS)
#define GPIO_AF_TIMGS_TIM0 GPIO_AF_TIMGS_TIM0_MASK
//===定时器ETR输入选择
#define GPIO_AF_TIMES_LPTIM0_POS 12
#define GPIO_AF_TIMES_LPTIM0_MASK (0x07UL<<GPIO_AF_TIMES_LPTIM0_POS)
#define GPIO_AF_TIMES_LPTIM0 GPIO_AF_TIMES_LPTIM0_MASK
#define GPIO_AF_TIMES_TIM3_POS 9
#define GPIO_AF_TIMES_TIM3_MASK (0x07UL<<GPIO_AF_TIMES_TIM3_POS)
#define GPIO_AF_TIMES_TIM3 GPIO_AF_TIMES_TIM3_MASK
#define GPIO_AF_TIMES_TIM2_POS 6
#define GPIO_AF_TIMES_TIM2_MASK (0x07UL<<GPIO_AF_TIMES_TIM2_POS)
#define GPIO_AF_TIMES_TIM2 GPIO_AF_TIMES_TIM2_MASK
#define GPIO_AF_TIMES_TIM1_POS 3
#define GPIO_AF_TIMES_TIM1_MASK (0x07UL<<GPIO_AF_TIMES_TIM1_POS)
#define GPIO_AF_TIMES_TIM1 GPIO_AF_TIMES_TIM1_MASK
#define GPIO_AF_TIMES_TIM0_POS 0
#define GPIO_AF_TIMES_TIM0_MASK (0x07UL<<GPIO_AF_TIMES_TIM0_POS)
#define GPIO_AF_TIMES_TIM0 GPIO_AF_TIMES_TIM0_MASK
//===输入捕捉通道选择
#define GPIO_AF_TIMCPS_TIM3_CH0B_POS 12
#define GPIO_AF_TIMCPS_TIM3_CH0B_MASK (0x07UL<<GPIO_AF_TIMCPS_TIM3_CH0B_POS)
#define GPIO_AF_TIMCPS_TIM3_CH0B GPIO_AF_TIMCPS_TIM3_CH0B_MASK
#define GPIO_AF_TIMCPS_TIM3_CH0A_POS 9
#define GPIO_AF_TIMCPS_TIM3_CH0A_MASK (0x07UL<<GPIO_AF_TIMCPS_TIM3_CH0A_POS)
#define GPIO_AF_TIMCPS_TIM3_CH0A GPIO_AF_TIMCPS_TIM3_CH0A_MASK
#define GPIO_AF_TIMCPS_TIM2_CH0A_POS 6
#define GPIO_AF_TIMCPS_TIM2_CH0A_MASK (0x07UL<<GPIO_AF_TIMCPS_TIM2_CH0A_POS)
#define GPIO_AF_TIMCPS_TIM2_CH0A GPIO_AF_TIMCPS_TIM2_CH0A_MASK
#define GPIO_AF_TIMCPS_TIM1_CH0A_POS 3
#define GPIO_AF_TIMCPS_TIM1_CH0A_MASK (0x07UL<<GPIO_AF_TIMCPS_TIM1_CH0A_POS)
#define GPIO_AF_TIMCPS_TIM1_CH0A GPIO_AF_TIMCPS_TIM1_CH0A_MASK
#define GPIO_AF_TIMCPS_TIM0_CH0A_POS 0
#define GPIO_AF_TIMCPS_TIM0_CH0A_MASK (0x07UL<<GPIO_AF_TIMCPS_TIM0_CH0A_POS)
#define GPIO_AF_TIMCPS_TIM0_CH0A GPIO_AF_TIMCPS_TIM0_CH0A_MASK
//===PCA捕获选择
#define GPIO_AF_PCAS_LPTIM1_ETR_POS 9
#define GPIO_AF_PCAS_LPTIM1_ETR_MASK (0x07UL<<GPIO_AF_PCAS_LPTIM1_ETR_POS)
#define GPIO_AF_PCAS_LPTIM1_ETR GPIO_AF_PCAS_LPTIM1_ETR_MASK
#define GPIO_AF_PCAS_LPTIM1_GATE_POS 6
#define GPIO_AF_PCAS_LPTIM1_GATE_MASK (0x07UL<<GPIO_AF_PCAS_LPTIM1_GATE_POS)
#define GPIO_AF_PCAS_LPTIM1_GATE GPIO_AF_PCAS_LPTIM1_GATE_MASK
#define GPIO_AF_PCAS_PCA_EC1_POS 3
#define GPIO_AF_PCAS_PCA_EC1_MASK (0x07UL<<GPIO_AF_PCAS_PCA_EC1_POS)
#define GPIO_AF_PCAS_PCA_EC1 GPIO_AF_PCAS_PCA_EC1_MASK
#define GPIO_AF_PCAS_PCA_CH0_POS 0
#define GPIO_AF_PCAS_PCA_CH0_MASK (0x07UL<<GPIO_AF_PCAS_PCA_CH0_POS)
#define GPIO_AF_PCAS_PCA_CH0 GPIO_AF_PCAS_PCA_CH0_MASK
//===PCNT输入选择
#define GPIO_AF_PCNTS_PCNT_S1_POS 2
#define GPIO_AF_PCNTS_PCNT_S1_MASK (0x03UL<<GPIO_AF_PCNTS_PCNT_S1_POS)
#define GPIO_AF_PCNTS_PCNT_S1 GPIO_AF_PCNTS_PCNT_S1_MASK
#define GPIO_AF_PCNTS_PCNT_S0_POS 0
#define GPIO_AF_PCNTS_PCNT_S0_MASK (0x03UL<<GPIO_AF_PCNTS_PCNT_S0_POS)
#define GPIO_AF_PCNTS_PCNT_S0 GPIO_AF_PCNTS_PCNT_S0_MASK
#pragma endregion
//===外部中断
#pragma region EXTI
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t HIE; //---高电平中断使能 130
__IO uint32_t LIE; //---低电平中断使能 134
__IO uint32_t RIE; //---上升沿中断使能 138
__IO uint32_t FIE; //---下降沿中断使能 13c
uint32_t RESERVED1[48]; //---保留字节
__IO uint32_t SR; //---中断状态 200
uint32_t RESERVED2[3]; //---保留字节
__IO uint32_t CSR; //---清除中断状态 210
} EXIT_TypeDef;
#define EXIT_PIN_0_POS 0
#define EXIT_PIN_0_MASK (0x01UL<<EXIT_PIN_0_POS)
#define EXIT_PIN_0 EXIT_PIN_0_MASK
#define EXIT_PIN_1_POS 1
#define EXIT_PIN_1_MASK (0x01UL<<EXIT_PIN_1_POS)
#define EXIT_PIN_1 EXIT_PIN_1_MASK
#define EXIT_PIN_2_POS 2
#define EXIT_PIN_2_MASK (0x01UL<<EXIT_PIN_2_POS)
#define EXIT_PIN_2 EXIT_PIN_2
#define EXIT_PIN_3_POS 3
#define EXIT_PIN_3_MASK (0x01UL<<EXIT_PIN_3_POS)
#define EXIT_PIN_3 EXIT_PIN_3_MASK
#define EXIT_PIN_4_POS 4
#define EXIT_PIN_4_MASK (0x01UL<<EXIT_PIN_4_POS)
#define EXIT_PIN_4 EXIT_PIN_4_MASK
#define EXIT_PIN_5_POS 5
#define EXIT_PIN_5_MASK (0x01UL<<EXIT_PIN_5_POS)
#define EXIT_PIN_5 EXIT_PIN_5_MASK
#define EXIT_PIN_6_POS 6
#define EXIT_PIN_6_MASK (0x01UL<<EXIT_PIN_6_POS)
#define EXIT_PIN_6 EXIT_PIN_6_MASK
#define EXIT_PIN_7_POS 7
#define EXIT_PIN_7_MASK (0x01UL<<EXIT_PIN_7_POS)
#define EXIT_PIN_7 EXIT_PIN_7_MASK
#define EXIT_PIN_8_POS 8
#define EXIT_PIN_8_MASK (0x01UL<<EXIT_PIN_8_POS)
#define EXIT_PIN_8 EXIT_PIN_8_MASK
#define EXIT_PIN_9_POS 9
#define EXIT_PIN_9_MASK (0x01UL<<EXIT_PIN_9_POS)
#define EXIT_PIN_9 EXIT_PIN_9_MASK
#define EXIT_PIN_10_POS 10
#define EXIT_PIN_10_MASK (0x01UL<<EXIT_PIN_10_POS)
#define EXIT_PIN_10 EXIT_PIN_10_MASK
#define EXIT_PIN_11_POS 11
#define EXIT_PIN_11_MASK (0x01UL<<EXIT_PIN_11_POS)
#define EXIT_PIN_11 EXIT_PIN_11_MASK
#define EXIT_PIN_12_POS 12
#define EXIT_PIN_12_MASK (0x01UL<<EXIT_PIN_12_POS)
#define EXIT_PIN_12 EXIT_PIN_12_MASK
#define EXIT_PIN_13_POS 13
#define EXIT_PIN_13_MASK (0x01UL<<EXIT_PIN_13_POS)
#define EXIT_PIN_13 EXIT_PIN_13_MASK
#define EXIT_PIN_14_POS 14
#define EXIT_PIN_14_MASK (0x01UL<<EXIT_PIN_14_POS)
#define EXIT_PIN_14 EXIT_PIN_14_MASK
#define EXIT_PIN_15_POS 15
#define EXIT_PIN_15_MASK (0x01UL<<EXIT_PIN_15_POS)
#define EXIT_PIN_15 EXIT_PIN_15_MASK
#pragma endregion
#pragma region CRC
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR; //---控制寄存器
__IO uint32_t DR; //---数据寄存器 04
uint32_t RESERVED[30]; //---保留字节
__IO uint32_t IDR; //---输入数据寄存器 80
} CRC_TypeDef;
//===CRC编码格式，CRC16或者CRC32
#define CRC_CR_ENCODE_POS 0
#define CRC_CR_ENCODE_MASK (0x01U<<CRC_CR_ENCODE_POS)
#define CRC_CR_ENCODE CRC_CR_ENCODE_MASK
//===CRC校验结果
#define CRC_CR_FLAG_POS 1
#define CRC_CR_FLAG_MASK (0x01U<<CRC_CR_FLAG_POS)
#define CRC_CR_FLAG CRC_CR_FLAG_MASK
//===CRC16编码
#define CRC_CR_CRC16 0
//===CRC32编码
#define CRC_CR_CRC32 1
//===CRC校验错误
#define CRC_CR_FLAG_ERR 0
//===CRC校验成功
#define CRC_CR_FLAG_OK 1
#pragma endregion
#pragma region I2C
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t TMRUN; //---时钟寄存器1
__IO uint32_t TM; //---时钟寄存器2
__IO uint32_t CR; //---控制寄存器
__IO uint32_t DR; //---数据寄存器
__IO uint32_t ADDR; //---地址寄存器
__IO uint32_t SR; //---状态寄存器
} I2C_TypeDef;
#define I2C_TMRUN_TME_POS 0
#define I2C_TMRUN_TME_MASK (0x01U<<I2C_TMRUN_TME_POS)
#define I2C_TMRUN_TME I2C_TMRUN_TME_MASK
#define I2C_TM_POS 0
#define I2C_TM_MASK (0xFFU<<I2C_TM_POS)
#define I2C_TM I2C_TM_MASK
#define I2C_CR_EN_POS 6
#define I2C_CR_EN_MASK (0x01U<<I2C_CR_EN_POS)
#define I2C_CR_EN I2C_CR_EN_MASK
#define I2C_CR_START_POS 5
#define I2C_CR_START_MASK (0x01U<<I2C_CR_START_POS)
#define I2C_CR_START I2C_CR_START_MASK
#define I2C_CR_STOP_POS 4
#define I2C_CR_STOP_MASK (0x01U<<I2C_CR_STOP_POS)
#define I2C_CR_STOP I2C_CR_STOP_MASK
#define I2C_CR_IE_FLAG_POS 3
#define I2C_CR_IE_FLAG_MASK (0x01U<<I2C_CR_IE_FLAG_POS)
#define I2C_CR_IE_FLAG I2C_CR_IE_FLAG_MASK
#define I2C_CR_ACK_POS 2
#define I2C_CR_ACK_MASK (0x01U<<I2C_CR_ACK_POS)
#define I2C_CR_ACK I2C_CR_ACK_MASK
#define I2C_CR_FILTER_POS 0
#define I2C_CR_FILTER_MASK (0x01U<<I2C_CR_FILTER_POS)
#define I2C_CR_FILTER I2C_CR_FILTER_MASK
#define I2C_DATA_POS 0
#define I2C_DATA_MASK (0xFFU<<I2C_DATA_POS)
#define I2C_DATA I2C_DATA_MASK
#define I2C_ADDR_SLAVE_POS 1
#define I2C_ADDR_SLAVE_MASK (0x7FU<<I2C_ADDR_SLAVE_POS)
#define I2C_ADDR_SLAVE I2C_ADDR_SLAVE_MASK
#define I2C_ADDR_GC_POS 0
#define I2C_ADDR_GC_MASK (0x01U<<I2C_ADDR_GC_POS)
#define I2C_ADDR_GC I2C_ADDR_GC_MASK
#define I2C_STATE_POS 0
#define I2C_STATE_MASK (0xFFU<<I2C_STATE_POS)
#define I2C_STATE I2C_STATE_MASK
#define I2C_STATE_M_START 0X08
#define I2C_STATE_M_RESTART 0X10
#define I2C_STATE_M_ERR 0X38
#define I2C_STATE_MT_ADDR_ACK 0X18
#define I2C_STATE_MT_ADDR_NACK 0X20
#define I2C_STATE_MT_DATA_ACK 0X28
#define I2C_STATE_MT_DATA_NACK 0X30
#define I2C_STATE_MR_ADDR_ACK 0X40
#define I2C_STATE_MR_ADDR_NACK 0X48
#define I2C_STATE_MR_DATA_ACK 0X50
#define I2C_STATE_MR_DATA_NACK 0X58
#define I2C_STATE_STATIC_ADDR 0XA0
#define I2C_STATE_SR_ADDR_ACK 0X60
#define I2C_STATE_SR_ADDR_ERR_ACK 0X68
#define I2C_STATE_SR_DATA_ACK 0X80
#define I2C_STATE_SR_DATA_NACK 0X88
#define I2C_STATE_ST_ADDR_ACK 0XA8
#define I2C_STATE_ST_ADDR_ERR_ACK 0XB0
#define I2C_STATE_ST_DATA_ACK 0XB8
#define I2C_STATE_ST_DATA_NACK 0XC0
#define I2C_STATE_ST_DATA_LOAD_ACK 0XC8
#define I2C_STATE_GC_ADDR_ACK 0X70
#define I2C_STATE_GC_ADDR_ERR_ACK 0X78
#define I2C_STATE_GC_DATA_ACK 0X78
#define I2C_STATE_GC_DATA_NACK 0X98
#define I2C_STATE_NONE 0XF8
#define I2C_STATE_ERR 0X00
#pragma endregion
#pragma region SPI
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR; //---配置寄存器1 00
__IO uint32_t SSN; //---片选配置寄存器 04
__IO uint32_t SR; //---状态寄存器 08
__IO uint32_t DR; //---数据寄存器 0C
__IO uint32_t CR2; //---配置寄存器2 10
__IO uint32_t CSR; //---状态清除寄存器 14
} SPI_TypeDef;
#define SPI_CR_BAUDRATE_SPR2_POS 7
#define SPI_CR_BAUDRATE_SPR2_MASK (0x01U<<SPI_CR_BAUDRATE_SPR2_POS)
#define SPI_CR_BAUDRATE_SPR2 SPI_CR_BAUDRATE_SPR2_MASK
#define SPI_CR_EN_POS 6
#define SPI_CR_EN_MASK (0x01U<<SPI_CR_EN_POS)
#define SPI_CR_EN SPI_CR_EN_MASK
#define SPI_CR_MODE_POS 4
#define SPI_CR_MODE_MASK (0x01U<<SPI_CR_MODE_POS)
#define SPI_CR_MODE SPI_CR_MODE_MASK
#define SPI_CR_MODE_MASTER SPI_CR_MODE
#define SPI_CR_MODE_SLAVE (~SPI_CR_MODE)
#define SPI_CR_CPOL_POS 3
#define SPI_CR_CPOL_MASK (0x01U<<SPI_CR_CPOL_POS)
#define SPI_CR_CPOL SPI_CR_CPOL_MASK
#define SPI_CR_CPOL_LOW (~SPI_CR_CPOL)
#define SPI_CR_CPOL_HIGH (SPI_CR_CPOL)
#define SPI_CR_CPHA_POS 2
#define SPI_CR_CPHA_MASK (0x01U<<SPI_CR_CPHA_POS)
#define SPI_CR_CPHA SPI_CR_CPHA_MASK
#define SPI_CR_CPHA_1EDGE (~SPI_CR_CPHA)
#define SPI_CR_CPHA_2EDGE (SPI_CR_CPHA)
#define SPI_CR_BAUDRATE_SPR1_POS 1
#define SPI_CR_BAUDRATE_SPR1_MASK (0x01U<<SPI_CR_BAUDRATE_SPR1_POS)
#define SPI_CR_BAUDRATE_SPR1 SPI_CR_BAUDRATE_SPR1_MASK
#define SPI_CR_BAUDRATE_SPR0_POS 0
#define SPI_CR_BAUDRATE_SPR0_MASK (0x01U<<SPI_CR_BAUDRATE_SPR0_POS)
#define SPI_CR_BAUDRATE_SPR0 SPI_CR_BAUDRATE_SPR0_MASK
#define SPI_CR_BAUDRATE_SPR (SPI_CR_BAUDRATE_SPR0|SPI_CR_BAUDRATE_SPR1|SPI_CR_BAUDRATE_SPR2)
#define SPI_CR_SCK_PRE_2 ((0x00U<<SPI_CR_BAUDRATE_SPR2_POS)|(0x00U<<SPI_CR_BAUDRATE_SPR1_POS)|(0x00U<<SPI_CR_BAUDRATE_SPR0_POS))
#define SPI_CR_SCK_PRE_4 ((0x00U<<SPI_CR_BAUDRATE_SPR2_POS)|(0x00U<<SPI_CR_BAUDRATE_SPR1_POS)|(0x01U<<SPI_CR_BAUDRATE_SPR0_POS))
#define SPI_CR_SCK_PRE_8 ((0x00U<<SPI_CR_BAUDRATE_SPR2_POS)|(0x01U<<SPI_CR_BAUDRATE_SPR1_POS)|(0x00U<<SPI_CR_BAUDRATE_SPR0_POS))
#define SPI_CR_SCK_PRE_16 ((0x00U<<SPI_CR_BAUDRATE_SPR2_POS)|(0x01U<<SPI_CR_BAUDRATE_SPR1_POS)|(0x01U<<SPI_CR_BAUDRATE_SPR0_POS))
#define SPI_CR_SCK_PRE_32 ((0x01U<<SPI_CR_BAUDRATE_SPR2_POS)|(0x00U<<SPI_CR_BAUDRATE_SPR1_POS)|(0x00U<<SPI_CR_BAUDRATE_SPR0_POS))
#define SPI_CR_SCK_PRE_64 ((0x01U<<SPI_CR_BAUDRATE_SPR2_POS)|(0x00U<<SPI_CR_BAUDRATE_SPR1_POS)|(0x01U<<SPI_CR_BAUDRATE_SPR0_POS))
#define SPI_CR_SCK_PRE_128 ((0x01U<<SPI_CR_BAUDRATE_SPR2_POS)|(0x01U<<SPI_CR_BAUDRATE_SPR1_POS)|(0x00U<<SPI_CR_BAUDRATE_SPR0_POS))
#define SPI_SSN_SSN_POS 0
#define SPI_SSN_SSN_MASK (0x01U<<SPI_SSN_SSN_POS)
#define SPI_SSN_SSN SPI_SSN_SSN_MASK
#define SPI_SR_SPIF_POS 7
#define SPI_SR_SPIF_MASK (0x01U<<SPI_SR_SPIF_POS)
#define SPI_SR_SPIF SPI_SR_SPIF_MASK
#define SPI_SR_SSERR_POS 5
#define SPI_SR_SSERR_MASK (0x01U<<SPI_SR_SSERR_POS)
#define SPI_SR_SSERR SPI_SR_SSERR_MASK
#define SPI_SR_MDF_POS 4
#define SPI_SR_MDF_MASK (0x01U<<SPI_SR_MDF_POS)
#define SPI_SR_MDF SPI_SR_MDF_MASK
#define SPI_SR_BUSY_POS 3
#define SPI_SR_BUSY_MASK (0x01U<<SPI_SR_BUSY_POS)
#define SPI_SR_BUSY SPI_SR_BUSY_MASK
#define SPI_SR_TXE_POS 2
#define SPI_SR_TXE_MASK (0x01U<<SPI_SR_TXE_POS)
#define SPI_SR_TXE SPI_SR_TXE_MASK
#define SPI_SR_RXNE_POS 1
#define SPI_SR_RXNE_MASK (0x01U<<SPI_SR_RXNE_POS)
#define SPI_SR_RXNE SPI_SR_RXNE_MASK
#define SPI_DR_POS 0
#define SPI_DR_MASK (0xFFUL<<SPI_DR_POS)
#define SPI_DR SPI_DR_MASK
#define SPI_CR2_RXNEIE_POS 6
#define SPI_CR2_RXNEIE_MASK (0x01U<<SPI_CR2_RXNEIE_POS)
#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_MASK
#define SPI_CR2_TXEIE_POS 5
#define SPI_CR2_TXEIE_MASK (0x01U<<SPI_CR2_TXEIE_POS)
#define SPI_CR2_TXEIE SPI_CR2_TXEIE_MASK
#define SPI_CR2_DMATXEN_POS 4
#define SPI_CR2_DMATXEN_MASK (0x01U<<SPI_CR2_DMATXEN_POS)
#define SPI_CR2_DMATXEN SPI_CR2_DMATXEN_MASK
#define SPI_CR2_DMARXEN_POS 3
#define SPI_CR2_DMARXEN_MASK (0x01U<<SPI_CR2_DMARXEN_POS)
#define SPI_CR2_DMARXEN SPI_CR2_DMARXEN_MASK
#define SPI_CR2_IE_POS 2
#define SPI_CR2_IE_MASK (0x01U<<SPI_CR2_IE_POS)
#define SPI_CR2_IE SPI_CR2_IE_MASK
#define SPI_CSR_IE_POS 0
#define SPI_CSR_IE_MASK (0x01U<<SPI_CSR_IE_POS)
#define SPI_CSR_IE SPI_CSR_IE_MASK
#pragma endregion
#pragma region USART
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t SBUF; //---数据寄存器
__IO uint32_t SCON; //---控制寄存器
__IO uint32_t SADDR; //---地址寄存器寄存器
__IO uint32_t SADEN; //---地址寄存器寄存器
__IO uint32_t SR; //---状态寄存器
__IO uint32_t CSR; //---状态清除寄存器
__IO uint32_t SCNT; //---波特率寄存器
} USART_TypeDef;
//===>>>USART控制寄存器的的功能
//===单线半双工模式使能位
#define USART_SCON_HDSEL_POS 22
#define USART_SCON_HDSEL_MASK (0x01U<<USART_SCON_HDSEL_POS)
#define USART_SCON_HDSEL USART_SCON_HDSEL_MASK
//===帧错误中断使能位
#define USART_SCON_FEIE_POS 21
#define USART_SCON_FEIE_MASK (0x01U<<USART_SCON_FEIE_POS)
#define USART_SCON_FEIE USART_SCON_FEIE_MASK
//===CTS信号翻转中断使能位
#define USART_SCON_CTSIE_POS 20
#define USART_SCON_CTSIE_MASK (0x01U<<USART_SCON_CTSIE_POS)
#define USART_SCON_CTSIE USART_SCON_CTSIE_MASK
//===硬件流控制使能位
#define USART_SCON_CTSEN_POS 19
#define USART_SCON_CTSEN_MASK (0x01U<<USART_SCON_CTSEN_POS)
#define USART_SCON_CTSEN USART_SCON_CTSEN_MASK
//===硬件流控制使能位
#define USART_SCON_RTSEN_POS 18
#define USART_SCON_RTSEN_MASK (0x01U<<USART_SCON_RTSEN_POS)
#define USART_SCON_RTSEN USART_SCON_RTSEN_MASK
//===DMA使能位
#define USART_SCON_DMATXEN_POS 17
#define USART_SCON_DMATXEN_MASK (0x01U<<USART_SCON_DMATXEN_POS)
#define USART_SCON_DMATXEN USART_SCON_DMATXEN_MASK
//===DMA使能位
#define USART_SCON_DMARXEN_POS 16
#define USART_SCON_DMARXEN_MASK (0x01U<<USART_SCON_DMARXEN_POS)
#define USART_SCON_DMARXEN USART_SCON_DMARXEN_MASK
//===停止位
#define USART_SCON_STOPBIT_POS 14
#define USART_SCON_STOPBIT_MASK (0x03U<<USART_SCON_STOPBIT_POS)
#define USART_SCON_STOPBIT USART_SCON_STOPBIT_MASK
#define USART_SCON_STOPBIT_1BIT (0x00U<<USART_SCON_STOPBIT_POS)
#define USART_SCON_STOPBIT_1BIT5 (0x01U<<USART_SCON_STOPBIT_POS)
#define USART_SCON_STOPBIT_2BIT (0x02U<<USART_SCON_STOPBIT_POS)
//===奇偶校验错误中断使能位
#define USART_SCON_PEIE_POS 13
#define USART_SCON_PEIE_MASK (0x01U<<USART_SCON_PEIE_POS)
#define USART_SCON_PEIE USART_SCON_PEIE_MASK
//===采样分频
#define USART_SCON_OVER_POS 9
#define USART_SCON_OVER_MASK (0x01U<<USART_SCON_OVER_POS)
#define USART_SCON_OVER USART_SCON_OVER_MASK
#define USART_SCON_OVER1_16 (0x00U<<USART_SCON_OVER_POS)
#define USART_SCON_OVER1_8 (0x01U<<USART_SCON_OVER_POS)
#define USART_SCON_OVER2_32 (0x00U<<USART_SCON_OVER_POS)
#define USART_SCON_OVER2_16 (0x01U<<USART_SCON_OVER_POS)
//===发送空中断使能位
#define USART_SCON_TXEIE_POS 8
#define USART_SCON_TXEIE_MASK (0x01U<<USART_SCON_TXEIE_POS)
#define USART_SCON_TXEIE USART_SCON_TXEIE_MASK
//===工作模式
#define USART_SCON_SM_POS 6
#define USART_SCON_SM_MASK (0x03U<<USART_SCON_SM_POS)
#define USART_SCON_SM USART_SCON_SM_MASK
#define USART_SCON_SM_MODE0 (0x00U<<USART_SCON_SM_POS)
#define USART_SCON_SM_MODE1 (0x01U<<USART_SCON_SM_POS)
#define USART_SCON_SM_MODE2 (0x02U<<USART_SCON_SM_POS)
#define USART_SCON_SM_MODE3 (0x03U<<USART_SCON_SM_POS)
//===多机通讯地址自动识别使能位
#define USART_SCON_ADRDET_POS 5
#define USART_SCON_ADRDET_MASK (0x01U<<USART_SCON_ADRDET_POS)
#define USART_SCON_ADRDET USART_SCON_ADRDET_MASK
//===收发模式控制
#define USART_SCON_REN_POS 4
#define USART_SCON_REN_MASK (0x01U<<USART_SCON_REN_POS)
#define USART_SCON_REN USART_SCON_REN_MASK
#define USART_SCON_REN_TX (0x00U<<USART_SCON_REN_POS)
#define USART_SCON_REN_RX (0x01U<<USART_SCON_REN_POS)
#define USART_SCON_REN_TX_RX (0x01U<<USART_SCON_REN_POS)
//===BIT8数据控制位
#define USART_SCON_B8CONT_POS 2
#define USART_SCON_B8CONT_MASK (0x03U<<USART_SCON_B8CONT_POS)
#define USART_SCON_B8CONT USART_SCON_B8CONT_MASK
#define USART_SCON_B8CONT_B8SBUF (0x00U<<USART_SCON_B8CONT_POS)
#define USART_SCON_B8CONT_EVEN (0x01U<<USART_SCON_B8CONT_POS)
#define USART_SCON_B8CONT_ODD (0x02U<<USART_SCON_B8CONT_POS)
#define USART_SCON_B8CONT_NONE (0x03U<<USART_SCON_B8CONT_POS)
//===发送完成中断使能位
#define USART_SCON_TCIE_POS 1
#define USART_SCON_TCIE_MASK (0x01U<<USART_SCON_TCIE_POS)
#define USART_SCON_TCIE USART_SCON_TCIE_MASK
//===接收完成中断使能位
#define USART_SCON_RCIE_POS 0
#define USART_SCON_RCIE_MASK (0x01U<<USART_SCON_RCIE_POS)
#define USART_SCON_RCIE USART_SCON_RCIE_MASK
//===<<<USART控制寄存器的的功能
//===>>>USART标志寄存器的的功能
//===CTS信号标志位
#define USART_SR_CTS_POS 6
#define USART_SR_CTS_MASK (0x01U<<USART_SR_CTS_POS)
#define USART_SR_CTS USART_SR_CTS_MASK
//===CTS中断标志位
#define USART_SR_CTSIF_POS 5
#define USART_SR_CTSIF_MASK (0x01U<<USART_SR_CTSIF_POS)
#define USART_SR_CTSIF USART_SR_CTSIF_MASK
//===PE奇偶校验错误中断标志位
#define USART_SR_PE_POS 4
#define USART_SR_PE_MASK (0x01U<<USART_SR_PE_POS)
#define USART_SR_PE USART_SR_PE_MASK
//===发送寄存器空中断标志位
#define USART_SR_TXE_POS 3
#define USART_SR_TXE_MASK (0x01U<<USART_SR_TXE_POS)
#define USART_SR_TXE USART_SR_TXE_MASK
//===帧错误中断标志位
#define USART_SR_FE_POS 2
#define USART_SR_FE_MASK (0x01U<<USART_SR_FE_POS)
#define USART_SR_FE USART_SR_FE_MASK
//===发送寄存器空中断标志位
#define USART_SR_TC_POS 1
#define USART_SR_TC_MASK (0x01U<<USART_SR_TC_POS)
#define USART_SR_TC USART_SR_TC_MASK
//===发送寄存器空中断标志位
#define USART_SR_RC_POS 0
#define USART_SR_RC_MASK (0x01U<<USART_SR_RC_POS)
#define USART_SR_RC USART_SR_RC_MASK
//===<<<USART标志寄存器的的功能
//===>>>USART标志清楚寄存器的的功能
//===CTS中断标志位
#define USART_CSR_CTSIF_POS 5
#define USART_CSR_CTSIF_MASK (0x01U<<USART_CSR_CTSIF_POS)
#define USART_CSR_CTSIF USART_CSR_CTSIF_MASK
//===PE奇偶校验错误中断标志位
#define USART_CSR_PE_POS 4
#define USART_CSR_PE_MASK (0x01U<<USART_CSR_PE_POS)
#define USART_CSR_PE USART_CSR_PE_MASK
//===帧错误中断标志位
#define USART_CSR_FE_POS 2
#define USART_CSR_FE_MASK (0x01U<<USART_CSR_FE_POS)
#define USART_CSR_FE USART_CSR_FE_MASK
//===发送寄存器空中断标志位
#define USART_CSR_TC_POS 1
#define USART_CSR_TC_MASK (0x01U<<USART_CSR_TC_POS)
#define USART_CSR_TC USART_CSR_TC_MASK
//===发送寄存器空中断标志位
#define USART_CSR_RC_POS 0
#define USART_CSR_RC_MASK (0x01U<<USART_CSR_RC_POS)
#define USART_CSR_RC USART_CSR_RC_MASK
//===<<<USART标志清楚寄存器的的功能
#pragma endregion
#pragma region LPUSART
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t SBUF; //---数据寄存器
__IO uint32_t SCON; //---控制寄存器
__IO uint32_t SADDR; //---地址寄存器寄存器
__IO uint32_t SADEN; //---地址寄存器寄存器
__IO uint32_t SR; //---状态寄存器
__IO uint32_t CSR; //---状态清除寄存器
__IO uint32_t SCNT; //---波特率寄存器
} LPUSART_TypeDef;
//===>>>LPUSART控制寄存器的的功能
//===单线半双工模式使能位
#define LPUSART_SCON_HDSEL_POS 22
#define LPUSART_SCON_HDSEL_MASK (0x01U<<LPUSART_SCON_HDSEL_POS)
#define LPUSART_SCON_HDSEL LPUSART_SCON_HDSEL_MASK
//===帧错误中断使能位
#define LPUSART_SCON_FEIE_POS 21
#define LPUSART_SCON_FEIE_MASK (0x01U<<LPUSART_SCON_FEIE_POS)
#define LPUSART_SCON_FEIE LPUSART_SCON_FEIE_MASK
//===CTS信号翻转中断使能位
#define LPUSART_SCON_CTSIE_POS 20
#define LPUSART_SCON_CTSIE_MASK (0x01U<<LPUSART_SCON_CTSIE_POS)
#define LPUSART_SCON_CTSIE LPUSART_SCON_CTSIE_MASK
//===硬件流控制使能位
#define LPUSART_SCON_CTSEN_POS 19
#define LPUSART_SCON_CTSEN_MASK (0x01U<<LPUSART_SCON_CTSEN_POS)
#define LPUSART_SCON_CTSEN LPUSART_SCON_CTSEN_MASK
//===硬件流控制使能位
#define LPUSART_SCON_RTSEN_POS 18
#define LPUSART_SCON_RTSEN_MASK (0x01U<<LPUSART_SCON_RTSEN_POS)
#define LPUSART_SCON_RTSEN LPUSART_SCON_RTSEN_MASK
//===DMA使能位
#define LPUSART_SCON_DMATXEN_POS 17
#define LPUSART_SCON_DMATXEN_MASK (0x01U<<LPUSART_SCON_DMATXEN_POS)
#define LPUSART_SCON_DMATXEN LPUSART_SCON_DMATXEN_MASK
//===DMA使能位
#define LPUSART_SCON_DMARXEN_POS 16
#define LPUSART_SCON_DMARXEN_MASK (0x01U<<LPUSART_SCON_DMARXEN_POS)
#define LPUSART_SCON_DMARXEN LPUSART_SCON_DMARXEN_MASK
//===停止位
#define LPUSART_SCON_STOPBIT_POS 14
#define LPUSART_SCON_STOPBIT_MASK (0x03U<<LPUSART_SCON_STOPBIT_POS)
#define LPUSART_SCON_STOPBIT LPUSART_SCON_STOPBIT_MASK
#define LPUSART_SCON_STOPBIT_1BIT (0x00U<<LPUSART_SCON_STOPBIT_POS)
#define LPUSART_SCON_STOPBIT_1BIT5 (0x01U<<LPUSART_SCON_STOPBIT_POS)
#define LPUSART_SCON_STOPBIT_2BIT (0x02U<<LPUSART_SCON_STOPBIT_POS)
//===奇偶校验错误中断使能位
#define LPUSART_SCON_PEIE_POS 13
#define LPUSART_SCON_PEIE_MASK (0x01U<<LPUSART_SCON_PEIE_POS)
#define LPUSART_SCON_PEIE LPUSART_SCON_PEIE_MASK
//===传输时钟选择为
#define LPUSART_SCON_SCLK_POS 11
#define LPUSART_SCON_SCLK_MASK (0x03U<<LPUSART_SCON_SCLK_POS)
#define LPUSART_SCON_SCLK LPUSART_SCON_SCLK_MASK
#define LPUSART_SCON_SCLK_PCLK (0x00U<<LPUSART_SCON_SCLK_POS)
#define LPUSART_SCON_SCLK_XTL (0x02U<<LPUSART_SCON_SCLK_POS)
#define LPUSART_SCON_SCLK_RCL (0x03U<<LPUSART_SCON_SCLK_POS)
//===采样分频
#define LPUSART_SCON_OVER_POS 9
#define LPUSART_SCON_OVER_MASK (0x03U<<LPUSART_SCON_OVER_POS)
#define LPUSART_SCON_OVER LPUSART_SCON_OVER_MASK
#define LPUSART_SCON_OVER1_16 (0x00U<<LPUSART_SCON_OVER_POS)
#define LPUSART_SCON_OVER1_8 (0x01U<<LPUSART_SCON_OVER_POS)
#define LPUSART_SCON_OVER1_4 (0x02U<<LPUSART_SCON_OVER_POS)
#define LPUSART_SCON_OVER2_32 (0x00U<<LPUSART_SCON_OVER_POS)
#define LPUSART_SCON_OVER2_16 (0x01U<<LPUSART_SCON_OVER_POS)
#define LPUSART_SCON_OVER2_8 (0x02U<<LPUSART_SCON_OVER_POS)
//===发送空中断使能位
#define LPUSART_SCON_TXEIE_POS 8
#define LPUSART_SCON_TXEIE_MASK (0x01U<<LPUSART_SCON_TXEIE_POS)
#define LPUSART_SCON_TXEIE LPUSART_SCON_TXEIE_MASK
//===工作模式
#define LPUSART_SCON_SM_POS 6
#define LPUSART_SCON_SM_MASK (0x03U<<LPUSART_SCON_SM_POS)
#define LPUSART_SCON_SM LPUSART_SCON_SM_MASK
#define LPUSART_SCON_SM_MODE0 (0x00U<<LPUSART_SCON_SM_POS)
#define LPUSART_SCON_SM_MODE1 (0x01U<<LPUSART_SCON_SM_POS)
#define LPUSART_SCON_SM_MODE2 (0x02U<<LPUSART_SCON_SM_POS)
#define LPUSART_SCON_SM_MODE3 (0x03U<<LPUSART_SCON_SM_POS)
//===多机通讯地址自动识别使能位
#define LPUSART_SCON_ADRDET_POS 5
#define LPUSART_SCON_ADRDET_MASK (0x01U<<LPUSART_SCON_ADRDET_POS)
#define LPUSART_SCON_ADRDET LPUSART_SCON_ADRDET_MASK
//===收发模式控制
#define LPUSART_SCON_REN_POS 4
#define LPUSART_SCON_REN_MASK (0x01U<<LPUSART_SCON_REN_POS)
#define LPUSART_SCON_REN LPUSART_SCON_REN_MASK
#define LPUSART_SCON_REN_TX (0x00U<<LPUSART_SCON_REN_POS)
#define LPUSART_SCON_REN_RX (0x01U<<LPUSART_SCON_REN_POS)
#define LPUSART_SCON_REN_TX_RX (0x01U<<LPUSART_SCON_REN_POS)
//===BIT8数据控制位
#define LPUSART_SCON_B8CONT_POS 2
#define LPUSART_SCON_B8CONT_MASK (0x03U<<LPUSART_SCON_B8CONT_POS)
#define LPUSART_SCON_B8CONT LPUSART_SCON_B8CONT_MASK
#define LPUSART_SCON_B8CONT_B8SBUF (0x00U<<LPUSART_SCON_B8CONT_POS)
#define LPUSART_SCON_B8CONT_EVEN (0x01U<<LPUSART_SCON_B8CONT_POS)
#define LPUSART_SCON_B8CONT_ODD (0x02U<<LPUSART_SCON_B8CONT_POS)
#define LPUSART_SCON_B8CONT_NONE (0x03U<<LPUSART_SCON_B8CONT_POS)
//===发送完成中断使能位
#define LPUSART_SCON_TCIE_POS 1
#define LPUSART_SCON_TCIE_MASK (0x01U<<LPUSART_SCON_TCIE_POS)
#define LPUSART_SCON_TCIE LPUSART_SCON_TCIE_MASK
//===接收完成中断使能位
#define LPUSART_SCON_RCIE_POS 0
#define LPUSART_SCON_RCIE_MASK (0x01U<<LPUSART_SCON_RCIE_POS)
#define LPUSART_SCON_RCIE LPUSART_SCON_RCIE_MASK
//===<<<LPUSART控制寄存器的的功能
//===>>>LPUSART标志寄存器的的功能
//===CTS信号标志位
#define LPUSART_SR_CTS_POS 6
#define LPUSART_SR_CTS_MASK (0x01U<<LPUSART_SR_CTS_POS)
#define LPUSART_SR_CTS LPUSART_SR_CTS_MASK
//===CTS中断标志位
#define LPUSART_SR_CTSIF_POS 5
#define LPUSART_SR_CTSIF_MASK (0x01U<<LPUSART_SR_CTSIF_POS)
#define LPUSART_SR_CTSIF LPUSART_SR_CTSIF_MASK
//===PE奇偶校验错误中断标志位
#define LPUSART_SR_PE_POS 4
#define LPUSART_SR_PE_MASK (0x01U<<LPUSART_SR_PE_POS)
#define LPUSART_SR_PE LPUSART_SR_PE_MASK
//===发送寄存器空中断标志位
#define LPUSART_SR_TXE_POS 3
#define LPUSART_SR_TXE_MASK (0x01U<<LPUSART_SR_TXE_POS)
#define LPUSART_SR_TXE LPUSART_SR_TXE_MASK
//===帧错误中断标志位
#define LPUSART_SR_FE_POS 2
#define LPUSART_SR_FE_MASK (0x01U<<LPUSART_SR_FE_POS)
#define LPUSART_SR_FE LPUSART_SR_FE_MASK
//===发送寄存器空中断标志位
#define LPUSART_SR_TC_POS 1
#define LPUSART_SR_TC_MASK (0x01U<<LPUSART_SR_TC_POS)
#define LPUSART_SR_TC LPUSART_SR_TC_MASK
//===发送寄存器空中断标志位
#define LPUSART_SR_RC_POS 0
#define LPUSART_SR_RC_MASK (0x01U<<LPUSART_SR_RC_POS)
#define LPUSART_SR_RC LPUSART_SR_RC_MASK
//===<<<LPUSART标志寄存器的的功能
//===>>>LPUSART标志清楚寄存器的的功能
//===CTS中断标志位
#define LPUSART_CSR_CTSIF_POS 5
#define LPUSART_CSR_CTSIF_MASK (0x01U<<LPUSART_CSR_CTSIF_POS)
#define LPUSART_CSR_CTSIF LPUSART_CSR_CTSIF_MASK
//===PE奇偶校验错误中断标志位
#define LPUSART_CSR_PE_POS 4
#define LPUSART_CSR_PE_MASK (0x01U<<LPUSART_CSR_PE_POS)
#define LPUSART_CSR_PE LPUSART_CSR_PE_MASK
//===帧错误中断标志位
#define LPUSART_CSR_FE_POS 2
#define LPUSART_CSR_FE_MASK (0x01U<<LPUSART_CSR_FE_POS)
#define LPUSART_CSR_FE LPUSART_CSR_FE_MASK
//===发送寄存器空中断标志位
#define LPUSART_CSR_TC_POS 1
#define LPUSART_CSR_TC_MASK (0x01U<<LPUSART_CSR_TC_POS)
#define LPUSART_CSR_TC LPUSART_CSR_TC_MASK
//===发送寄存器空中断标志位
#define LPUSART_CSR_RC_POS 0
#define LPUSART_CSR_RC_MASK (0x01U<<LPUSART_CSR_RC_POS)
#define LPUSART_CSR_RC LPUSART_CSR_RC_MASK
//===<<<LPUSART标志清楚寄存器的的功能
#pragma endregion
#pragma region FLASH
//===FLASH寄存器
typedef struct
{
__IO uint32_t TNVS; //---时间参数
__IO uint32_t TPGS; //---时间参数
__IO uint32_t TPROG; //---地址寄存器寄存器
__IO uint32_t TSERASE; //---地址寄存器寄存器
__IO uint32_t TMERASE; //---状态寄存器
__IO uint32_t TPRCV; //---状态清除寄存器
__IO uint32_t TSRCV; //---状态清除寄存器
__IO uint32_t TMRCV; //---状态清除寄存器
__IO uint32_t CR; //---状态清除寄存器
__IO uint32_t SR; //---状态清除寄存器
__IO uint32_t CSR; //---状态清除寄存器
__IO uint32_t BYPASS; //---状态清除寄存器
__IO uint32_t SLOCK0; //---状态清除寄存器
__IO uint32_t SLOCK1; //---状态清除寄存器
uint32_t RESERVED[2]; //---保留字节
__IO uint32_t SLOCK2; //---状态清除寄存器
__IO uint32_t SLOCK3; //---状态清除寄存器
} FLASH_TypeDef;
//====TNVS
#define FLASH_TNVS_POS 0
#define FLASH_TNVS_MASK (0x1FFUL<<FLASH_TNVS_POS)
#define FLASH_TNVS FLASH_TNVS_MASK
//===TPGS
#define FLASH_TPGS_POS 0
#define FLASH_TPGS_MASK (0x1FFUL<<FLASH_TPGS_POS)
#define FLASH_TPGS FLASH_TPGS_MASK
//===TPRGOS
#define FLASH_TPRGOS_POS 0
#define FLASH_TPRGOS_MASK (0x1FFUL<<FLASH_TPRGOS_POS)
#define FLASH_TPRGOS FLASH_TPRGOS_MASK
//===TSERASE
#define FLASH_TSERASE_POS 0
#define FLASH_TSERASE_MASK (0x1FFFFUL<<FLASH_TSERASE_POS)
#define FLASH_TSERASE FLASH_TSERASE_MASK
//===TMERASE
#define FLASH_TMERASE_POS 0
#define FLASH_TMERASE_MASK (0x1FFFFFUL<<FLASH_TMERASE_POS)
#define FLASH_TMERASE FLASH_TMERASE_MASK
//===TPRCV
#define FLASH_TPRCV_POS 0
#define FLASH_TPRCV_MASK (0xFFFUL<<FLASH_TPRCV_POS)
#define FLASH_TPRCV FLASH_TPRCV_MASK
//===TSRCV
#define FLASH_TSRCV_POS 0
#define FLASH_TSRCV_MASK (0xFFFUL<<FLASH_TSRCV_POS)
#define FLASH_TSRCV FLASH_TSRCV_MASK
//===TMRCV
#define FLASH_TMRCV_POS 0
#define FLASH_TMRCV_MASK (0x3FFFUL<<FLASH_TMRCV_POS)
#define FLASH_TMRCV FLASH_TMRCV_MASK
//===>>>FLASH_CR寄存器
#define FLASH_CR_DPSTN_EN_POS 9
#define FLASH_CR_DPSTN_EN_MASK (0x1UL<<FLASH_CR_DPSTN_EN_POS)
#define FLASH_CR_DPSTN_EN FLASH_CR_DPSTN_EN_MASK
#define FLASH_CR_IE_ADDR_POS 6
#define FLASH_CR_IE_ADDR_MASK (0x1UL<<FLASH_CR_IE_ADDR_POS)
#define FLASH_CR_IE_ADDR FLASH_CR_IE_ADDR_MASK
#define FLASH_CR_IE_PC_POS 5
#define FLASH_CR_IE_PC_MASK (0x1UL<<FLASH_CR_IE_PC_POS)
#define FLASH_CR_IE_PC FLASH_CR_IE_PC_MASK
#define FLASH_CR_BUSY_POS 4
#define FLASH_CR_BUSY_MASK (0x1UL<<FLASH_CR_BUSY_POS)
#define FLASH_CR_BUSY FLASH_CR_BUSY_MASK
#define FLASH_CR_WAIT_POS 2
#define FLASH_CR_WAIT_MASK (0x3UL<<FLASH_CR_WAIT_POS)
#define FLASH_CR_WAIT FLASH_CR_WAIT_MASK
#define FLASH_CR_WAIT_0 (0x0UL<<FLASH_CR_WAIT_POS)
#define FLASH_CR_WAIT_1 (0x0UL<<FLASH_CR_WAIT_POS)
#define FLASH_CR_WAIT_2 (0x1UL<<FLASH_CR_WAIT_POS)
#define FLASH_CR_WAIT_3 (0x2UL<<FLASH_CR_WAIT_POS)
#define FLASH_CR_OP_POS 0
#define FLASH_CR_OP_MASK (0x3UL<<FLASH_CR_OP_POS)
#define FLASH_CR_OP FLASH_CR_OP_MASK
#define FLASH_CR_OP_READ (0x0UL<<FLASH_CR_OP_POS)
#define FLASH_CR_OP_PROGRAM (0x1UL<<FLASH_CR_OP_POS)
#define FLASH_CR_OP_SECTOR_ERASE (0x2UL<<FLASH_CR_OP_POS)
#define FLASH_CR_OP_CHIP_ERASE (0x3UL<<FLASH_CR_OP_POS)
//===<<<FLASH_CR寄存器
#define FLASH_SR_IE_ADDR_POS 1
#define FLASH_SR_IE_ADDR_MASK (0x1UL<<FLASH_SR_IE_ADDR_POS)
#define FLASH_SR_IE_ADDR FLASH_SR_IE_ADDR_MASK
#define FLASH_SR_IE_PC_POS 0
#define FLASH_SR_IE_PC_MASK (0x1UL<<FLASH_SR_IE_PC_POS)
#define FLASH_SR_IE_PC FLASH_SR_IE_PC_MASK
#define FLASH_CSR_IE_ADDR_POS 1
#define FLASH_CSR_IE_ADDR_MASK (0x1UL<<FLASH_CSR_IE_ADDR_POS)
#define FLASH_CSR_IE_ADDR FLASH_CSR_IE_ADDR_MASK
#define FLASH_CSR_IE_PC_POS 0
#define FLASH_CSR_IE_PC_MASK (0x1UL<<FLASH_CSR_IE_PC_POS)
#define FLASH_CSR_IE_PC FLASH_CSR_IE_PC_MASK
#define FLASH_BYPASS_POS 0
#define FLASH_BYPASS_MASK (0xFFFFUL<<FLASH_BYPASS_POS)
#define FLASH_BYPASS FLASH_BYPASS_MASK
#pragma endregion
#pragma region RAM
//==RAM寄存器
typedef struct
{
__IO uint32_t CR; //---控制寄存器
__IO uint32_t ERR; //---出错地址寄存器
__IO uint32_t SR; //---状态寄存器
__IO uint32_t CSR; //---状态清除寄存器
} RAM_TypeDef;
//===RAM校验报警中断使能信号
#define RAM_CR_IE_POS 1
#define RAM_CR_IE_MASK (0x01UL<<RAM_CR_IE_POS)
#define RAM_CR_IE RAM_CR_IE_MASK
//===RAM校验出错地址
#define RAM_ERR_ADDR_POS 0
#define RAM_ERR_ADDR_MASK (0x3FFFUL<<RAM_ERR_ADDR_POS)
#define RAM_ERR_ADDR RAM_ERR_ADDR_MASK
//===RAM错误中断标志
#define RAM_SR_ERR_POS 0
#define RAM_SR_ERR_MASK (0x01UL<<RAM_SR_ERR_POS)
#define RAM_SR_ERR RAM_SR_ERR_MASK
//===RAM错误中断标志清除
#define RAM_CSR_ERR_POS 0
#define RAM_CSR_ERR_MASK (0x01UL<<RAM_CSR_ERR_POS)
#define RAM_CSR_ERR RAM_CSR_ERR_MASK
#pragma endregion
#pragma region RNG
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR; //---控制寄存器
__IO uint32_t MODE; //---模式寄存器
uint32_t RESERVED; //---保留字节
__IO uint32_t DR1; //---数据寄存器1
__IO uint32_t DR2; //---数据寄存器2
} RNG_TypeDef;
//===随机数状态
#define RNG_CR_RUN_POS 1
#define RNG_CR_RUN_MASK (0x01UL<<RNG_CR_RUN_POS)
#define RNG_CR_RUN RNG_CR_RUN_MASK
//===使能RNG
#define RNG_CR_EN_POS 0
#define RNG_CR_EN_MASK (0x01UL<<RNG_CR_EN_POS)
#define RNG_CR_EN RNG_CR_EN_MASK
//===随机数反馈移位次数
#define RNG_MODE_CNT_POS 2
#define RNG_MODE_CNT_MASK (0x07UL<<RNG_MODE_CNT_POS)
#define RNG_MODE_CNT RNG_MODE_CNT_MASK
#define RNG_MODE_CNT_NONE (0x00UL<<RNG_MODE_CNT_POS)
#define RNG_MODE_CNT_8 (0x01UL<<RNG_MODE_CNT_POS)
#define RNG_MODE_CNT_16 (0x02UL<<RNG_MODE_CNT_POS)
#define RNG_MODE_CNT_32 (0x03UL<<RNG_MODE_CNT_POS)
#define RNG_MODE_CNT_64 (0x04UL<<RNG_MODE_CNT_POS)
#define RNG_MODE_CNT_128 (0x05UL<<RNG_MODE_CNT_POS)
#define RNG_MODE_CNT_256 (0x06UL<<RNG_MODE_CNT_POS)
//===异或运算
#define RNG_MODE_FDBK_POS 1
#define RNG_MODE_FDBK_MASK (0x01UL<<RNG_MODE_FDBK_POS)
#define RNG_MODE_FDBK RNG_MODE_FDBK_MASK
//===产生真随机数，还是伪随机数
#define RNG_MODE_LOAD_POS 0
#define RNG_MODE_LOAD_MASK (0x01UL<<RNG_MODE_LOAD_POS)
#define RNG_MODE_LOAD RNG_MODE_LOAD_MASK
#pragma endregion
#pragma region RTC
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR0; //---控制寄存器0
__IO uint32_t CR1; //---控制寄存器1
__IO uint32_t SEC; //---秒计数寄存器
__IO uint32_t MIN; //---分计数寄存器
__IO uint32_t HOUR; //---十计数寄存器
__IO uint32_t WEEKDAY; //---周计数寄存器
__IO uint32_t DAY; //---日计数寄存器
__IO uint32_t MONTH; //---月计数寄存器
__IO uint32_t YEAR; //---年计数寄存器
__IO uint32_t ALMMIN; //---分闹钟寄存器
__IO uint32_t ALMHOUR; //---时闹钟寄存器
__IO uint32_t ALMWEEKDAY; //---周闹钟寄存器
__IO uint32_t COMPEM; //---时钟误差补偿寄存器
__IO uint32_t ALMSEC; //---秒闹钟寄存器
} RTC_TypeDef;
//===控制寄存器0的配置
#define RTC_CR0_PRDSEL_POS 14
#define RTC_CR0_PRDSEL_MASK (0x01UL<<RTC_CR0_PRDSEL_POS)
#define RTC_CR0_PRDSEL RTC_CR0_PRDSEL_MASK
#define RTC_CR0_PRDX_POS 8
#define RTC_CR0_PRDX_MASK (0x3FUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX RTC_CR0_PRDX_MASK
#define RTC_CR0_PRDX_SEC_0P5 (0x00UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_1 (0x01UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_1P5 (0x02UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_2 (0x03UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_2P5 (0x04UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_3 (0x05UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_3P5 (0x06UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_4 (0x07UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_4P5 (0x08UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_5 (0x09UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_5P5 (0x0AUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_6 (0x0BUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_6P5 (0x0CUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_7 (0x0DUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_7P5 (0x0EUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_8 (0x0FUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_8P5 (0x10UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_9 (0x11UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_9P5 (0x12UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_10 (0x13UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_10P5 (0x14UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_11 (0x15UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_11P5 (0x16UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_12 (0x17UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_12P5 (0x18UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_13 (0x19UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_13P5 (0x1AUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_14 (0x1BUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_14P5 (0x1CUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_15 (0x1DUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_15P5 (0x1EUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_16 (0x1FUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_16P5 (0x20UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_17 (0x21UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_17P5 (0x22UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_18 (0x23UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_18P5 (0x24UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_19 (0x25UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_19P5 (0x26UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_20 (0x27UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_20P5 (0x28UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_21 (0x29UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_21P5 (0x2AUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_22 (0x2BUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_22P5 (0x2CUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_23 (0x2DUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_23P5 (0x2EUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_24 (0x2FUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_24P5 (0x30UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_25 (0x31UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_25P5 (0x32UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_26 (0x33UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_26P5 (0x34UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_27 (0x35UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_27P5 (0x36UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_28 (0x37UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_28P5 (0x38UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_29 (0x39UL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_29P5 (0x3AUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_30 (0x3BUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_30P5 (0x3CUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_31 (0x3DUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_31P5 (0x3EUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_PRDX_SEC_32 (0x3FUL<<RTC_CR0_PRDX_POS)
#define RTC_CR0_START_POS 7
#define RTC_CR0_START_MASK (0x01UL<<RTC_CR0_START_POS)
#define RTC_CR0_START RTC_CR0_START_MASK
#define RTC_CR0_1HZSEL_POS 6
#define RTC_CR0_1HZSEL_MASK (0x01UL<<RTC_CR0_1HZSEL_POS)
#define RTC_CR0_1HZSEL RTC_CR0_1HZSEL_MASK
#define RTC_CR0_1HZEN_POS 5
#define RTC_CR0_1HZEN_MASK (0x01UL<<RTC_CR0_1HZEN_POS)
#define RTC_CR0_1HZEN RTC_CR0_1HZEN_MASK
#define RTC_CR0_AMPM_POS 3
#define RTC_CR0_AMPM_MASK (0x01UL<<RTC_CR0_AMPM_POS)
#define RTC_CR0_AMPM RTC_CR0_AMPM_MASK
#define RTC_CR0_AM (0x01UL<<RTC_CR0_AMPM_POS)
#define RTC_CR0_PM (0x00UL<<RTC_CR0_AMPM_POS)
#define RTC_CR0_PRDS_POS 0
#define RTC_CR0_PRDS_MASK (0x3UL<<RTC_CR0_PRDS_POS)
#define RTC_CR0_PRDS RTC_CR0_PRDS_MASK
#define RTC_CR0_PRDS_NONE (0x00UL<<RTC_CR0_PRDS_POS)
#define RTC_CR0_PRDS_SEC_0P5 (0x01UL<<RTC_CR0_PRDS_POS)
#define RTC_CR0_PRDS_SEC_1 (0x02UL<<RTC_CR0_PRDS_POS)
#define RTC_CR0_PRDS_MIN_1 (0x03UL<<RTC_CR0_PRDS_POS)
#define RTC_CR0_PRDS_HOUR_1 (0x04UL<<RTC_CR0_PRDS_POS)
#define RTC_CR0_PRDS_DAY_1 (0x05UL<<RTC_CR0_PRDS_POS)
#define RTC_CR0_PRDS_MON_1 (0x06UL<<RTC_CR0_PRDS_POS)
//===控制寄存器1的配置
#define RTC_CR1_CKSEL_POS 8
#define RTC_CR1_CKSEL_MASK (0x07UL<<RTC_CR1_CKSEL_POS)
#define RTC_CR1_CKSEL RTC_CR1_CKSEL_MASK
#define RTC_CR1_CKSEL_XTL (0x00UL<<RTC_CR1_CKSEL_POS)
#define RTC_CR1_CKSEL_RCL (0x02UL<<RTC_CR1_CKSEL_POS)
#define RTC_CR1_CKSEL_XTH_PRE128 (0x04UL<<RTC_CR1_CKSEL_POS)
#define RTC_CR1_CKSEL_XTH_PRE256 (0x05UL<<RTC_CR1_CKSEL_POS)
#define RTC_CR1_CKSEL_XTH_PRE512 (0x06UL<<RTC_CR1_CKSEL_POS)
#define RTC_CR1_CKSEL_XTH_PRE1024 (0x07UL<<RTC_CR1_CKSEL_POS)
#define RTC_CR1_ALMEN_POS 7
#define RTC_CR1_ALMEN_MASK (0x01UL<<RTC_CR1_ALMEN_POS)
#define RTC_CR1_ALMEN RTC_CR1_ALMEN_MASK
//===闹钟中断使能位
#define RTC_CR1_ALMIE_POS 6
#define RTC_CR1_ALMIE_MASK (0x01UL<<RTC_CR1_ALMIE_POS)
#define RTC_CR1_ALMIE RTC_CR1_ALMIE_MASK
//===闹钟中断标志
#define RTC_CR1_ALMF_POS 4
#define RTC_CR1_ALMF_MASK (0x01UL<<RTC_CR1_ALMF_POS)
#define RTC_CR1_ALMF RTC_CR1_ALMF_MASK
//===周期中断标志
#define RTC_CR1_PRDF_POS 3
#define RTC_CR1_PRDF_MASK (0x01UL<<RTC_CR1_PRDF_POS)
#define RTC_CR1_PRDF RTC_CR1_PRDF_MASK
//===技术模式标志
#define RTC_CR1_WAITF_POS 1
#define RTC_CR1_WAITF_MASK (0x01UL<<RTC_CR1_WAITF_POS)
#define RTC_CR1_WAITF RTC_CR1_WAITF_MASK
//===计数模式
#define RTC_CR1_WAIT_POS 0
#define RTC_CR1_WAIT_MASK (0x01UL<<RTC_CR1_WAIT_POS)
#define RTC_CR1_WAIT RTC_CR1_WAIT_MASK
#pragma endregion
#pragma region TIM
//===普通定时器
typedef struct
{
__IO uint32_t ARR; //---重载寄存器 00
__IO uint32_t CNT; //---16位模式计数寄存器 04
__IO uint32_t CNT32; //---32位模式计数寄存器 08
__IO uint32_t MCR; //---控制寄存器 0C
__IO uint32_t SR; //---中断标志 10
__IO uint32_t CSR; //---中断标志清除 14
__IO uint32_t MSCR; //---主从模式控制 18
__IO uint32_t FLTR; //---滤波控制 1C
__IO uint32_t ADTR; //---ADC触发控制 20
__IO uint32_t CRCH0_CR0; //---比较单元0控制寄存器 24
__IO uint32_t CRCH1; //---比较单元1控制寄存器 28
__IO uint32_t CRCH2; //---比较单元2控制寄存器 2C
__IO uint32_t DTR; //---死区寄存器 30
__IO uint32_t RCR; //---重复计数寄存器 34
__IO uint32_t ARRDM; //---控制寄存器1 38
__IO uint32_t CCR0A; //---比较0A寄存器 3C
__IO uint32_t CCR0B; //---比较0B寄存器 40
__IO uint32_t CCR1A; //---比较1A寄存器 44
__IO uint32_t CCR1B; //---比较1B寄存器 48
__IO uint32_t CCR2A; //---比较2A寄存器 4C
__IO uint32_t CCR2B; //---比较2B寄存器 50
} TIM_TypeDef;
//===工作模式
#define TIM_MCR_MODE_POS 12
#define TIM_MCR_MODE_MASK (0x03UL<<TIM_MCR_MODE_POS)
#define TIM_MCR_MODE TIM_MCR_MODE_MASK
#define TIM_MCR_MODE_TIM0 (0x00UL<<TIM_MCR_MODE_POS)
#define TIM_MCR_MODE_PWC (0x01UL<<TIM_MCR_MODE_POS)
#define TIM_MCR_MODE_SAWTOOTH (0x02UL<<TIM_MCR_MODE_POS)
#define TIM_MCR_MODE_TRIANGLE (0x03UL<<TIM_MCR_MODE_POS)
#define TIM_MCR_PRS_POS 4
#define TIM_MCR_PRS_MASK (0x07U<<TIM_MCR_PRS_POS)
#define TIM_MCR_PRS TIM_MCR_PRS_MASK
#define TIM_MCR_PRS_1 (0x00U<<TIM_MCR_PRS_POS)
#define TIM_MCR_PRS_2 (0x01U<<TIM_MCR_PRS_POS)
#define TIM_MCR_PRS_4 (0x02U<<TIM_MCR_PRS_POS)
#define TIM_MCR_PRS_8 (0x03U<<TIM_MCR_PRS_POS)
#define TIM_MCR_PRS_16 (0x04U<<TIM_MCR_PRS_POS)
#define TIM_MCR_PRS_32 (0x05U<<TIM_MCR_PRS_POS)
#define TIM_MCR_PRS_64 (0x06U<<TIM_MCR_PRS_POS)
#define TIM_MCR_PRS_256 (0x07U<<TIM_MCR_PRS_POS)
#define TIM_MCR_CT_POS 2
#define TIM_MCR_CT_MASK (0x01U<<TIM_MCR_CT_POS)
#define TIM_MCR_CT TIM_MCR_CT_MASK
#define TIM_MCR_EN_POS 0
#define TIM_MCR_EN_MASK (0x01U<<TIM_MCR_EN_POS)
#define TIM_MCR_EN TIM_MCR_EN_MASK
#pragma region TIM_M0
//===普通定时器
typedef struct
{
__IO uint32_t ARR; //---重载寄存器 00
__IO uint32_t CNT; //---16位模式计数寄存器 04
__IO uint32_t CNT32; //---32位模式计数寄存器 08
__IO uint32_t M0CR; //---控制寄存器 0C
__IO uint32_t SR; //---中断标志 10
__IO uint32_t CSR; //---中断标志清除 14
uint32_t RESERVED[6]; //---保留字节
__IO uint32_t DTR; //---死区寄存器 30
} TIM_M0_TypeDef;
#define TIM_M0_ARR_ARR_POS 0
#define TIM_M0_ARR_ARR_MASK (0xFFFFUL<<TIM_M0_ARR_ARR_POS)
#define TIM_M0_ARR_ARR TIM_M0_ARR_ARR_MASK
#define TIM_M0_CNT_CNT_POS 0
#define TIM_M0_CNT_CNT_MASK (0xFFFFUL<<TIM_M0_CNT_CNT_POS)
#define TIM_M0_CNT_CNT TIM_M0_CNT_CNT_MASK
#define TIM_M0_CNT_CNT32_POS 0
#define TIM_M0_CNT_CNT32_MASK (0xFFFFFFFFUL<<TIM_M0_CNT_CNT32_POS)
#define TIM_M0_CNT_CNT32 TIM_M0_CNT_CNT32_MASK
//===控制寄存器
#define TIM_M0_M0CR_MODE_POS 12
#define TIM_M0_M0CR_MODE_MASK (0x03U<<TIM_M0_M0CR_MODE_POS)
#define TIM_M0_M0CR_MODE TIM_M0_M0CR_MODE_MASK
#define TIM_M0_M0CR_IE_POS 10
#define TIM_M0_M0CR_IE_MASK (0x01U<<TIM_M0_M0CR_IE_POS)
#define TIM_M0_M0CR_IE TIM_M0_M0CR_IE_MASK
#define TIM_M0_M0CR_GATEP_POS 9
#define TIM_M0_M0CR_GATEP_MASK (0x01U<<TIM_M0_M0CR_GATEP_POS)
#define TIM_M0_M0CR_GATEP TIM_M0_M0CR_GATEP_MASK
#define TIM_M0_M0CR_GATEN_POS 8
#define TIM_M0_M0CR_GATEN_MASK (0x01U<<TIM_M0_M0CR_GATEN_POS)
#define TIM_M0_M0CR_GATEN TIM_M0_M0CR_GATEN_MASK
#define TIM_M0_M0CR_PRS_POS 4
#define TIM_M0_M0CR_PRS_MASK (0x07U<<TIM_M0_M0CR_PRS_POS)
#define TIM_M0_M0CR_PRS TIM_M0_M0CR_PRS_MASK
#define TIM_M0_M0CR_PRS_1 (0x00U<<TIM_M0_M0CR_PRS_POS)
#define TIM_M0_M0CR_PRS_2 (0x01U<<TIM_M0_M0CR_PRS_POS)
#define TIM_M0_M0CR_PRS_4 (0x02U<<TIM_M0_M0CR_PRS_POS)
#define TIM_M0_M0CR_PRS_8 (0x03U<<TIM_M0_M0CR_PRS_POS)
#define TIM_M0_M0CR_PRS_16 (0x04U<<TIM_M0_M0CR_PRS_POS)
#define TIM_M0_M0CR_PRS_32 (0x05U<<TIM_M0_M0CR_PRS_POS)
#define TIM_M0_M0CR_PRS_64 (0x06U<<TIM_M0_M0CR_PRS_POS)
#define TIM_M0_M0CR_PRS_256 (0x07U<<TIM_M0_M0CR_PRS_POS)
#define TIM_M0_M0CR_TOGEN_POS 3
#define TIM_M0_M0CR_TOGEN_MASK (0x01U<<TIM_M0_M0CR_TOGEN_POS)
#define TIM_M0_M0CR_TOGEN TIM_M0_M0CR_TOGEN_MASK
#define TIM_M0_M0CR_CT_POS 2
#define TIM_M0_M0CR_CT_MASK (0x01U<<TIM_M0_M0CR_CT_POS)
#define TIM_M0_M0CR_CT TIM_M0_M0CR_CT_MASK
#define TIM_M0_M0CR_MD_POS 1
#define TIM_M0_M0CR_MD_MASK (0x01U<<TIM_M0_M0CR_MD_POS)
#define TIM_M0_M0CR_MD TIM_M0_M0CR_MD_MASK
#define TIM_M0_M0CR_EN_POS 0
#define TIM_M0_M0CR_EN_MASK (0x01U<<TIM_M0_M0CR_EN_POS)
#define TIM_M0_M0CR_EN TIM_M0_M0CR_EN_MASK
//===标志寄存器
#define TIM_M0_SR_IE_POS 0
#define TIM_M0_SR_IE_MASK (0x01U<<TIM_M0_SR_IE_POS)
#define TIM_M0_SR_IE TIM_M0_SR_IE_MASK
//===清楚标志寄存器
#define TIM_M0_CSR_IE_POS 0
#define TIM_M0_CSR_IE_MASK (0x01U<<TIM_M0_CSR_IE_POS)
#define TIM_M0_CSR_IE TIM_M0_CSR_IE_MASK
//===死区控制寄存器
#define TIM_M0_DTR_MOE_POS 12
#define TIM_M0_DTR_MOE_MASK (0x01U<<TIM_M0_DTR_MOE_POS)
#define TIM_M0_DTR_MOE TIM_M0_DTR_MOE_MASK
#pragma endregion
#pragma region TIM_M1
//===普通定时器
typedef struct
{
uint32_t RESERVED1; //---保留字节 00
__IO uint32_t CNT; //---16位模式计数寄存器 04
uint32_t RESERVED2; //---保留字节 08
__IO uint32_t M1CR; //---控制寄存器 0C
__IO uint32_t SR; //---中断标志 10
__IO uint32_t CSR; //---中断标志清除 14
__IO uint32_t DTR; //---死区寄存器 30
__IO uint32_t MSCR; //---主从模式控制 18
__IO uint32_t FLTR; //---滤波控制 1C
uint32_t RESERVED3; //---保留字节 20
__IO uint32_t CR0; //---比较单元0控制寄存器 24
uint32_t RESERVED4[5]; //---保留字节
__IO uint32_t CCR0A; //---比较0A寄存器 3C
} TIM_M1_TypeDef;
//===控制寄存器
#define TIM_M1_CR_TRIG_POS 14
#define TIM_M1_CR_TRIG_MASK (0x03U<<TIM_M1_CR_TRIG_POS)
#define TIM_M1_CR_TRIG TIM_M1_CR_TRIG_MASK
#define TIM_M1_CR_MODE_POS 12
#define TIM_M1_CR_MODE_MASK (0x03U<<TIM_M1_CR_MODE_POS)
#define TIM_M1_CR_MODE TIM_M1_CR_MODE_MASK
#define TIM_M1_CR_IE_POS 10
#define TIM_M1_CR_IE_MASK (0x01U<<TIM_M1_CR_IE_POS)
#define TIM_M1_CR_IE TIM_M1_CR_IE_MASK
#define TIM_M1_CR_EDG_POS 8
#define TIM_M1_CR_EDG_MASK (0x03U<<TIM_M1_CR_EDG_POS)
#define TIM_M1_CR_EDG TIM_M1_CR_EDG_MASK
#define TIM_M1_CR_PRS_POS 4
#define TIM_M1_CR_PRS_MASK (0x07U<<TIM_M1_CR_PRS_POS)
#define TIM_M1_CR_PRS TIM_M1_CR_PRS_MASK
#define TIM_M1_CR_TOGEN_POS 3
#define TIM_M1_CR_TOGEN_MASK (0x01U<<TIM_M1_CR_TOGEN_POS)
#define TIM_M1_CR_TOGEN TIM_M1_CR_TOGEN_MASK
#define TIM_M1_CR_CT_POS 2
#define TIM_M1_CR_CT_MASK (0x01U<<TIM_M1_CR_CT_POS)
#define TIM_M1_CR_CT TIM_M1_CR_CT_MASK
#define TIM_M1_CR_EN_POS 0
#define TIM_M1_CR_EN_MASK (0x01U<<TIM_M1_CR_EN_POS)
#define TIM_M1_CR_EN TIM_M1_CR_EN_MASK
//===标志寄存器
#define TIM_M1_SR_CAE_POS 2
#define TIM_M1_SR_CAE_MASK (0x01U<<TIM_M1_SR_CAE_POS)
#define TIM_M1_SR_CAE TIM_M1_SR_CAE_MASK
#define TIM_M1_SR_IE_POS 0
#define TIM_M1_SR_IE_MASK (0x01U<<TIM_M1_SR_IE_POS)
#define TIM_M1_SR_IE TIM_M1_SR_IE_MASK
//===清楚标志寄存器
#define TIM_M1_CSR_CAE_POS 2
#define TIM_M1_CSR_CAE_MASK (0x01U<<TIM_M1_CSR_CAE_POS)
#define TIM_M1_CSR_CAE TIM_M1_CSR_CAE_MASK
#define TIM_M1_CSR_IE_POS 0
#define TIM_M1_CSR_IE_MASK (0x01U<<TIM_M1_CSR_IE_POS)
#define TIM_M1_CSR_IE TIM_M1_CSR_IE_MASK
//===主从模式控制寄存器
#define TIM_M1_MSCR_IB_POS 12
#define TIM_M1_MSCR_IB_MASK (0x01U<<TIM_M1_MSCR_IB_POS)
#define TIM_M1_MSCR_IB TIM_M1_MSCR_IB_MASK
#define TIM_M1_MSCR_IA_POS 11
#define TIM_M1_MSCR_IA_MASK (0x01U<<TIM_M1_MSCR_IA_POS)
#define TIM_M1_MSCR_IA TIM_M1_MSCR_IA_MASK
#define TIM_M1_MSCR_TRIG_POS 5
#define TIM_M1_MSCR_TRIG_MASK (0x07U<<TIM_M1_MSCR_TRIG_POS)
#define TIM_M1_MSCR_TRIG TIM_M1_MSCR_TRIG_MASK
//===滤波控制寄存器
//===ETR输入相位
#define TIM_M1_FLTR_ETP_POS 31
#define TIM_M1_FLTR_ETP_MASK (0x01U<<TIM_M1_FLTR_ETP_POS)
#define TIM_M1_FLTR_ETP TIM_M1_FLTR_ETP_MASK
//===ETR滤波控制
#define TIM_M1_FLTR_ETR_POS 28
#define TIM_M1_FLTR_ETR_MASK (0x07U<<TIM_M1_FLTR_ETR_POS)
#define TIM_M1_FLTR_ETR TIM_M1_FLTR_ETR_MASK
//===CHB滤波控制
#define TIM_M1_FLTR_CHB_POS 4
#define TIM_M1_FLTR_CHB_MASK (0x07U<<TIM_M1_FLTR_CHB_POS)
#define TIM_M1_FLTR_CHB TIM_M1_FLTR_CHB_MASK
//===CHA滤波控制
#define TIM_M1_FLTR_CHA_POS 0
#define TIM_M1_FLTR_CHA_MASK (0x07U<<TIM_M1_FLTR_CHA_POS)
#define TIM_M1_FLTR_CHA TIM_M1_FLTR_CHA_POS
//===CR0控制寄存器
#define TIM_M1_CR0_CAE_POS 8
#define TIM_M1_CR0_CAE_MASK (0x01U<<TIM_M1_CR0_CAE_POS)
#define TIM_M1_CR0_CAE TIM_M1_CR0_CAE_MASK
#pragma endregion
#pragma region TIM_M2
//===普通定时器
typedef struct
{
__IO uint32_t ARR; //---重载寄存器 00
__IO uint32_t CNT; //---16位模式计数寄存器 04
uint32_t RESERVED1; //---保留字节 08
__IO uint32_t M23CR; //---控制寄存器 0C
__IO uint32_t SR; //---中断标志 10
__IO uint32_t CSR; //---中断标志清除 14
__IO uint32_t MSCR; //---主从模式控制 18
__IO uint32_t FLTR; //---滤波控制 1C
__IO uint32_t ADTR; //---ADC触发控制 20
__IO uint32_t CRCH0; //---比较单元0控制寄存器 24
__IO uint32_t CRCH1; //---比较单元1控制寄存器 28
__IO uint32_t CRCH2; //---比较单元2控制寄存器 2C
__IO uint32_t DTR; //---死区寄存器 30
__IO uint32_t RCR; //---重复计数寄存器 34
__IO uint32_t ARRDM; //---控制寄存器1 38
__IO uint32_t CCR0A; //---比较0A寄存器 3C
__IO uint32_t CCR0B; //---比较0B寄存器 40
__IO uint32_t CCR1A; //---比较1A寄存器 44
__IO uint32_t CCR1B; //---比较1B寄存器 48
__IO uint32_t CCR2A; //---比较2A寄存器 4C
__IO uint32_t CCR2B; //---比较2B寄存器 50
} TIM_M2_TypeDef;
#define TIM_M2_ARR_ARR_POS 0
#define TIM_M2_ARR_ARR_MASK (0xFFFFUL<<TIM_M2_ARR_ARR_POS)
#define TIM_M2_ARR_ARR TIM_M2_ARR_ARR_MASK
#define TIM_M2_CNT_CNT_POS 0
#define TIM_M2_CNT_CNT_MASK (0xFFFFUL<<TIM_M2_CNT_CNT_POS)
#define TIM_M2_CNT_CNT TIM_M2_CNT_CNT_MASK
//===控制寄存器
#define TIM_M2_M23CR_DIR_POS 27
#define TIM_M2_M23CR_DIR_MASK (0x01UL<<TIM_M2_M23CR_DIR_POS)
#define TIM_M2_M23CR_DIR TIM_M2_M23CR_DIR_MASK
#define TIM_M2_M23CR_DIR_UP (0x00UL<<TIM_M2_M23CR_DIR_POS)
#define TIM_M2_M23CR_DIR_DOWN (0x01UL<<TIM_M2_M23CR_DIR_POS)
//===软件刹车
#define TIM_M2_M23CR_BG_POS 26
#define TIM_M2_M23CR_BG_MASK (0x01UL<<TIM_M2_M23CR_BG_POS)
#define TIM_M2_M23CR_BG TIM_M2_M23CR_BG_MASK
#define TIM_M2_M23CR_BG_ENABLE (0x01UL<<TIM_M2_M23CR_BG_POS)
#define TIM_M2_M23CR_BG_DISABLE (0x00UL<<TIM_M2_M23CR_BG_POS)
//===软件更新
#define TIM_M2_M23CR_UG_POS 25
#define TIM_M2_M23CR_UG_MASK (0x01UL<<TIM_M2_M23CR_UG_POS)
#define TIM_M2_M23CR_UG TIM_M2_M23CR_UG_MASK
#define TIM_M2_M23CR_UG_ENABLE (0x01UL<<TIM_M2_M23CR_UG_POS)
#define TIM_M2_M23CR_UG_DISABLE (0x00UL<<TIM_M2_M23CR_UG_POS)
//===软件触发
#define TIM_M2_M23CR_TG_POS 24
#define TIM_M2_M23CR_TG_MASK (0x01UL<<TIM_M2_M23CR_TG_POS)
#define TIM_M2_M23CR_TG TIM_M2_M23CR_TG_MASK
#define TIM_M2_M23CR_TG_ENABLE (0x01UL<<TIM_M2_M23CR_TG_POS)
#define TIM_M2_M23CR_TG_DISABLE (0x00UL<<TIM_M2_M23CR_TG_POS)
//===OCREF清除使能
#define TIM_M2_M23CR_OCCE_POS 23
#define TIM_M2_M23CR_OCCE_MASK (0x01UL<<TIM_M2_M23CR_OCCE_POS)
#define TIM_M2_M23CR_OCCE TIM_M2_M23CR_OCCE_MASK
#define TIM_M2_M23CR_OCCE_ENABLE (0x01UL<<TIM_M2_M23CR_OCCE_POS)
#define TIM_M2_M23CR_OCCE_DISABLE (0x00UL<<TIM_M2_M23CR_OCCE_POS)
//===A比较模式中断
#define TIM_M2_M23CR_CISA_POS 21
#define TIM_M2_M23CR_CISA_MASK (0x03UL<<TIM_M2_M23CR_CISA_POS)
#define TIM_M2_M23CR_CISA TIM_M2_M23CR_CISA_MASK
#define TIM_M2_M23CR_CISA_EDGE_NONE (0x00UL<<TIM_M2_M23CR_CISA_POS)
#define TIM_M2_M23CR_CISA_EDGE_RISE (0x01UL<<TIM_M2_M23CR_CISA_POS)
#define TIM_M2_M23CR_CISA_EDGE_FAIL (0x02UL<<TIM_M2_M23CR_CISA_POS)
#define TIM_M2_M23CR_CISA_EDGE_ALL (0x03UL<<TIM_M2_M23CR_CISA_POS)
//===刹车中断使能
#define TIM_M2_M23CR_BIE_POS 20
#define TIM_M2_M23CR_BIE_MASK (0x01UL<<TIM_M2_M23CR_BIE_POS)
#define TIM_M2_M23CR_BIE TIM_M2_M23CR_BIE_MASK
//===触发中断使能
#define TIM_M2_M23CR_TIE_POS 19
#define TIM_M2_M23CR_TIE_MASK (0x01UL<<TIM_M2_M23CR_TIE_POS)
#define TIM_M2_M23CR_TIE TIM_M2_M23CR_TIE_MASK
//===触发DMA中断使能
#define TIM_M2_M23CR_TDMAIE_POS 18
#define TIM_M2_M23CR_TDMAIE_MASK (0x01UL<<TIM_M2_M23CR_TDMAIE_POS)
#define TIM_M2_M23CR_TDMAIE TIM_M2_M23CR_TDMAIE_MASK
//===更新源
#define TIM_M2_M23CR_URS_POS 17
#define TIM_M2_M23CR_URS_MASK (0x01UL<<TIM_M2_M23CR_URS_POS)
#define TIM_M2_M23CR_URS TIM_M2_M23CR_URS_MASK
#define TIM_M2_M23CR_URS_ALL (0x00UL<<TIM_M2_M23CR_URS_POS)
#define TIM_M2_M23CR_URS_RISE_OR_FAIL (0x00UL<<TIM_M2_M23CR_URS_POS)
//===OCREF清除源选择
#define TIM_M2_M23CR_OCCS_POS 16
#define TIM_M2_M23CR_OCCS_MASK (0x01UL<<TIM_M2_M23CR_OCCS_POS)
#define TIM_M2_M23CR_OCCS TIM_M2_M23CR_OCCS_MASK
#define TIM_M2_M23CR_OCCS_VC (0x00UL<<TIM_M2_M23CR_OCCS_POS)
#define TIM_M2_M23CR_OCCS_ETR (0x01UL<<TIM_M2_M23CR_OCCS_POS)
//===PWM互补模式选择
#define TIM_M2_M23CR_CSG_POS 15
#define TIM_M2_M23CR_CSG_MASK (0x01UL<<TIM_M2_M23CR_CSG_POS)
#define TIM_M2_M23CR_CSG TIM_M2_M23CR_CSG_MASK
#define TIM_M2_M23CR_CSG_COMP (0x00UL<<TIM_M2_M23CR_CSG_POS)
#define TIM_M2_M23CR_CSG_CAPT (0x01UL<<TIM_M2_M23CR_CSG_POS)
//===触发选择
#define TIM_M2_M23CR_TRIG_POS 14
#define TIM_M2_M23CR_TRIG_MASK (0x01UL<<TIM_M2_M23CR_TRIG_POS)
#define TIM_M2_M23CR_TRIG TIM_M2_M23CR_TRIG_MASK
#define TIM_M2_M23CR_TRIG_CYCLE (0x00UL<<TIM_M2_M23CR_TRIG_POS)
#define TIM_M2_M23CR_TRIG_SINGLE (0x01UL<<TIM_M2_M23CR_TRIG_POS)
//===工作模式
#define TIM_M2_M23CR_MODE_POS 12
#define TIM_M2_M23CR_MODE_MASK (0x03UL<<TIM_M2_M23CR_MODE_POS)
#define TIM_M2_M23CR_MODE TIM_M2_M23CR_MODE_MASK
#define TIM_M2_M23CR_MODE_TIM0 (0x00UL<<TIM_M2_M23CR_MODE_POS)
#define TIM_M2_M23CR_MODE_PWC (0x01UL<<TIM_M2_M23CR_MODE_POS)
#define TIM_M2_M23CR_MODE_SAWTOOTH (0x02UL<<TIM_M2_M23CR_MODE_POS)
#define TIM_M2_M23CR_MODE_TRIANGLE (0x03UL<<TIM_M2_M23CR_MODE_POS)
//===更新DMA使能
#define TIM_M2_M23CR_UDMAEN_POS 11
#define TIM_M2_M23CR_UDMAEN_MASK (0x01UL<<TIM_M2_M23CR_UDMAEN_POS)
#define TIM_M2_M23CR_UDMAEN TIM_M2_M23CR_UDMAEN_MASK
//===更新中断使能
#define TIM_M2_M23CR_UIE_POS 10
#define TIM_M2_M23CR_UIE_MASK (0x01UL<<TIM_M2_M23CR_UIE_POS)
#define TIM_M2_M23CR_UIE TIM_M2_M23CR_UIE_MASK
//===下降沿捕获使能控制
#define TIM_M2_M23CR_CFG_POS 9
#define TIM_M2_M23CR_CFG_MASK (0x01UL<<TIM_M2_M23CR_CFG_POS)
#define TIM_M2_M23CR_CFG TIM_M2_M23CR_CFG_MASK
#define TIM_M2_M23CR_CFG_ENABLE (0x01UL<<TIM_M2_M23CR_CFG_POS)
#define TIM_M2_M23CR_CFG_DISABLE (0x00UL<<TIM_M2_M23CR_CFG_POS)
//===上升沿捕获使能控制
#define TIM_M2_M23CR_CRG_POS 8
#define TIM_M2_M23CR_CRG_MASK (0x01UL<<TIM_M2_M23CR_CRG_POS)
#define TIM_M2_M23CR_CRG TIM_M2_M23CR_CRG_MASK
#define TIM_M2_M23CR_CRG_ENABLE (0x01UL<<TIM_M2_M23CR_CRG_POS)
#define TIM_M2_M23CR_CRG_DISABLE (0x00UL<<TIM_M2_M23CR_CRG_POS)
//===重载缓存使能控制
#define TIM_M2_M23CR_BUFPEN_POS 7
#define TIM_M2_M23CR_BUFPEN_MASK (0x01UL<<TIM_M2_M23CR_BUFPEN_POS)
#define TIM_M2_M23CR_BUFPEN TIM_M2_M23CR_BUFPEN_MASK
//===时钟分频选择
#define TIM_M2_M23CR_PRS_POS 4
#define TIM_M2_M23CR_PRS_MASK (0x07UL<<TIM_M2_M23CR_PRS_POS)
#define TIM_M2_M23CR_PRS TIM_M2_M23CR_PRS_MASK
#define TIM_M2_M23CR_PRS_1 (0x00UL<<TIM_M2_M23CR_PRS_POS)
#define TIM_M2_M23CR_PRS_2 (0x01UL<<TIM_M2_M23CR_PRS_POS)
#define TIM_M2_M23CR_PRS_4 (0x02UL<<TIM_M2_M23CR_PRS_POS)
#define TIM_M2_M23CR_PRS_8 (0x03UL<<TIM_M2_M23CR_PRS_POS)
#define TIM_M2_M23CR_PRS_16 (0x04UL<<TIM_M2_M23CR_PRS_POS)
#define TIM_M2_M23CR_PRS_32 (0x05UL<<TIM_M2_M23CR_PRS_POS)
#define TIM_M2_M23CR_PRS_64 (0x06UL<<TIM_M2_M23CR_PRS_POS)
#define TIM_M2_M23CR_PRS_256 (0x07UL<<TIM_M2_M23CR_PRS_POS)
//===单双点比较控制
#define TIM_M2_M23CR_PWM2S_POS 3
#define TIM_M2_M23CR_PWM2S_MASK (0x01UL<<TIM_M2_M23CR_PWM2S_POS)
#define TIM_M2_M23CR_PWM2S TIM_M2_M23CR_PWM2S_MASK
#define TIM_M2_M23CR_PWM2S_DOUBLE (0x00UL<<TIM_M2_M23CR_PWM2S_POS)
#define TIM_M2_M23CR_PWM2S_SINGLE (0x01UL<<TIM_M2_M23CR_PWM2S_POS)
//===计数时钟
#define TIM_M2_M23CR_CT_POS 2
#define TIM_M2_M23CR_CT_MASK (0x01UL<<TIM_M2_M23CR_CT_POS)
#define TIM_M2_M23CR_CT TIM_M2_M23CR_CT_MASK
#define TIM_M2_M23CR_CT_TCLK (0x00UL<<TIM_M2_M23CR_CT_POS)
#define TIM_M2_M23CR_CT_ETR (0x01UL<<TIM_M2_M23CR_CT_POS)
//===PWM模式选择
#define TIM_M2_M23CR_COMP_POS 1
#define TIM_M2_M23CR_COMP_MASK (0x01UL<<TIM_M2_M23CR_COMP_POS)
#define TIM_M2_M23CR_COMP TIM_M2_M23CR_COMP_MASK
#define TIM_M2_M23CR_COMP_PWM_COMP (0x01UL<<TIM_M2_M23CR_COMP_POS)
#define TIM_M2_M23CR_COMP_PWM_INDEP (0x00UL<<TIM_M2_M23CR_COMP_POS)
//===定时器使能控制
#define TIM_M2_M23CR_EN_POS 0
#define TIM_M2_M23CR_EN_MASK (0x01U<<TIM_M2_M23CR_EN_POS)
#define TIM_M2_M23CR_EN TIM_M2_M23CR_EN_MASK
//===中断标志寄存器
//===触发中断标志
#define TIM_M2_SR_TIE_POS 15
#define TIM_M2_SR_TIE_MASK (0x01U<<TIM_M2_SR_TIE_POS)
#define TIM_M2_SR_TIE TIM_M2_SR_TIE_MASK
//===刹车中断标志
#define TIM_M2_SR_BIE_POS 14
#define TIM_M2_SR_BIE_MASK (0x01U<<TIM_M2_SR_BIE_POS)
#define TIM_M2_SR_BIE TIM_M2_SR_BIE_MASK
//==CH2B捕获丢数据
#define TIM_M2_SR_CH2B_ERROR_POS 13
#define TIM_M2_SR_CH2B_ERROR_MASK (0x01U<<TIM_M2_SR_CH2B_ERROR_POS)
#define TIM_M2_SR_CH2B_ERROR TIM_M2_SR_CH2B_ERROR_MASK
//==CH1B捕获丢数据
#define TIM_M2_SR_CH1B_ERROR_POS 12
#define TIM_M2_SR_CH1B_ERROR_MASK (0x01U<<TIM_M2_SR_CH1B_ERROR_POS)
#define TIM_M2_SR_CH1B_ERROR TIM_M2_SR_CH1B_ERROR_MASK
//==CH0B捕获丢数据
#define TIM_M2_SR_CH0B_ERROR_POS 11
#define TIM_M2_SR_CH0B_ERROR_MASK (0x01U<<TIM_M2_SR_CH0B_ERROR_POS)
#define TIM_M2_SR_CH0B_ERROR TIM_M2_SR_CH0B_ERROR_MASK
//==CH2A捕获丢数据
#define TIM_M2_SR_CH2A_ERROR_POS 10
#define TIM_M2_SR_CH2A_ERROR_MASK (0x01U<<TIM_M2_SR_CH2A_ERROR_POS)
#define TIM_M2_SR_CH2A_ERROR TIM_M2_SR_CH2A_ERROR_MASK
//==CH1A捕获丢数据
#define TIM_M2_SR_CH1A_ERROR_POS 9
#define TIM_M2_SR_CH1A_ERROR_MASK (0x01U<<TIM_M2_SR_CH1A_ERROR_POS)
#define TIM_M2_SR_CH1A_ERROR TIM_M2_SR_CH1A_ERROR_MASK
//==CH0A捕获丢数据
#define TIM_M2_SR_CH0A_ERROR_POS 8
#define TIM_M2_SR_CH0A_ERROR_MASK (0x01U<<TIM_M2_SR_CH0A_ERROR_POS)
#define TIM_M2_SR_CH0A_ERROR TIM_M2_SR_CH0A_ERROR_MASK
//==CH2B捕获/比较中断标志
#define TIM_M2_SR_CH2B_FLAG_POS 7
#define TIM_M2_SR_CH2B_FLAG_MASK (0x01U<<TIM_M2_SR_CH2B_FLAG_POS)
#define TIM_M2_SR_CH2B_FLAG TIM_M2_SR_CH2B_FLAG_MASK
//==CH1B捕获/比较中断标志
#define TIM_M2_SR_CH1B_FLAG_POS 6
#define TIM_M2_SR_CH1B_FLAG_MASK (0x01U<<TIM_M2_SR_CH1B_FLAG_POS)
#define TIM_M2_SR_CH1B_FLAG TIM_M2_SR_CH1B_FLAG_MASK
//==CH0B捕获/比较中断标志
#define TIM_M2_SR_CH0B_FLAG_POS 5
#define TIM_M2_SR_CH0B_FLAG_MASK (0x01U<<TIM_M2_SR_CH0B_FLAG_POS)
#define TIM_M2_SR_CH0B_FLAG TIM_M2_SR_CH0B_FLAG_MASK
//==CH2A捕获/比较中断标志
#define TIM_M2_SR_CH2A_FLAG_POS 4
#define TIM_M2_SR_CH2A_FLAG_MASK (0x01U<<TIM_M2_SR_CH2A_FLAG_POS)
#define TIM_M2_SR_CH2A_FLAG TIM_M2_SR_CH2A_FLAG_MASK
//==CH1A捕获/比较中断标志
#define TIM_M2_SR_CH1A_FLAG_POS 3
#define TIM_M2_SR_CH1A_FLAG_MASK (0x01U<<TIM_M2_SR_CH1A_FLAG_POS)
#define TIM_M2_SR_CH1A_FLAG TIM_M2_SR_CH1A_FLAG_MASK
//==CH0A捕获/比较中断标志
#define TIM_M2_SR_CH0A_FLAG_POS 2
#define TIM_M2_SR_CH0A_FLAG_MASK (0x01U<<TIM_M2_SR_CH0A_FLAG_POS)
#define TIM_M2_SR_CH0A_FLAG TIM_M2_SR_CH0A_FLAG_MASK
//===更新中断标志位
#define TIM_M2_SR_UIE_POS 0
#define TIM_M2_SR_UIE_MASK (0x01U<<TIM_M2_SR_UIE_POS)
#define TIM_M2_SR_UIE TIM_M2_SR_UIE_MASK
//===清楚标志寄存器
#define TIM_M2_CSR_MASK 0xFFFDUL
#define TIM_M2_CSR_TIE_POS 15
#define TIM_M2_CSR_TIE_MASK (0x01U<<TIM_M2_CSR_TIE_POS)
#define TIM_M2_CSR_TIE TIM_M2_CSR_TIE_MASK
#define TIM_M2_CSR_BIE_POS 14
#define TIM_M2_CSR_BIE_MASK (0x01U<<TIM_M2_CSR_BIE_POS)
#define TIM_M2_CSR_BIE TIM_M2_CSR_BIE_MASK
#define TIM_M2_CSR_CH2B_ERROR_POS 13
#define TIM_M2_CSR_CH2B_ERROR_MASK (0x01U<<TIM_M2_CSR_CH2B_ERROR_POS)
#define TIM_M2_CSR_CH2B_ERROR TIM_M2_CSR_CH2B_ERROR_MASK
#define TIM_M2_CSR_CH1B_ERROR_POS 12
#define TIM_M2_CSR_CH1B_ERROR_MASK (0x01U<<TIM_M2_CSR_CH1B_ERROR_POS)
#define TIM_M2_CSR_CH1B_ERROR TIM_M2_CSR_CH1B_ERROR_MASK
#define TIM_M2_CSR_CH0B_ERROR_POS 11
#define TIM_M2_CSR_CH0B_ERROR_MASK (0x01U<<TIM_M2_CSR_CH0B_ERROR_POS)
#define TIM_M2_CSR_CH0B_ERROR TIM_M2_CSR_CH0B_ERROR_MASK
#define TIM_M2_CSR_CH2A_ERROR_POS 10
#define TIM_M2_CSR_CH2A_ERROR_MASK (0x01U<<TIM_M2_CSR_CH2A_ERROR_POS)
#define TIM_M2_CSR_CH2A_ERROR TIM_M2_CSR_CH2A_ERROR_MASK
#define TIM_M2_CSR_CH1A_ERROR_POS 9
#define TIM_M2_CSR_CH1A_ERROR_MASK (0x01U<<TIM_M2_CSR_CH1A_ERROR_POS)
#define TIM_M2_CSR_CH1A_ERROR TIM_M2_CSR_CH1A_ERROR_MASK
#define TIM_M2_CSR_CH0A_ERROR_POS 8
#define TIM_M2_CSR_CH0A_ERROR_MASK (0x01U<<TIM_M2_CSR_CH0A_ERROR_POS)
#define TIM_M2_CSR_CH0A_ERROR TIM_M2_CSR_CH0A_ERROR_MASK
#define TIM_M2_CSR_CH2B_FLAG_POS 7
#define TIM_M2_CSR_CH2B_FLAG_MASK (0x01U<<TIM_M2_CSR_CH2B_FLAG_POS)
#define TIM_M2_CSR_CH2B_FLAG TIM_M2_CSR_CH2B_FLAG_MASK
#define TIM_M2_CSR_CH1B_FLAG_POS 6
#define TIM_M2_CSR_CH1B_FLAG_MASK (0x01U<<TIM_M2_CSR_CH1B_FLAG_POS)
#define TIM_M2_CSR_CH1B_FLAG TIM_M2_CSR_CH1B_FLAG_MASK
#define TIM_M2_CSR_CH0B_FLAG_POS 5
#define TIM_M2_CSR_CH0B_FLAG_MASK (0x01U<<TIM_M2_CSR_CH0B_FLAG_POS)
#define TIM_M2_CSR_CH0B_FLAG TIM_M2_CSR_CH0B_FLAG_MASK
#define TIM_M2_CSR_CH2A_FLAG_POS 4
#define TIM_M2_CSR_CH2A_FLAG_MASK (0x01U<<TIM_M2_CSR_CH2A_FLAG_POS)
#define TIM_M2_CSR_CH2A_FLAG TIM_M2_CSR_CH2A_FLAG_MASK
#define TIM_M2_CSR_CH1A_FLAG_POS 3
#define TIM_M2_CSR_CH1A_FLAG_MASK (0x01U<<TIM_M2_CSR_CH1A_FLAG_POS)
#define TIM_M2_CSR_CH1A_FLAG TIM_M2_CSR_CH1A_FLAG_MASK
#define TIM_M2_CSR_CH0A_FLAG_POS 2
#define TIM_M2_CSR_CH0A_FLAG_MASK (0x01U<<TIM_M2_CSR_CH0A_FLAG_POS)
#define TIM_M2_CSR_CH0A_FLAG TIM_M2_CSR_CH0A_FLAG_MASK
#define TIM_M2_CSR_UIE_POS 0
#define TIM_M2_CSR_UIE_MASK (0x01U<<TIM_M2_CSR_UIE_POS)
#define TIM_M2_CSR_UIE TIM_M2_CSR_UIE_MASK
//===主从模式控制寄存器
//===CH0B输入选择
#define TIM_M2_MSCR_IB0S_POS 12
#define TIM_M2_MSCR_IB0S_MASK (0x01U<<TIM_M2_MSCR_IB0S_POS)
#define TIM_M2_MSCR_IB0S TIM_M2_MSCR_IB0S_MASK
//===CH0A输入选择
#define TIM_M2_MSCR_IA0S_POS 11
#define TIM_M2_MSCR_IA0S_MASK (0x01U<<TIM_M2_MSCR_IA0S_POS)
#define TIM_M2_MSCR_IA0S TIM_M2_MSCR_IA0S_MASK
//===从模式选择
#define TIM_M2_MSCR_SMS_POS 8
#define TIM_M2_MSCR_SMS_MASK (0x07U<<TIM_M2_MSCR_SMS_POS)
#define TIM_M2_MSCR_SMS TIM_M2_MSCR_SMS_MASK
#define TIM_M2_MSCR_SMS_TCLK (0x00U<<TIM_M2_MSCR_SMS_POS)
#define TIM_M2_MSCR_SMS_RESET (0x01U<<TIM_M2_MSCR_SMS_POS)
#define TIM_M2_MSCR_SMS_TRIG (0x02U<<TIM_M2_MSCR_SMS_POS)
#define TIM_M2_MSCR_SMS_ETR (0x03U<<TIM_M2_MSCR_SMS_POS)
#define TIM_M2_MSCR_SMS_ENCODE_MODE1 (0x04U<<TIM_M2_MSCR_SMS_POS)
#define TIM_M2_MSCR_SMS_ENCODE_MODE2 (0x05U<<TIM_M2_MSCR_SMS_POS)
#define TIM_M2_MSCR_SMS_ENCODE_MODE3 (0x06U<<TIM_M2_MSCR_SMS_POS)
#define TIM_M2_MSCR_SMS_GATE (0x07U<<TIM_M2_MSCR_SMS_POS)
//===触发模式选择
#define TIM_M2_MSCR_TRIG_POS 5
#define TIM_M2_MSCR_TRIG_MASK (0x07U<<TIM_M2_MSCR_TRIG_POS)
#define TIM_M2_MSCR_TRIG TIM_M2_MSCR_TRIG_MASK
#define TIM_M2_MSCR_TRIG_ETRP (0x00U<<TIM_M2_MSCR_TRIG_POS)
#define TIM_M2_MSCR_TRIG_ITR0 (0x01U<<TIM_M2_MSCR_TRIG_POS)
#define TIM_M2_MSCR_TRIG_ITR1 (0x02U<<TIM_M2_MSCR_TRIG_POS)
#define TIM_M2_MSCR_TRIG_ITR2 (0x03U<<TIM_M2_MSCR_TRIG_POS)
#define TIM_M2_MSCR_TRIG_ITR3 (0x04U<<TIM_M2_MSCR_TRIG_POS)
#define TIM_M2_MSCR_TRIG_CH0A (0x05U<<TIM_M2_MSCR_TRIG_POS)
#define TIM_M2_MSCR_TRIG_CH0AP (0x06U<<TIM_M2_MSCR_TRIG_POS)
#define TIM_M2_MSCR_TRIG_CH0BP (0x07U<<TIM_M2_MSCR_TRIG_POS)
//===主从模式选择
#define TIM_M2_MSCR_MSM_POS 4
#define TIM_M2_MSCR_MSM_MASK (0x07U<<TIM_M2_MSCR_MSM_POS)
#define TIM_M2_MSCR_MSM TIM_M2_MSCR_MSM_MASK
//===比较模式下DMA比较触发选择
#define TIM_M2_MSCR_CCDS_POS 3
#define TIM_M2_MSCR_CCDS_MASK (0x07U<<TIM_M2_MSCR_CCDS_POS)
#define TIM_M2_MSCR_CCDS TIM_M2_MSCR_CCDS_MASK
//===主模式输出选择
#define TIM_M2_MSCR_MMS_POS 0
#define TIM_M2_MSCR_MMS_MASK (0x07UL<<TIM_M2_MSCR_MMS_POS)
#define TIM_M2_MSCR_MMS TIM_M2_MSCR_MMS_MASK
#define TIM_M2_MSCR_MMS_UG (0x00U<<TIM_M2_MSCR_MMS_POS)
#define TIM_M2_MSCR_MMS_EN (0x01U<<TIM_M2_MSCR_MMS_POS)
#define TIM_M2_MSCR_MMS_UEV (0x02U<<TIM_M2_MSCR_MMS_POS)
#define TIM_M2_MSCR_MMS_CMPSO (0x03U<<TIM_M2_MSCR_MMS_POS)
#define TIM_M2_MSCR_MMS_OCREF0A (0x04U<<TIM_M2_MSCR_MMS_POS)
#define TIM_M2_MSCR_MMS_OCREF1A (0x05U<<TIM_M2_MSCR_MMS_POS)
#define TIM_M2_MSCR_MMS_OCREF2A (0x06U<<TIM_M2_MSCR_MMS_POS)
#define TIM_M2_MSCR_MMS_OCREF0B (0x07U<<TIM_M2_MSCR_MMS_POS)
//===滤波控制寄存器
//===ETR输入相位
#define TIM_M2_FLTR_ETP_POS 31
#define TIM_M2_FLTR_ETP_MASK (0x01UL<<TIM_M2_FLTR_ETP_POS)
#define TIM_M2_FLTR_ETP TIM_M2_FLTR_ETP_MASK
//===ETR滤波控制
#define TIM_M2_FLTR_ETR_POS 28
#define TIM_M2_FLTR_ETR_MASK (0x07UL<<TIM_M2_FLTR_ETR_POS)
#define TIM_M2_FLTR_ETR TIM_M2_FLTR_ETR_MASK
#define TIM_M2_FLTR_ETR_NONE (0x00U<<TIM_M2_FLTR_ETR_POS)
#define TIM_M2_FLTR_ETR_PCLK_DIV1 (0x04U<<TIM_M2_FLTR_ETR_POS)
#define TIM_M2_FLTR_ETR_PCLK_DIV4 (0x05U<<TIM_M2_FLTR_ETR_POS)
#define TIM_M2_FLTR_ETR_PCLK_DIV16 (0x06U<<TIM_M2_FLTR_ETR_POS)
#define TIM_M2_FLTR_ETR_PCLK_DIV64 (0x07U<<TIM_M2_FLTR_ETR_POS)
//===刹车BK输入相位选择
#define TIM_M2_FLTR_BKP_POS 27
#define TIM_M2_FLTR_BKP_MASK (0x01U<<TIM_M2_FLTR_BKP_POS)
#define TIM_M2_FLTR_BKP TIM_M2_FLTR_BKP_MASK
//===刹车输入滤波控制
#define TIM_M2_FLTR_BKR_POS 24
#define TIM_M2_FLTR_BKR_MASK (0x07UL<<TIM_M2_FLTR_BKR_POS)
#define TIM_M2_FLTR_BKR TIM_M2_FLTR_BKR_MASK
#define TIM_M2_FLTR_BKR_NONE (0x00UL<<TIM_M2_FLTR_BKR_POS)
#define TIM_M2_FLTR_BKR_PCLK_DIV1 (0x04UL<<TIM_M2_FLTR_BKR_POS)
#define TIM_M2_FLTR_BKR_PCLK_DIV4 (0x05UL<<TIM_M2_FLTR_BKR_POS)
#define TIM_M2_FLTR_BKR_PCLK_DIV16 (0x06UL<<TIM_M2_FLTR_BKR_POS)
#define TIM_M2_FLTR_BKR_PCLK_DIV64 (0x07UL<<TIM_M2_FLTR_BKR_POS)
//===CH2B比较输出相位控制
#define TIM_M2_FLTR_CCPB2_POS 23
#define TIM_M2_FLTR_CCPB2_MASK (0x01UL<<TIM_M2_FLTR_CCPB2_POS)
#define TIM_M2_FLTR_CCPB2 TIM_M2_FLTR_CCPB2_MASK
//==CH2B比较输出控制
#define TIM_M2_FLTR_OCMB2_POS 20
#define TIM_M2_FLTR_OCMB2_MASK (0x07UL<<TIM_M2_FLTR_OCMB2_POS)
#define TIM_M2_FLTR_OCMB2 TIM_M2_FLTR_OCMB2_MASK
#define TIM_M2_FLTR_OCMB2_FORCE_LOW (0x00UL<<TIM_M2_FLTR_OCMB2_POS)
#define TIM_M2_FLTR_OCMB2_FORCE_HIGH (0x01UL<<TIM_M2_FLTR_OCMB2_POS)
#define TIM_M2_FLTR_OCMB2_COMP_LOW (0x02UL<<TIM_M2_FLTR_OCMB2_POS)
#define TIM_M2_FLTR_OCMB2_COMP_HIGH (0x03UL<<TIM_M2_FLTR_OCMB2_POS)
#define TIM_M2_FLTR_OCMB2_COMP_TOGGLE (0x04UL<<TIM_M2_FLTR_OCMB2_POS)
#define TIM_M2_FLTR_OCMB2_COMP_KEEP_HIGH (0x05UL<<TIM_M2_FLTR_OCMB2_POS)
#define TIM_M2_FLTR_OCMB2_PWM_MODE1 (0x06UL<<TIM_M2_FLTR_OCMB2_POS)
#define TIM_M2_FLTR_OCMB2_PWM_MODE2 (0x07UL<<TIM_M2_FLTR_OCMB2_POS)
//==CH2B捕获输入滤波控制
#define TIM_M2_FLTR_CH2B_POS 20
#define TIM_M2_FLTR_CH2B_MASK (0x07UL<<TIM_M2_FLTR_CH2B_POS)
#define TIM_M2_FLTR_CH2B TIM_M2_FLTR_CH2B_MASK
#define TIM_M2_FLTR_CH2B_NONE (0x00U<<TIM_M2_FLTR_CH2B_POS)
#define TIM_M2_FLTR_CH2B_PCLK_DIV1 (0x04U<<TIM_M2_FLTR_CH2B_POS)
#define TIM_M2_FLTR_CH2B_PCLK_DIV4 (0x05U<<TIM_M2_FLTR_CH2B_POS)
#define TIM_M2_FLTR_CH2B_PCLK_DIV16 (0x06U<<TIM_M2_FLTR_CH2B_POS)
#define TIM_M2_FLTR_CH2B_PCLK_DIV64 (0x07U<<TIM_M2_FLTR_CH2B_POS)
//===CH2A比较输出相位控制
#define TIM_M2_FLTR_CCPA2_POS 19
#define TIM_M2_FLTR_CCPA2_MASK (0x01UL<<TIM_M2_FLTR_CCPA2_POS)
#define TIM_M2_FLTR_CCPA2 TIM_M2_FLTR_CCPA2_MASK
//==CH2A比较输出控制
#define TIM_M2_FLTR_OCMA2_POS 16
#define TIM_M2_FLTR_OCMA2_MASK (0x07UL<<TIM_M2_FLTR_OCMA2_POS)
#define TIM_M2_FLTR_OCMA2 TIM_M2_FLTR_OCMA2_MASK
#define TIM_M2_FLTR_OCMA2_FORCE_LOW (0x00UL<<TIM_M2_FLTR_OCMA2_POS)
#define TIM_M2_FLTR_OCMA2_FORCE_HIGH (0x01UL<<TIM_M2_FLTR_OCMA2_POS)
#define TIM_M2_FLTR_OCMA2_COMP_LOW (0x02UL<<TIM_M2_FLTR_OCMA2_POS)
#define TIM_M2_FLTR_OCMA2_COMP_HIGH (0x03UL<<TIM_M2_FLTR_OCMA2_POS)
#define TIM_M2_FLTR_OCMA2_COMP_TOGGLE (0x04UL<<TIM_M2_FLTR_OCMA2_POS)
#define TIM_M2_FLTR_OCMA2_COMP_KEEP_HIGH (0x05UL<<TIM_M2_FLTR_OCMA2_POS)
#define TIM_M2_FLTR_OCMA2_PWM_MODE1 (0x06UL<<TIM_M2_FLTR_OCMA2_POS)
#define TIM_M2_FLTR_OCMA2_PWM_MODE2 (0x07UL<<TIM_M2_FLTR_OCMA2_POS)
//==CH2A捕获输入滤波控制
#define TIM_M2_FLTR_CH2A_POS 16
#define TIM_M2_FLTR_CH2A_MASK (0x07UL<<TIM_M2_FLTR_CH2A_POS)
#define TIM_M2_FLTR_CH2A TIM_M2_FLTR_CH2A_MASK
#define TIM_M2_FLTR_CH2A_NONE (0x00UL<<TIM_M2_FLTR_CH2A_POS)
#define TIM_M2_FLTR_CH2A_PCLK_DIV1 (0x04UL<<TIM_M2_FLTR_CH2A_POS)
#define TIM_M2_FLTR_CH2A_PCLK_DIV4 (0x05UL<<TIM_M2_FLTR_CH2A_POS)
#define TIM_M2_FLTR_CH2A_PCLK_DIV16 (0x06UL<<TIM_M2_FLTR_CH2A_POS)
#define TIM_M2_FLTR_CH2A_PCLK_DIV64 (0x07UL<<TIM_M2_FLTR_CH2A_POS)
//===CH1B比较输出相位控制
#define TIM_M2_FLTR_CCPB1_POS 15
#define TIM_M2_FLTR_CCPB1_MASK (0x01UL<<TIM_M2_FLTR_CCPB1_POS)
#define TIM_M2_FLTR_CCPB1 TIM_M2_FLTR_CCPB1_MASK
//==CH1B比较输出控制
#define TIM_M2_FLTR_OCMB1_POS 12
#define TIM_M2_FLTR_OCMB1_MASK (0x07UL<<TIM_M2_FLTR_OCMB1_POS)
#define TIM_M2_FLTR_OCMB1 TIM_M2_FLTR_OCMB1_MASK
#define TIM_M2_FLTR_OCMB1_FORCE_LOW (0x00UL<<TIM_M2_FLTR_OCMB1_POS)
#define TIM_M2_FLTR_OCMB1_FORCE_HIGH (0x01UL<<TIM_M2_FLTR_OCMB1_POS)
#define TIM_M2_FLTR_OCMB1_COMP_LOW (0x02UL<<TIM_M2_FLTR_OCMB1_POS)
#define TIM_M2_FLTR_OCMB1_COMP_HIGH (0x03UL<<TIM_M2_FLTR_OCMB1_POS)
#define TIM_M2_FLTR_OCMB1_COMP_TOGGLE (0x04UL<<TIM_M2_FLTR_OCMB1_POS)
#define TIM_M2_FLTR_OCMB1_COMP_KEEP_HIGH (0x05UL<<TIM_M2_FLTR_OCMB1_POS)
#define TIM_M2_FLTR_OCMB1_PWM_MODE1 (0x06UL<<TIM_M2_FLTR_OCMB1_POS)
#define TIM_M2_FLTR_OCMB1_PWM_MODE2 (0x07UL<<TIM_M2_FLTR_OCMB1_POS)
//==CH1B捕获输入滤波控制
#define TIM_M2_FLTR_CH1B_POS 12
#define TIM_M2_FLTR_CH1B_MASK (0x07UL<<TIM_M2_FLTR_CH1B_POS)
#define TIM_M2_FLTR_CH1B TIM_M2_FLTR_CH1B_MASK
#define TIM_M2_FLTR_CH1B_NONE (0x00UL<<TIM_M2_FLTR_CH1B_POS)
#define TIM_M2_FLTR_CH1B_PCLK_DIV1 (0x04UL<<TIM_M2_FLTR_CH1B_POS)
#define TIM_M2_FLTR_CH1B_PCLK_DIV4 (0x05UL<<TIM_M2_FLTR_CH1B_POS)
#define TIM_M2_FLTR_CH1B_PCLK_DIV16 (0x06UL<<TIM_M2_FLTR_CH1B_POS)
#define TIM_M2_FLTR_CH1B_PCLK_DIV64 (0x07UL<<TIM_M2_FLTR_CH1B_POS)
//===CH1A比较输出相位控制
#define TIM_M2_FLTR_CCPA1_POS 11
#define TIM_M2_FLTR_CCPA1_MASK (0x01UL<<TIM_M2_FLTR_CCPA1_POS)
#define TIM_M2_FLTR_CCPA1 TIM_M2_FLTR_CCPA1_MASK
//==CH1A比较输出控制
#define TIM_M2_FLTR_OCMA1_POS 8
#define TIM_M2_FLTR_OCMA1_MASK (0x07UL<<TIM_M2_FLTR_OCMA1_POS)
#define TIM_M2_FLTR_OCMA1 TIM_M2_FLTR_OCMA1_MASK
#define TIM_M2_FLTR_OCMA1_FORCE_LOW (0x00UL<<TIM_M2_FLTR_OCMA1_POS)
#define TIM_M2_FLTR_OCMA1_FORCE_HIGH (0x01UL<<TIM_M2_FLTR_OCMA1_POS)
#define TIM_M2_FLTR_OCMA1_COMP_LOW (0x02UL<<TIM_M2_FLTR_OCMA1_POS)
#define TIM_M2_FLTR_OCMA1_COMP_HIGH (0x03UL<<TIM_M2_FLTR_OCMA1_POS)
#define TIM_M2_FLTR_OCMA1_COMP_TOGGLE (0x04UL<<TIM_M2_FLTR_OCMA1_POS)
#define TIM_M2_FLTR_OCMA1_COMP_KEEP_HIGH (0x05UL<<TIM_M2_FLTR_OCMA1_POS)
#define TIM_M2_FLTR_OCMA1_PWM_MODE1 (0x06UL<<TIM_M2_FLTR_OCMA1_POS)
#define TIM_M2_FLTR_OCMA1_PWM_MODE2 (0x07UL<<TIM_M2_FLTR_OCMA1_POS)
//==CH1A捕获输入滤波控制
#define TIM_M2_FLTR_CH1A_POS 8
#define TIM_M2_FLTR_CH1A_MASK (0x07UL<<TIM_M2_FLTR_CH1A_POS)
#define TIM_M2_FLTR_CH1A TIM_M2_FLTR_CH1A_MASK
#define TIM_M2_FLTR_CH1A_NONE (0x00UL<<TIM_M2_FLTR_CH1A_POS)
#define TIM_M2_FLTR_CH1A_PCLK_DIV1 (0x04UL<<TIM_M2_FLTR_CH1A_POS)
#define TIM_M2_FLTR_CH1A_PCLK_DIV4 (0x05UL<<TIM_M2_FLTR_CH1A_POS)
#define TIM_M2_FLTR_CH1A_PCLK_DIV16 (0x06UL<<TIM_M2_FLTR_CH1A_POS)
#define TIM_M2_FLTR_CH1A_PCLK_DIV64 (0x07UL<<TIM_M2_FLTR_CH1A_POS)
//===CH0B比较输出相位控制
#define TIM_M2_FLTR_CCPB0_POS 7
#define TIM_M2_FLTR_CCPB0_MASK (0x01UL<<TIM_M2_FLTR_CCPB0_POS)
#define TIM_M2_FLTR_CCPB0 TIM_M2_FLTR_CCPB0_MASK
//==CH0B捕获输入滤波控制
#define TIM_M2_FLTR_OCMB0_POS 4
#define TIM_M2_FLTR_OCMB0_MASK (0x07UL<<TIM_M2_FLTR_OCMB0_POS)
#define TIM_M2_FLTR_OCMB0 TIM_M2_FLTR_OCMB0_MASK
#define TIM_M2_FLTR_OCMB0_FORCE_LOW (0x00UL<<TIM_M2_FLTR_OCMB0_POS)
#define TIM_M2_FLTR_OCMB0_FORCE_HIGH (0x01UL<<TIM_M2_FLTR_OCMB0_POS)
#define TIM_M2_FLTR_OCMB0_COMP_LOW (0x02UL<<TIM_M2_FLTR_OCMB0_POS)
#define TIM_M2_FLTR_OCMB0_COMP_HIGH (0x03UL<<TIM_M2_FLTR_OCMB0_POS)
#define TIM_M2_FLTR_OCMB0_COMP_TOGGLE (0x04UL<<TIM_M2_FLTR_OCMB0_POS)
#define TIM_M2_FLTR_OCMB0_COMP_KEEP_HIGH (0x05UL<<TIM_M2_FLTR_OCMB0_POS)
#define TIM_M2_FLTR_OCMB0_PWM_MODE1 (0x06UL<<TIM_M2_FLTR_OCMB0_POS)
#define TIM_M2_FLTR_OCMB0_PWM_MODE2 (0x07UL<<TIM_M2_FLTR_OCMB0_POS)
//==CH0B捕获输入滤波控制
#define TIM_M2_FLTR_CH0B_POS 4
#define TIM_M2_FLTR_CH0B_MASK (0x07UL<<TIM_M2_FLTR_CH0B_POS)
#define TIM_M2_FLTR_CH0B TIM_M2_FLTR_CH0B_MASK
#define TIM_M2_FLTR_CH0B_NONE (0x00UL<<TIM_M2_FLTR_CH0B_POS)
#define TIM_M2_FLTR_CH0B_PCLK_DIV1 (0x04UL<<TIM_M2_FLTR_CH0B_POS)
#define TIM_M2_FLTR_CH0B_PCLK_DIV4 (0x05UL<<TIM_M2_FLTR_CH0B_POS)
#define TIM_M2_FLTR_CH0B_PCLK_DIV16 (0x06UL<<TIM_M2_FLTR_CH0B_POS)
#define TIM_M2_FLTR_CH0B_PCLK_DIV64 (0x07UL<<TIM_M2_FLTR_CH0B_POS)
//===CH0A比较输出相位控制
#define TIM_M2_FLTR_CCPA0_POS 3
#define TIM_M2_FLTR_CCPA0_MASK (0x01UL<<TIM_M2_FLTR_CCPA0_POS)
#define TIM_M2_FLTR_CCPA0 TIM_M2_FLTR_CCPA0_MASK
//==CH0A比较输出控制
#define TIM_M2_FLTR_OCMA0_POS 0
#define TIM_M2_FLTR_OCMA0_MASK (0x07UL<<TIM_M2_FLTR_OCMA0_POS)
#define TIM_M2_FLTR_OCMA0 TIM_M2_FLTR_OCMA0_MASK
#define TIM_M2_FLTR_OCMA0_FORCE_LOW (0x00UL<<TIM_M2_FLTR_OCMA0_POS)
#define TIM_M2_FLTR_OCMA0_FORCE_HIGH (0x01UL<<TIM_M2_FLTR_OCMA0_POS)
#define TIM_M2_FLTR_OCMA0_COMP_LOW (0x02UL<<TIM_M2_FLTR_OCMA0_POS)
#define TIM_M2_FLTR_OCMA0_COMP_HIGH (0x03UL<<TIM_M2_FLTR_OCMA0_POS)
#define TIM_M2_FLTR_OCMA0_COMP_TOGGLE (0x04UL<<TIM_M2_FLTR_OCMA0_POS)
#define TIM_M2_FLTR_OCMA0_COMP_KEEP_HIGH (0x05UL<<TIM_M2_FLTR_OCMA0_POS)
#define TIM_M2_FLTR_OCMA0_PWM_MODE1 (0x06UL<<TIM_M2_FLTR_OCMA0_POS)
#define TIM_M2_FLTR_OCMA0_PWM_MODE2 (0x07UL<<TIM_M2_FLTR_OCMA0_POS)
//==CH0A捕获输入滤波控制
#define TIM_M2_FLTR_CH0A_POS 0
#define TIM_M2_FLTR_CH0A_MASK (0x07UL<<TIM_M2_FLTR_CH0A_POS)
#define TIM_M2_FLTR_CH0A TIM_M2_FLTR_CH0A_MASK
#define TIM_M2_FLTR_CH0A_NONE (0x00UL<<TIM_M2_FLTR_CH0A_POS)
#define TIM_M2_FLTR_CH0A_PCLK_DIV1 (0x04UL<<TIM_M2_FLTR_CH0A_POS)
#define TIM_M2_FLTR_CH0A_PCLK_DIV4 (0x05UL<<TIM_M2_FLTR_CH0A_POS)
#define TIM_M2_FLTR_CH0A_PCLK_DIV16 (0x06UL<<TIM_M2_FLTR_CH0A_POS)
#define TIM_M2_FLTR_CH0A_PCLK_DIV64 (0x07UL<<TIM_M2_FLTR_CH0A_POS)
//===ADC触发控制寄存器
#define TIM_M2_ADTR_EN_POS 7
#define TIM_M2_ADTR_EN_MASK (0x01UL<<TIM_M2_ADTR_EN_POS)
#define TIM_M2_ADTR_EN TIM_M2_ADTR_EN_MASK
//===CH2B比较匹配触发adc
#define TIM_M2_ADTR_CMB2EN_POS 6
#define TIM_M2_ADTR_CMB2EN_MASK (0x01UL<<TIM_M2_ADTR_CMB2EN_POS)
#define TIM_M2_ADTR_CMB2EN TIM_M2_ADTR_CMB2EN_MASK
//===CH1B比较匹配触发adc
#define TIM_M2_ADTR_CMB1EN_POS 5
#define TIM_M2_ADTR_CMB1EN_MASK (0x01UL<<TIM_M2_ADTR_CMB1EN_POS)
#define TIM_M2_ADTR_CMB1EN TIM_M2_ADTR_CMB1EN_MASK
//===CH0B比较匹配触发adc
#define TIM_M2_ADTR_CMB0EN_POS 4
#define TIM_M2_ADTR_CMB0EN_MASK (0x01UL<<TIM_M2_ADTR_CMB0EN_POS)
#define TIM_M2_ADTR_CMB0EN TIM_M2_ADTR_CMB0EN_MASK
//===CH2A比较匹配触发adc
#define TIM_M2_ADTR_CMA2EN_POS 3
#define TIM_M2_ADTR_CMA2EN_MASK (0x01UL<<TIM_M2_ADTR_CMA2EN_POS)
#define TIM_M2_ADTR_CMA2EN TIM_M2_ADTR_CMA2EN_MASK
//===CH0A比较匹配触发adc
#define TIM_M2_ADTR_CMA1EN_POS 2
#define TIM_M2_ADTR_CMA1EN_MASK (0x01UL<<TIM_M2_ADTR_CMA1EN_POS)
#define TIM_M2_ADTR_CMA1EN TIM_M2_ADTR_CMA1EN_MASK
//===CH0A比较匹配触发adc
#define TIM_M2_ADTR_CMA0EN_POS 1
#define TIM_M2_ADTR_CMA0EN_MASK (0x01UL<<TIM_M2_ADTR_CMA0EN_POS)
#define TIM_M2_ADTR_CMA0EN TIM_M2_ADTR_CMA0EN_MASK
//===事件更新触发adc
#define TIM_M2_ADTR_UEN_POS 0
#define TIM_M2_ADTR_UEN_MASK (0x01UL<<TIM_M2_ADTR_UEN_POS)
#define TIM_M2_ADTR_UEN TIM_M2_ADTR_UEN_MASK
//===通道0控制寄存器
//===捕获比较B软件触发
#define TIM_M2_CRCH0_CCGB_POS 15
#define TIM_M2_CRCH0_CCGB_MASK (0x01UL<<TIM_M2_CRCH0_CCGB_POS)
#define TIM_M2_CRCH0_CCGB TIM_M2_CRCH0_CCGB_MASK
//===捕获比较A软件触发
#define TIM_M2_CRCH0_CCGA_POS 14
#define TIM_M2_CRCH0_CCGA_MASK (0x01UL<<TIM_M2_CRCH0_CCGA_POS)
#define TIM_M2_CRCH0_CCGA TIM_M2_CRCH0_CCGA_MASK
//===B比较模式中断
#define TIM_M2_CRCH0_CISB_POS 13
#define TIM_M2_CRCH0_CISB_MASK (0x03UL<<TIM_M2_CRCH0_CISB_POS)
#define TIM_M2_CRCH0_CISB TIM_M2_CRCH0_CISB_MASK
#define TIM_M2_CRCH0_CISB_EDGE_NONE (0x00UL<<TIM_M2_CRCH0_CISB_POS)
#define TIM_M2_CRCH0_CISB_EDGE_RISE (0x01UL<<TIM_M2_CRCH0_CISB_POS)
#define TIM_M2_CRCH0_CISB_EDGE_FAIL (0x02UL<<TIM_M2_CRCH0_CISB_POS)
#define TIM_M2_CRCH0_CISB_EDGE_ALL (0x03UL<<TIM_M2_CRCH0_CISB_POS)
//===B捕获比较触发DMA使能
#define TIM_M2_CRCH0_CDMABEN_POS 11
#define TIM_M2_CRCH0_CDMABEN_MASK (0x01UL<<TIM_M2_CRCH0_CDMABEN_POS)
#define TIM_M2_CRCH0_CDMABEN TIM_M2_CRCH0_CDMABEN_MASK
//===A捕获比较触发DMA使能
#define TIM_M2_CRCH0_CDMAAEN_POS 10
#define TIM_M2_CRCH0_CDMAAEN_MASK (0x01UL<<TIM_M2_CRCH0_CDMAAEN_POS)
#define TIM_M2_CRCH0_CDMAAEN TIM_M2_CRCH0_CDMAAEN_MASK
//===B捕获比较触发中断
#define TIM_M2_CRCH0_CIEB_POS 9
#define TIM_M2_CRCH0_CIEB_MASK (0x01UL<<TIM_M2_CRCH0_CIEB_POS)
#define TIM_M2_CRCH0_CIEB TIM_M2_CRCH0_CIEB_MASK
//===B捕获比较触发中断
#define TIM_M2_CRCH0_CIEA_POS 8
#define TIM_M2_CRCH0_CIEA_MASK (0x01UL<<TIM_M2_CRCH0_CIEA_POS)
#define TIM_M2_CRCH0_CIEA TIM_M2_CRCH0_CIEA_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M2_CRCH0_BUFEB_POS 7
#define TIM_M2_CRCH0_BUFEB_MASK (0x01UL<<TIM_M2_CRCH0_BUFEB_POS)
#define TIM_M2_CRCH0_BUFEB TIM_M2_CRCH0_BUFEB_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M2_CRCH0_BUFEA_POS 6
#define TIM_M2_CRCH0_BUFEA_MASK (0x01UL<<TIM_M2_CRCH0_BUFEA_POS)
#define TIM_M2_CRCH0_BUFEA TIM_M2_CRCH0_BUFEA_MASK
#define TIM_M2_CRCH0_CSB_POS 5
#define TIM_M2_CRCH0_CSB_MASK (0x01UL<<TIM_M2_CRCH0_CSB_POS)
#define TIM_M2_CRCH0_CSB TIM_M2_CRCH0_CSB_MASK
#define TIM_M2_CRCH0_CSA_POS 4
#define TIM_M2_CRCH0_CSA_MASK (0x01UL<<TIM_M2_CRCH0_CSA_POS)
#define TIM_M2_CRCH0_CSA TIM_M2_CRCH0_CSA_MASK
#define TIM_M2_CRCH0_CFB_POS 3
#define TIM_M2_CRCH0_CFB_MASK (0x01UL<<TIM_M2_CRCH0_CFB_POS)
#define TIM_M2_CRCH0_CFB TIM_M2_CRCH0_CFB_MASK
#define TIM_M2_CRCH0_CRB_POS 2
#define TIM_M2_CRCH0_CRB_MASK (0x01UL<<TIM_M2_CRCH0_CRB_POS)
#define TIM_M2_CRCH0_CRB TIM_M2_CRCH0_CRB_MASK
//===B通道比较输出刹车电平控制
#define TIM_M2_CRCH0_BKSB_POS 2
#define TIM_M2_CRCH0_BKSB_MASK (0x03UL<<TIM_M2_CRCH0_BKSB_POS)
#define TIM_M2_CRCH0_BKSB TIM_M2_CRCH0_BKSB_MASK
#define TIM_M2_CRCH0_BKSB_HZ (0x00UL<<TIM_M2_CRCH0_BKSB_POS)
#define TIM_M2_CRCH0_BKSB_NONE (0x01UL<<TIM_M2_CRCH0_BKSB_POS)
#define TIM_M2_CRCH0_BKSB_LOW (0x02UL<<TIM_M2_CRCH0_BKSB_POS)
#define TIM_M2_CRCH0_BKSB_HIGHT (0x03UL<<TIM_M2_CRCH0_BKSB_POS)
#define TIM_M2_CRCH0_CFA_POS 1
#define TIM_M2_CRCH0_CFA_MASK (0x01UL<<TIM_M2_CRCH0_CFA_POS)
#define TIM_M2_CRCH0_CFA TIM_M2_CRCH0_CFA_MASK
#define TIM_M2_CRCH0_CRA_POS 0
#define TIM_M2_CRCH0_CRA_MASK (0x01UL<<TIM_M2_CRCH0_CRA_POS)
#define TIM_M2_CRCH0_CRA TIM_M2_CRCH0_CRA_MASK
#define TIM_M2_CRCH0_BKSA_POS 0
#define TIM_M2_CRCH0_BKSA_MASK (0x03UL<<TIM_M2_CRCH0_BKSA_POS)
#define TIM_M2_CRCH0_BKSA TIM_M2_CRCH0_BKSA_MASK
#define TIM_M2_CRCH0_BKSA_HZ (0x00UL<<TIM_M2_CRCH0_BKSA_POS)
#define TIM_M2_CRCH0_BKSA_NONE (0x01UL<<TIM_M2_CRCH0_BKSA_POS)
#define TIM_M2_CRCH0_BKSA_LOW (0x02UL<<TIM_M2_CRCH0_BKSA_POS)
#define TIM_M2_CRCH0_BKSA_HIGHT (0x03UL<<TIM_M2_CRCH0_BKSA_POS)
//===通道1控制寄存器
//===捕获比较B软件触发
#define TIM_M2_CRCH1_CCGB_POS 15
#define TIM_M2_CRCH1_CCGB_MASK (0x01UL<<TIM_M2_CRCH1_CCGB_POS)
#define TIM_M2_CRCH1_CCGB TIM_M2_CRCH1_CCGB_MASK
//===捕获比较A软件触发
#define TIM_M2_CRCH1_CCGA_POS 14
#define TIM_M2_CRCH1_CCGA_MASK (0x01UL<<TIM_M2_CRCH1_CCGA_POS)
#define TIM_M2_CRCH1_CCGA TIM_M2_CRCH1_CCGA_MASK
//===B比较模式中断
#define TIM_M2_CRCH1_CISB_POS 13
#define TIM_M2_CRCH1_CISB_MASK (0x03UL<<TIM_M2_CRCH1_CISB_POS)
#define TIM_M2_CRCH1_CISB TIM_M2_CRCH1_CISB_MASK
#define TIM_M2_CRCH1_CISB_EDGE_NONE (0x00UL<<TIM_M2_CRCH1_CISB_POS)
#define TIM_M2_CRCH1_CISB_EDGE_RISE (0x01UL<<TIM_M2_CRCH1_CISB_POS)
#define TIM_M2_CRCH1_CISB_EDGE_FAIL (0x02UL<<TIM_M2_CRCH1_CISB_POS)
#define TIM_M2_CRCH1_CISB_EDGE_ALL (0x03UL<<TIM_M2_CRCH1_CISB_POS)
//===B捕获比较触发DMA使能
#define TIM_M2_CRCH1_CDMABEN_POS 11
#define TIM_M2_CRCH1_CDMABEN_MASK (0x01UL<<TIM_M2_CRCH1_CDMABEN_POS)
#define TIM_M2_CRCH1_CDMABEN TIM_M2_CRCH1_CDMABEN_MASK
//===A捕获比较触发DMA使能
#define TIM_M2_CRCH1_CDMAAEN_POS 10
#define TIM_M2_CRCH1_CDMAAEN_MASK (0x01UL<<TIM_M2_CRCH1_CDMAAEN_POS)
#define TIM_M2_CRCH1_CDMAAEN TIM_M2_CRCH1_CDMAAEN_MASK
//===B捕获比较触发中断
#define TIM_M2_CRCH1_CIEB_POS 9
#define TIM_M2_CRCH1_CIEB_MASK (0x01UL<<TIM_M2_CRCH1_CIEB_POS)
#define TIM_M2_CRCH1_CIEB TIM_M2_CRCH1_CIEB_MASK
//===B捕获比较触发中断
#define TIM_M2_CRCH1_CIEA_POS 8
#define TIM_M2_CRCH1_CIEA_MASK (0x01UL<<TIM_M2_CRCH1_CIEA_POS)
#define TIM_M2_CRCH1_CIEA TIM_M2_CRCH1_CIEA_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M2_CRCH1_BUFEB_POS 7
#define TIM_M2_CRCH1_BUFEB_MASK (0x01UL<<TIM_M2_CRCH1_BUFEB_POS)
#define TIM_M2_CRCH1_BUFEB TIM_M2_CRCH1_BUFEB_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M2_CRCH1_BUFEA_POS 6
#define TIM_M2_CRCH1_BUFEA_MASK (0x01UL<<TIM_M2_CRCH1_BUFEA_POS)
#define TIM_M2_CRCH1_BUFEA TIM_M2_CRCH1_BUFEA_MASK
#define TIM_M2_CRCH1_CSB_POS 5
#define TIM_M2_CRCH1_CSB_MASK (0x01UL<<TIM_M2_CRCH1_CSB_POS)
#define TIM_M2_CRCH1_CSB TIM_M2_CRCH1_CSB_MASK
#define TIM_M2_CRCH1_CSA_POS 4
#define TIM_M2_CRCH1_CSA_MASK (0x01UL<<TIM_M2_CRCH1_CSA_POS)
#define TIM_M2_CRCH1_CSA TIM_M2_CRCH1_CSA_MASK
#define TIM_M2_CRCH1_CFB_POS 3
#define TIM_M2_CRCH1_CFB_MASK (0x01UL<<TIM_M2_CRCH1_CFB_POS)
#define TIM_M2_CRCH1_CFB TIM_M2_CRCH1_CFB_MASK
#define TIM_M2_CRCH1_CRB_POS 2
#define TIM_M2_CRCH1_CRB_MASK (0x01UL<<TIM_M2_CRCH1_CRB_POS)
#define TIM_M2_CRCH1_CRB TIM_M2_CRCH1_CRB_MASK
//===B通道比较输出刹车电平控制
#define TIM_M2_CRCH1_BKSB_POS 2
#define TIM_M2_CRCH1_BKSB_MASK (0x03UL<<TIM_M2_CRCH1_BKSB_POS)
#define TIM_M2_CRCH1_BKSB TIM_M2_CRCH1_BKSB_MASK
#define TIM_M2_CRCH1_BKSB_HZ (0x00UL<<TIM_M2_CRCH1_BKSB_POS)
#define TIM_M2_CRCH1_BKSB_NONE (0x01UL<<TIM_M2_CRCH1_BKSB_POS)
#define TIM_M2_CRCH1_BKSB_LOW (0x02UL<<TIM_M2_CRCH1_BKSB_POS)
#define TIM_M2_CRCH1_BKSB_HIGHT (0x03UL<<TIM_M2_CRCH1_BKSB_POS)
#define TIM_M2_CRCH1_CFA_POS 1
#define TIM_M2_CRCH1_CFA_MASK (0x01UL<<TIM_M2_CRCH1_CFA_POS)
#define TIM_M2_CRCH1_CFA TIM_M2_CRCH1_CFA_MASK
#define TIM_M2_CRCH1_CRA_POS 0
#define TIM_M2_CRCH1_CRA_MASK (0x01UL<<TIM_M2_CRCH1_CRA_POS)
#define TIM_M2_CRCH1_CRA TIM_M2_CRCH1_CRA_MASK
#define TIM_M2_CRCH1_BKSA_POS 0
#define TIM_M2_CRCH1_BKSA_MASK (0x03UL<<TIM_M2_CRCH1_BKSA_POS)
#define TIM_M2_CRCH1_BKSA TIM_M2_CRCH1_BKSA_MASK
#define TIM_M2_CRCH1_BKSA_HZ (0x00UL<<TIM_M2_CRCH1_BKSA_POS)
#define TIM_M2_CRCH1_BKSA_NONE (0x01UL<<TIM_M2_CRCH1_BKSA_POS)
#define TIM_M2_CRCH1_BKSA_LOW (0x02UL<<TIM_M2_CRCH1_BKSA_POS)
#define TIM_M2_CRCH1_BKSA_HIGHT (0x03UL<<TIM_M2_CRCH1_BKSA_POS)
//===通道2控制寄存器
//===捕获比较B软件触发
#define TIM_M2_CRCH2_CCGB_POS 15
#define TIM_M2_CRCH2_CCGB_MASK (0x01UL<<TIM_M2_CRCH2_CCGB_POS)
#define TIM_M2_CRCH2_CCGB TIM_M2_CRCH2_CCGB_MASK
//===捕获比较A软件触发
#define TIM_M2_CRCH2_CCGA_POS 14
#define TIM_M2_CRCH2_CCGA_MASK (0x01UL<<TIM_M2_CRCH2_CCGA_POS)
#define TIM_M2_CRCH2_CCGA TIM_M2_CRCH2_CCGA_MASK
//===B比较模式中断
#define TIM_M2_CRCH2_CISB_POS 13
#define TIM_M2_CRCH2_CISB_MASK (0x03UL<<TIM_M2_CRCH2_CISB_POS)
#define TIM_M2_CRCH2_CISB TIM_M2_CRCH2_CISB_MASK
#define TIM_M2_CRCH2_CISB_EDGE_NONE (0x00UL<<TIM_M2_CRCH2_CISB_POS)
#define TIM_M2_CRCH2_CISB_EDGE_RISE (0x01UL<<TIM_M2_CRCH2_CISB_POS)
#define TIM_M2_CRCH2_CISB_EDGE_FAIL (0x02UL<<TIM_M2_CRCH2_CISB_POS)
#define TIM_M2_CRCH2_CISB_EDGE_ALL (0x03UL<<TIM_M2_CRCH2_CISB_POS)
//===B捕获比较触发DMA使能
#define TIM_M2_CRCH2_CDMABEN_POS 11
#define TIM_M2_CRCH2_CDMABEN_MASK (0x01UL<<TIM_M2_CRCH2_CDMABEN_POS)
#define TIM_M2_CRCH2_CDMABEN TIM_M2_CRCH2_CDMABEN_MASK
//===A捕获比较触发DMA使能
#define TIM_M2_CRCH2_CDMAAEN_POS 10
#define TIM_M2_CRCH2_CDMAAEN_MASK (0x01UL<<TIM_M2_CRCH2_CDMAAEN_POS)
#define TIM_M2_CRCH2_CDMAAEN TIM_M2_CRCH2_CDMAAEN_MASK
//===B捕获比较触发中断
#define TIM_M2_CRCH2_CIEB_POS 9
#define TIM_M2_CRCH2_CIEB_MASK (0x01UL<<TIM_M2_CRCH2_CIEB_POS)
#define TIM_M2_CRCH2_CIEB TIM_M2_CRCH2_CIEB_MASK
//===B捕获比较触发中断
#define TIM_M2_CRCH2_CIEA_POS 8
#define TIM_M2_CRCH2_CIEA_MASK (0x01UL<<TIM_M2_CRCH2_CIEA_POS)
#define TIM_M2_CRCH2_CIEA TIM_M2_CRCH2_CIEA_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M2_CRCH2_BUFEB_POS 7
#define TIM_M2_CRCH2_BUFEB_MASK (0x01UL<<TIM_M2_CRCH2_BUFEB_POS)
#define TIM_M2_CRCH2_BUFEB TIM_M2_CRCH2_BUFEB_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M2_CRCH2_BUFEA_POS 6
#define TIM_M2_CRCH2_BUFEA_MASK (0x01UL<<TIM_M2_CRCH2_BUFEA_POS)
#define TIM_M2_CRCH2_BUFEA TIM_M2_CRCH2_BUFEA_MASK
#define TIM_M2_CRCH2_CSB_POS 5
#define TIM_M2_CRCH2_CSB_MASK (0x01UL<<TIM_M2_CRCH2_CSB_POS)
#define TIM_M2_CRCH2_CSB TIM_M2_CRCH2_CSB_MASK
#define TIM_M2_CRCH2_CSA_POS 4
#define TIM_M2_CRCH2_CSA_MASK (0x01UL<<TIM_M2_CRCH2_CSA_POS)
#define TIM_M2_CRCH2_CSA TIM_M2_CRCH2_CSA_MASK
#define TIM_M2_CRCH2_CFB_POS 3
#define TIM_M2_CRCH2_CFB_MASK (0x01UL<<TIM_M2_CRCH2_CFB_POS)
#define TIM_M2_CRCH2_CFB TIM_M2_CRCH2_CFB_MASK
#define TIM_M2_CRCH2_CRB_POS 2
#define TIM_M2_CRCH2_CRB_MASK (0x01UL<<TIM_M2_CRCH2_CRB_POS)
#define TIM_M2_CRCH2_CRB TIM_M2_CRCH2_CRB_MASK
//===B通道比较输出刹车电平控制
#define TIM_M2_CRCH2_BKSB_POS 2
#define TIM_M2_CRCH2_BKSB_MASK (0x03UL<<TIM_M2_CRCH2_BKSB_POS)
#define TIM_M2_CRCH2_BKSB TIM_M2_CRCH2_BKSB_MASK
#define TIM_M2_CRCH2_BKSB_HZ (0x00UL<<TIM_M2_CRCH2_BKSB_POS)
#define TIM_M2_CRCH2_BKSB_NONE (0x01UL<<TIM_M2_CRCH2_BKSB_POS)
#define TIM_M2_CRCH2_BKSB_LOW (0x02UL<<TIM_M2_CRCH2_BKSB_POS)
#define TIM_M2_CRCH2_BKSB_HIGHT (0x03UL<<TIM_M2_CRCH2_BKSB_POS)
#define TIM_M2_CRCH2_CFA_POS 1
#define TIM_M2_CRCH2_CFA_MASK (0x01UL<<TIM_M2_CRCH2_CFA_POS)
#define TIM_M2_CRCH2_CFA TIM_M2_CRCH2_CFA_MASK
#define TIM_M2_CRCH2_CRA_POS 0
#define TIM_M2_CRCH2_CRA_MASK (0x01UL<<TIM_M2_CRCH2_CRA_POS)
#define TIM_M2_CRCH2_CRA TIM_M2_CRCH2_CRA_MASK
#define TIM_M2_CRCH2_BKSA_POS 0
#define TIM_M2_CRCH2_BKSA_MASK (0x03UL<<TIM_M2_CRCH2_BKSA_POS)
#define TIM_M2_CRCH2_BKSA TIM_M2_CRCH2_BKSA_MASK
#define TIM_M2_CRCH2_BKSA_HZ (0x00UL<<TIM_M2_CRCH2_BKSA_POS)
#define TIM_M2_CRCH2_BKSA_NONE (0x01UL<<TIM_M2_CRCH2_BKSA_POS)
#define TIM_M2_CRCH2_BKSA_LOW (0x02UL<<TIM_M2_CRCH2_BKSA_POS)
#define TIM_M2_CRCH2_BKSA_HIGHT (0x03UL<<TIM_M2_CRCH2_BKSA_POS)
//===死区控制寄存器
#define TIM_M2_DTR_VCEN_POS 14
#define TIM_M2_DTR_VCEN_MASK (0x01UL<<TIM_M2_DTR_VCEN_POS)
#define TIM_M2_DTR_VCEN TIM_M2_DTR_VCEN_MASK
//===Safety刹车控制使能
#define TIM_M2_DTR_SAFETYEN_POS 13
#define TIM_M2_DTR_SAFETYEN_MASK (0x01UL<<TIM_M2_DTR_SAFETYEN_POS)
#define TIM_M2_DTR_SAFETYEN TIM_M2_DTR_SAFETYEN_MASK
//===PWM输出控制使能
#define TIM_M2_DTR_MOEN_POS 12
#define TIM_M2_DTR_MOEN_MASK (0x01UL<<TIM_M2_DTR_MOEN_POS)
#define TIM_M2_DTR_MOEN TIM_M2_DTR_MOEN_MASK
//===PWM输出自动控制使能
#define TIM_M2_DTR_AOEN_POS 11
#define TIM_M2_DTR_AOEN_MASK (0x01UL<<TIM_M2_DTR_AOEN_POS)
#define TIM_M2_DTR_AOEN TIM_M2_DTR_AOEN_MASK
//===刹车控制使能
#define TIM_M2_DTR_BKE_POS 10
#define TIM_M2_DTR_BKE_MASK (0x01UL<<TIM_M2_DTR_BKE_POS)
#define TIM_M2_DTR_BKE TIM_M2_DTR_BKE_MASK
//===死区控制使能
#define TIM_M2_DTR_DTEN_POS 9
#define TIM_M2_DTR_DTEN_MASK (0x01UL<<TIM_M2_DTR_DTEN_POS)
#define TIM_M2_DTR_DTEN TIM_M2_DTR_DTEN_MASK
//===刹车选择
#define TIM_M2_DTR_BKSEL_POS 8
#define TIM_M2_DTR_BKSEL_MASK (0x01UL<<TIM_M2_DTR_BKSEL_POS)
#define TIM_M2_DTR_BKSEL TIM_M2_DTR_BKSEL_MASK
//===死区控制
#define TIM_M2_DTR_TIM_POS 0
#define TIM_M2_DTR_TIM_MASK (0xFFUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM TIM_M2_DTR_TIM_MASK
//===死区时间
#define TIM_M2_DTR_TIM_2 (0x00UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_3 (0x01UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_4 (0x02UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_5 (0x03UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_6 (0x04UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_7 (0x05UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_8 (0x06UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_9 (0x07UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_10 (0x08UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_11 (0x09UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_12 (0x0AUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_13 (0x0BUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_14 (0x0CUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_15 (0x0DUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_16 (0x0EUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_17 (0x0FUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_18 (0x10UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_19 (0x11UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_20 (0x12UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_21 (0x13UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_22 (0x14UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_23 (0x15UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_24 (0x16UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_25 (0x17UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_26 (0x18UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_27 (0x19UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_28 (0x1AUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_29 (0x1BUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_30 (0x1CUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_31 (0x1DUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_32 (0x1EUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_33 (0x1FUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_34 (0x20UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_35 (0x21UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_36 (0x22UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_37 (0x23UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_38 (0x24UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_39 (0x25UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_40 (0x26UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_41 (0x27UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_42 (0x28UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_43 (0x29UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_44 (0x2AUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_45 (0x2BUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_46 (0x2CUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_47 (0x2DUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_48 (0x2EUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_49 (0x2FUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_50 (0x30UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_51 (0x31UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_52 (0x32UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_53 (0x33UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_54 (0x34UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_55 (0x35UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_56 (0x36UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_57 (0x37UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_58 (0x38UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_59 (0x39UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_60 (0x3AUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_61 (0x3BUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_62 (0x3CUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_63 (0x3DUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_64 (0x3EUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_65 (0x3FUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_66 (0x40UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_67 (0x41UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_68 (0x42UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_69 (0x43UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_70 (0x44UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_71 (0x45UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_72 (0x46UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_73 (0x47UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_74 (0x48UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_75 (0x49UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_76 (0x4AUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_77 (0x4BUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_78 (0x4CUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_79 (0x4DUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_80 (0x4EUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_81 (0x4FUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_82 (0x50UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_83 (0x51UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_84 (0x52UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_85 (0x53UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_86 (0x54UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_87 (0x55UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_88 (0x56UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_89 (0x57UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_90 (0x58UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_91 (0x59UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_92 (0x5AUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_93 (0x5BUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_94 (0x5CUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_95 (0x5DUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_96 (0x5EUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_97 (0x5FUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_98 (0x60UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_99 (0x61UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_100 (0x62UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_101 (0x63UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_102 (0x64UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_103 (0x65UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_104 (0x66UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_105 (0x67UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_106 (0x68UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_107 (0x69UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_108 (0x6AUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_109 (0x6BUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_110 (0x6CUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_111 (0x6DUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_112 (0x6EUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_113 (0x6FUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_114 (0x70UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_115 (0x71UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_116 (0x72UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_117 (0x73UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_118 (0x74UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_119 (0x75UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_120 (0x76UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_121 (0x77UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_122 (0x78UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_123 (0x79UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_124 (0x7AUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_125 (0x7BUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_126 (0x7CUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_127 (0x7DUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_128 (0x7EUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_129 (0x7FUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_130 (0x80UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_132 (0x81UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_134 (0x82UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_136 (0x83UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_138 (0x84UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_140 (0x85UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_142 (0x86UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_144 (0x87UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_146 (0x88UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_148 (0x89UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_150 (0x8AUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_152 (0x8BUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_154 (0x8CUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_156 (0x8DUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_158 (0x8EUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_160 (0x8FUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_162 (0x90UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_164 (0x91UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_166 (0x92UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_168 (0x93UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_170 (0x94UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_172 (0x95UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_174 (0x96UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_176 (0x97UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_178 (0x98UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_180 (0x99UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_182 (0x9AUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_184 (0x9BUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_186 (0x9CUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_188 (0x9DUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_190 (0x9EUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_192 (0x9FUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_194 (0xA0UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_196 (0xA1UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_198 (0xA2UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_200 (0xA3UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_202 (0xA4UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_204 (0xA5UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_206 (0xA6UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_208 (0xA8UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_210 (0xA9UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_212 (0xAAUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_214 (0xABUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_216 (0xACUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_218 (0xADUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_220 (0xAEUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_222 (0xAFUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_224 (0xB0UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_226 (0xB1UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_228 (0xB2UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_230 (0xB3UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_232 (0xB4UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_234 (0xB5UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_236 (0xB6UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_238 (0xB7UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_240 (0xB8UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_242 (0xB9UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_246 (0xBAUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_248 (0xBBUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_250 (0xBCUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_252 (0xBDUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_254 (0xBEUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_256 (0xBFUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_258 (0xC0UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_266 (0xC1UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_274 (0xC2UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_282 (0xC3UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_290 (0xC4UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_296 (0xC5UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_302 (0xC6UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_308 (0xC7UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_314 (0xC8UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_322 (0xC9UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_330 (0xCAUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_338 (0xCBUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_346 (0xCCUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_354 (0xCDUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_362 (0xCEUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_370 (0xCFUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_378 (0xD0UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_386 (0xD1UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_394 (0xD2UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_402 (0xD3UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_410 (0xD4UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_418 (0xD5UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_426 (0xD6UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_434 (0xD7UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_442 (0xD8UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_450 (0xD9UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_458 (0xDAUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_466 (0xDBUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_474 (0xDCUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_482 (0xDDUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_490 (0xDEUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_498 (0xDFUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_514 (0xE0UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_530 (0xE1UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_546 (0xE2UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_547 (0xE3UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_562 (0xE4UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_578 (0xE5UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_594 (0xE6UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_610 (0xE7UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_642 (0xE8UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_658 (0xE9UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_674 (0xEAUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_690 (0xEBUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_706 (0xECUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_722 (0xEDUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_738 (0xEEUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_754 (0xEFUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_770 (0xF0UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_786 (0xF1UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_802 (0xF2UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_818 (0xF3UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_834 (0xF4UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_850 (0xF5UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_866 (0xF6UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_882 (0xF7UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_898 (0xF8UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_914 (0xF9UL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_930 (0xFAUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_946 (0xFBUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_962 (0xFCUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_978 (0xFDUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_994 (0xFEUL<<TIM_M2_DTR_TIM_POS)
#define TIM_M2_DTR_TIM_1010 (0xFFUL<<TIM_M2_DTR_TIM_POS)
//===重复周期设置值
#define TIM_M2_RCR_RCR_POS 0
#define TIM_M2_RCR_RCR_MASK (0xFFUL<<TIM_M2_RCR_RCR_POS)
#define TIM_M2_RCR_RCR TIM_M2_RCR_RCR_MASK
//===通道0比较捕获寄存器
#define TIM_M2_CCR_CCR0A_POS 0
#define TIM_M2_CCR_CCR0A_MASK (0xFFFFUL<<TIM_M2_CCR_CCR0A_POS)
#define TIM_M2_CCR_CCR0A TIM_M2_CCR_CCR0A_MASK
#define TIM_M2_CCR_CCR0B_POS 0
#define TIM_M2_CCR_CCR0B_MASK (0xFFFFUL<<TIM_M2_CCR_CCR0A_POS)
#define TIM_M2_CCR_CCR0B TIM_M2_CCR_CCR0B_MASK
//===通道1比较捕获寄存器
#define TIM_M2_CCR_CCR1A_POS 0
#define TIM_M2_CCR_CCR1A_MASK (0xFFFFUL<<TIM_M2_CCR_CCR1A_POS)
#define TIM_M2_CCR_CCR1A TIM_M2_CCR_CCR1A_MASK
#define TIM_M2_CCR_CCR1B_POS 0
#define TIM_M2_CCR_CCR1B_MASK (0xFFFFUL<<TIM_M2_CCR_CCR1B_POS)
#define TIM_M2_CCR_CCR1B TIM_M2_CCR_CCR1B_MASK
//===通道2比较捕获寄存器
#define TIM_M2_CCR_CCR2A_POS 0
#define TIM_M2_CCR_CCR2A_MASK (0xFFFFUL<<TIM_M2_CCR_CCR2A_POS)
#define TIM_M2_CCR_CCR2A TIM_M2_CCR_CCR2A_MASK
#define TIM_M2_CCR_CCR2B_POS 0
#define TIM_M2_CCR_CCR2B_MASK (0xFFFFUL<<TIM_M2_CCR_CCR2B_POS)
#define TIM_M2_CCR_CCR2B TIM_M2_CCR_CCR2B_MASK
#pragma endregion
#pragma region TIM_M3
//===普通定时器
typedef struct
{
__IO uint32_t ARR; //---重载寄存器 00
__IO uint32_t CNT; //---16位模式计数寄存器 04
uint32_t RESERVED1; //---保留字节 08
__IO uint32_t M23CR; //---控制寄存器 0C
__IO uint32_t SR; //---中断标志 10
__IO uint32_t CSR; //---中断标志清除 14
__IO uint32_t MSCR; //---主从模式控制 18
__IO uint32_t FLTR; //---滤波控制 1C
__IO uint32_t ADTR; //---ADC触发控制 20
__IO uint32_t CRCH0; //---比较单元0控制寄存器 24
__IO uint32_t CRCH1; //---比较单元1控制寄存器 28
__IO uint32_t CRCH2; //---比较单元2控制寄存器 2C
__IO uint32_t DTR; //---死区寄存器 30
__IO uint32_t RCR; //---重复计数寄存器 34
__IO uint32_t ARRDM; //---控制寄存器1 38
__IO uint32_t CCR0A; //---比较0A寄存器 3C
__IO uint32_t CCR0B; //---比较0B寄存器 40
__IO uint32_t CCR1A; //---比较1A寄存器 44
__IO uint32_t CCR1B; //---比较1B寄存器 48
__IO uint32_t CCR2A; //---比较2A寄存器 4C
__IO uint32_t CCR2B; //---比较2B寄存器 50
} TIM_M3_TypeDef;
#define TIM_M3_ARR_ARR_POS 0
#define TIM_M3_ARR_ARR_MASK (0xFFFFUL<<TIM_M3_ARR_ARR_POS)
#define TIM_M3_ARR_ARR TIM_M3_ARR_ARR_MASK
#define TIM_M3_CNT_CNT_POS 0
#define TIM_M3_CNT_CNT_MASK (0xFFFFUL<<TIM_M3_CNT_CNT_POS)
#define TIM_M3_CNT_CNT TIM_M3_CNT_CNT_MASK
//===控制寄存器
#define TIM_M3_M23CR_DIR_POS 27
#define TIM_M3_M23CR_DIR_MASK (0x01UL<<TIM_M3_M23CR_DIR_POS)
#define TIM_M3_M23CR_DIR TIM_M3_M23CR_DIR_MASK
#define TIM_M3_M23CR_DIR_UP (0x00UL<<TIM_M3_M23CR_DIR_POS)
#define TIM_M3_M23CR_DIR_DOWN (0x01UL<<TIM_M3_M23CR_DIR_POS)
//===软件刹车
#define TIM_M3_M23CR_BG_POS 26
#define TIM_M3_M23CR_BG_MASK (0x01UL<<TIM_M3_M23CR_BG_POS)
#define TIM_M3_M23CR_BG TIM_M3_M23CR_BG_MASK
#define TIM_M3_M23CR_BG_ENABLE (0x01UL<<TIM_M3_M23CR_BG_POS)
#define TIM_M3_M23CR_BG_DISABLE (0x00UL<<TIM_M3_M23CR_BG_POS)
//===软件更新
#define TIM_M3_M23CR_UG_POS 25
#define TIM_M3_M23CR_UG_MASK (0x01UL<<TIM_M3_M23CR_UG_POS)
#define TIM_M3_M23CR_UG TIM_M3_M23CR_UG_MASK
#define TIM_M3_M23CR_UG_ENABLE (0x01UL<<TIM_M3_M23CR_UG_POS)
#define TIM_M3_M23CR_UG_DISABLE (0x00UL<<TIM_M3_M23CR_UG_POS)
//===软件触发
#define TIM_M3_M23CR_TG_POS 24
#define TIM_M3_M23CR_TG_MASK (0x01UL<<TIM_M3_M23CR_TG_POS)
#define TIM_M3_M23CR_TG TIM_M3_M23CR_TG_MASK
#define TIM_M3_M23CR_TG_ENABLE (0x01UL<<TIM_M3_M23CR_TG_POS)
#define TIM_M3_M23CR_TG_DISABLE (0x00UL<<TIM_M3_M23CR_TG_POS)
//===OCREF清除使能
#define TIM_M3_M23CR_OCCE_POS 23
#define TIM_M3_M23CR_OCCE_MASK (0x01UL<<TIM_M3_M23CR_OCCE_POS)
#define TIM_M3_M23CR_OCCE TIM_M3_M23CR_OCCE_MASK
#define TIM_M3_M23CR_OCCE_ENABLE (0x01UL<<TIM_M3_M23CR_OCCE_POS)
#define TIM_M3_M23CR_OCCE_DISABLE (0x00UL<<TIM_M3_M23CR_OCCE_POS)
//===A比较模式中断
#define TIM_M3_M23CR_CISA_POS 21
#define TIM_M3_M23CR_CISA_MASK (0x03UL<<TIM_M3_M23CR_CISA_POS)
#define TIM_M3_M23CR_CISA TIM_M3_M23CR_CISA_MASK
#define TIM_M3_M23CR_CISA_EDGE_NONE (0x00UL<<TIM_M3_M23CR_CISA_POS)
#define TIM_M3_M23CR_CISA_EDGE_RISE (0x01UL<<TIM_M3_M23CR_CISA_POS)
#define TIM_M3_M23CR_CISA_EDGE_FAIL (0x02UL<<TIM_M3_M23CR_CISA_POS)
#define TIM_M3_M23CR_CISA_EDGE_ALL (0x03UL<<TIM_M3_M23CR_CISA_POS)
//===刹车中断使能
#define TIM_M3_M23CR_BIE_POS 20
#define TIM_M3_M23CR_BIE_MASK (0x01UL<<TIM_M3_M23CR_BIE_POS)
#define TIM_M3_M23CR_BIE TIM_M3_M23CR_BIE_MASK
//===触发中断使能
#define TIM_M3_M23CR_TIE_POS 19
#define TIM_M3_M23CR_TIE_MASK (0x01UL<<TIM_M3_M23CR_TIE_POS)
#define TIM_M3_M23CR_TIE TIM_M3_M23CR_TIE_MASK
//===触发DMA中断使能
#define TIM_M3_M23CR_TDMAIE_POS 18
#define TIM_M3_M23CR_TDMAIE_MASK (0x01UL<<TIM_M3_M23CR_TDMAIE_POS)
#define TIM_M3_M23CR_TDMAIE TIM_M3_M23CR_TDMAIE_MASK
//===更新源
#define TIM_M3_M23CR_URS_POS 17
#define TIM_M3_M23CR_URS_MASK (0x01UL<<TIM_M3_M23CR_URS_POS)
#define TIM_M3_M23CR_URS TIM_M3_M23CR_URS_MASK
#define TIM_M3_M23CR_URS_ALL (0x00UL<<TIM_M3_M23CR_URS_POS)
#define TIM_M3_M23CR_URS_RISE_OR_FAIL (0x00UL<<TIM_M3_M23CR_URS_POS)
//===OCREF清除源选择
#define TIM_M3_M23CR_OCCS_POS 16
#define TIM_M3_M23CR_OCCS_MASK (0x01UL<<TIM_M3_M23CR_OCCS_POS)
#define TIM_M3_M23CR_OCCS TIM_M3_M23CR_OCCS_MASK
#define TIM_M3_M23CR_OCCS_VC (0x00UL<<TIM_M3_M23CR_OCCS_POS)
#define TIM_M3_M23CR_OCCS_ETR (0x01UL<<TIM_M3_M23CR_OCCS_POS)
//===PWM互补模式选择
#define TIM_M3_M23CR_CSG_POS 15
#define TIM_M3_M23CR_CSG_MASK (0x01UL<<TIM_M3_M23CR_CSG_POS)
#define TIM_M3_M23CR_CSG TIM_M3_M23CR_CSG_MASK
#define TIM_M3_M23CR_CSG_COMP (0x00UL<<TIM_M3_M23CR_CSG_POS)
#define TIM_M3_M23CR_CSG_CAPT (0x01UL<<TIM_M3_M23CR_CSG_POS)
//===触发选择
#define TIM_M3_M23CR_TRIG_POS 14
#define TIM_M3_M23CR_TRIG_MASK (0x01UL<<TIM_M3_M23CR_TRIG_POS)
#define TIM_M3_M23CR_TRIG TIM_M3_M23CR_TRIG_MASK
#define TIM_M3_M23CR_TRIG_CYCLE (0x00UL<<TIM_M3_M23CR_TRIG_POS)
#define TIM_M3_M23CR_TRIG_SINGLE (0x01UL<<TIM_M3_M23CR_TRIG_POS)
//===工作模式
#define TIM_M3_M23CR_MODE_POS 12
#define TIM_M3_M23CR_MODE_MASK (0x03UL<<TIM_M3_M23CR_MODE_POS)
#define TIM_M3_M23CR_MODE TIM_M3_M23CR_MODE_MASK
#define TIM_M3_M23CR_MODE_TIM0 (0x00UL<<TIM_M3_M23CR_MODE_POS)
#define TIM_M3_M23CR_MODE_PWC (0x01UL<<TIM_M3_M23CR_MODE_POS)
#define TIM_M3_M23CR_MODE_SAWTOOTH (0x02UL<<TIM_M3_M23CR_MODE_POS)
#define TIM_M3_M23CR_MODE_TRIANGLE (0x03UL<<TIM_M3_M23CR_MODE_POS)
//===更新DMA使能
#define TIM_M3_M23CR_UDMAEN_POS 11
#define TIM_M3_M23CR_UDMAEN_MASK (0x01UL<<TIM_M3_M23CR_UDMAEN_POS)
#define TIM_M3_M23CR_UDMAEN TIM_M3_M23CR_UDMAEN_MASK
//===更新中断使能
#define TIM_M3_M23CR_UIE_POS 10
#define TIM_M3_M23CR_UIE_MASK (0x01UL<<TIM_M3_M23CR_UIE_POS)
#define TIM_M3_M23CR_UIE TIM_M3_M23CR_UIE_MASK
//===下降沿捕获使能控制
#define TIM_M3_M23CR_CFG_POS 9
#define TIM_M3_M23CR_CFG_MASK (0x01UL<<TIM_M3_M23CR_CFG_POS)
#define TIM_M3_M23CR_CFG TIM_M3_M23CR_CFG_MASK
#define TIM_M3_M23CR_CFG_ENABLE (0x01UL<<TIM_M3_M23CR_CFG_POS)
#define TIM_M3_M23CR_CFG_DISABLE (0x00UL<<TIM_M3_M23CR_CFG_POS)
//===上升沿捕获使能控制
#define TIM_M3_M23CR_CRG_POS 8
#define TIM_M3_M23CR_CRG_MASK (0x01UL<<TIM_M3_M23CR_CRG_POS)
#define TIM_M3_M23CR_CRG TIM_M3_M23CR_CRG_MASK
#define TIM_M3_M23CR_CRG_ENABLE (0x01UL<<TIM_M3_M23CR_CRG_POS)
#define TIM_M3_M23CR_CRG_DISABLE (0x00UL<<TIM_M3_M23CR_CRG_POS)
//===重载缓存使能控制
#define TIM_M3_M23CR_BUFPEN_POS 7
#define TIM_M3_M23CR_BUFPEN_MASK (0x01UL<<TIM_M3_M23CR_BUFPEN_POS)
#define TIM_M3_M23CR_BUFPEN TIM_M3_M23CR_BUFPEN_MASK
//===时钟分频选择
#define TIM_M3_M23CR_PRS_POS 4
#define TIM_M3_M23CR_PRS_MASK (0x07UL<<TIM_M3_M23CR_PRS_POS)
#define TIM_M3_M23CR_PRS TIM_M3_M23CR_PRS_MASK
#define TIM_M3_M23CR_PRS_1 (0x00UL<<TIM_M3_M23CR_PRS_POS)
#define TIM_M3_M23CR_PRS_2 (0x01UL<<TIM_M3_M23CR_PRS_POS)
#define TIM_M3_M23CR_PRS_4 (0x02UL<<TIM_M3_M23CR_PRS_POS)
#define TIM_M3_M23CR_PRS_8 (0x03UL<<TIM_M3_M23CR_PRS_POS)
#define TIM_M3_M23CR_PRS_16 (0x04UL<<TIM_M3_M23CR_PRS_POS)
#define TIM_M3_M23CR_PRS_32 (0x05UL<<TIM_M3_M23CR_PRS_POS)
#define TIM_M3_M23CR_PRS_64 (0x06UL<<TIM_M3_M23CR_PRS_POS)
#define TIM_M3_M23CR_PRS_256 (0x07UL<<TIM_M3_M23CR_PRS_POS)
//===单双点比较控制
#define TIM_M3_M23CR_PWM2S_POS 3
#define TIM_M3_M23CR_PWM2S_MASK (0x01UL<<TIM_M3_M23CR_PWM2S_POS)
#define TIM_M3_M23CR_PWM2S TIM_M3_M23CR_PWM2S_MASK
#define TIM_M3_M23CR_PWM2S_DOUBLE (0x00UL<<TIM_M3_M23CR_PWM2S_POS)
#define TIM_M3_M23CR_PWM2S_SINGLE (0x01UL<<TIM_M3_M23CR_PWM2S_POS)
//===计数时钟
#define TIM_M3_M23CR_CT_POS 2
#define TIM_M3_M23CR_CT_MASK (0x01UL<<TIM_M3_M23CR_CT_POS)
#define TIM_M3_M23CR_CT TIM_M3_M23CR_CT_MASK
#define TIM_M3_M23CR_CT_TCLK (0x00UL<<TIM_M3_M23CR_CT_POS)
#define TIM_M3_M23CR_CT_ETR (0x01UL<<TIM_M3_M23CR_CT_POS)
//===PWM模式选择
#define TIM_M3_M23CR_COMP_POS 1
#define TIM_M3_M23CR_COMP_MASK (0x01UL<<TIM_M3_M23CR_COMP_POS)
#define TIM_M3_M23CR_COMP TIM_M3_M23CR_COMP_MASK
#define TIM_M3_M23CR_COMP_PWM_COMP (0x01UL<<TIM_M3_M23CR_COMP_POS)
#define TIM_M3_M23CR_COMP_PWM_INDEP (0x00UL<<TIM_M3_M23CR_COMP_POS)
//===定时器使能控制
#define TIM_M3_M23CR_EN_POS 0
#define TIM_M3_M23CR_EN_MASK (0x01U<<TIM_M3_M23CR_EN_POS)
#define TIM_M3_M23CR_EN TIM_M3_M23CR_EN_MASK
//===中断标志寄存器
//===触发中断标志
#define TIM_M3_SR_TIE_POS 15
#define TIM_M3_SR_TIE_MASK (0x01U<<TIM_M3_SR_TIE_POS)
#define TIM_M3_SR_TIE TIM_M3_SR_TIE_MASK
//===刹车中断标志
#define TIM_M3_SR_BIE_POS 14
#define TIM_M3_SR_BIE_MASK (0x01U<<TIM_M3_SR_BIE_POS)
#define TIM_M3_SR_BIE TIM_M3_SR_BIE_MASK
//==CH2B捕获丢数据
#define TIM_M3_SR_CH2B_ERROR_POS 13
#define TIM_M3_SR_CH2B_ERROR_MASK (0x01U<<TIM_M3_SR_CH2B_ERROR_POS)
#define TIM_M3_SR_CH2B_ERROR TIM_M3_SR_CH2B_ERROR_MASK
//==CH1B捕获丢数据
#define TIM_M3_SR_CH1B_ERROR_POS 12
#define TIM_M3_SR_CH1B_ERROR_MASK (0x01U<<TIM_M3_SR_CH1B_ERROR_POS)
#define TIM_M3_SR_CH1B_ERROR TIM_M3_SR_CH1B_ERROR_MASK
//==CH0B捕获丢数据
#define TIM_M3_SR_CH0B_ERROR_POS 11
#define TIM_M3_SR_CH0B_ERROR_MASK (0x01U<<TIM_M3_SR_CH0B_ERROR_POS)
#define TIM_M3_SR_CH0B_ERROR TIM_M3_SR_CH0B_ERROR_MASK
//==CH2A捕获丢数据
#define TIM_M3_SR_CH2A_ERROR_POS 10
#define TIM_M3_SR_CH2A_ERROR_MASK (0x01U<<TIM_M3_SR_CH2A_ERROR_POS)
#define TIM_M3_SR_CH2A_ERROR TIM_M3_SR_CH2A_ERROR_MASK
//==CH1A捕获丢数据
#define TIM_M3_SR_CH1A_ERROR_POS 9
#define TIM_M3_SR_CH1A_ERROR_MASK (0x01U<<TIM_M3_SR_CH1A_ERROR_POS)
#define TIM_M3_SR_CH1A_ERROR TIM_M3_SR_CH1A_ERROR_MASK
//==CH0A捕获丢数据
#define TIM_M3_SR_CH0A_ERROR_POS 8
#define TIM_M3_SR_CH0A_ERROR_MASK (0x01U<<TIM_M3_SR_CH0A_ERROR_POS)
#define TIM_M3_SR_CH0A_ERROR TIM_M3_SR_CH0A_ERROR_MASK
//==CH2B捕获/比较中断标志
#define TIM_M3_SR_CH2B_FLAG_POS 7
#define TIM_M3_SR_CH2B_FLAG_MASK (0x01U<<TIM_M3_SR_CH2B_FLAG_POS)
#define TIM_M3_SR_CH2B_FLAG TIM_M3_SR_CH2B_FLAG_MASK
//==CH1B捕获/比较中断标志
#define TIM_M3_SR_CH1B_FLAG_POS 6
#define TIM_M3_SR_CH1B_FLAG_MASK (0x01U<<TIM_M3_SR_CH1B_FLAG_POS)
#define TIM_M3_SR_CH1B_FLAG TIM_M3_SR_CH1B_FLAG_MASK
//==CH0B捕获/比较中断标志
#define TIM_M3_SR_CH0B_FLAG_POS 5
#define TIM_M3_SR_CH0B_FLAG_MASK (0x01U<<TIM_M3_SR_CH0B_FLAG_POS)
#define TIM_M3_SR_CH0B_FLAG TIM_M3_SR_CH0B_FLAG_MASK
//==CH2A捕获/比较中断标志
#define TIM_M3_SR_CH2A_FLAG_POS 4
#define TIM_M3_SR_CH2A_FLAG_MASK (0x01U<<TIM_M3_SR_CH2A_FLAG_POS)
#define TIM_M3_SR_CH2A_FLAG TIM_M3_SR_CH2A_FLAG_MASK
//==CH1A捕获/比较中断标志
#define TIM_M3_SR_CH1A_FLAG_POS 3
#define TIM_M3_SR_CH1A_FLAG_MASK (0x01U<<TIM_M3_SR_CH1A_FLAG_POS)
#define TIM_M3_SR_CH1A_FLAG TIM_M3_SR_CH1A_FLAG_MASK
//==CH0A捕获/比较中断标志
#define TIM_M3_SR_CH0A_FLAG_POS 2
#define TIM_M3_SR_CH0A_FLAG_MASK (0x01U<<TIM_M3_SR_CH0A_FLAG_POS)
#define TIM_M3_SR_CH0A_FLAG TIM_M3_SR_CH0A_FLAG_MASK
//===更新中断标志位
#define TIM_M3_SR_UIE_POS 0
#define TIM_M3_SR_UIE_MASK (0x01U<<TIM_M3_SR_UIE_POS)
#define TIM_M3_SR_UIE TIM_M3_SR_UIE_MASK
//===清楚标志寄存器
#define TIM_M3_CSR_MASK 0xFFFDUL
#define TIM_M3_CSR_TIE_POS 15
#define TIM_M3_CSR_TIE_MASK (0x01U<<TIM_M3_CSR_TIE_POS)
#define TIM_M3_CSR_TIE TIM_M3_CSR_TIE_MASK
#define TIM_M3_CSR_BIE_POS 14
#define TIM_M3_CSR_BIE_MASK (0x01U<<TIM_M3_CSR_BIE_POS)
#define TIM_M3_CSR_BIE TIM_M3_CSR_BIE_MASK
#define TIM_M3_CSR_CH2B_ERROR_POS 13
#define TIM_M3_CSR_CH2B_ERROR_MASK (0x01U<<TIM_M3_CSR_CH2B_ERROR_POS)
#define TIM_M3_CSR_CH2B_ERROR TIM_M3_CSR_CH2B_ERROR_MASK
#define TIM_M3_CSR_CH1B_ERROR_POS 12
#define TIM_M3_CSR_CH1B_ERROR_MASK (0x01U<<TIM_M3_CSR_CH1B_ERROR_POS)
#define TIM_M3_CSR_CH1B_ERROR TIM_M3_CSR_CH1B_ERROR_MASK
#define TIM_M3_CSR_CH0B_ERROR_POS 11
#define TIM_M3_CSR_CH0B_ERROR_MASK (0x01U<<TIM_M3_CSR_CH0B_ERROR_POS)
#define TIM_M3_CSR_CH0B_ERROR TIM_M3_CSR_CH0B_ERROR_MASK
#define TIM_M3_CSR_CH2A_ERROR_POS 10
#define TIM_M3_CSR_CH2A_ERROR_MASK (0x01U<<TIM_M3_CSR_CH2A_ERROR_POS)
#define TIM_M3_CSR_CH2A_ERROR TIM_M3_CSR_CH2A_ERROR_MASK
#define TIM_M3_CSR_CH1A_ERROR_POS 9
#define TIM_M3_CSR_CH1A_ERROR_MASK (0x01U<<TIM_M3_CSR_CH1A_ERROR_POS)
#define TIM_M3_CSR_CH1A_ERROR TIM_M3_CSR_CH1A_ERROR_MASK
#define TIM_M3_CSR_CH0A_ERROR_POS 8
#define TIM_M3_CSR_CH0A_ERROR_MASK (0x01U<<TIM_M3_CSR_CH0A_ERROR_POS)
#define TIM_M3_CSR_CH0A_ERROR TIM_M3_CSR_CH0A_ERROR_MASK
#define TIM_M3_CSR_CH2B_FLAG_POS 7
#define TIM_M3_CSR_CH2B_FLAG_MASK (0x01U<<TIM_M3_CSR_CH2B_FLAG_POS)
#define TIM_M3_CSR_CH2B_FLAG TIM_M3_CSR_CH2B_FLAG_MASK
#define TIM_M3_CSR_CH1B_FLAG_POS 6
#define TIM_M3_CSR_CH1B_FLAG_MASK (0x01U<<TIM_M3_CSR_CH1B_FLAG_POS)
#define TIM_M3_CSR_CH1B_FLAG TIM_M3_CSR_CH1B_FLAG_MASK
#define TIM_M3_CSR_CH0B_FLAG_POS 5
#define TIM_M3_CSR_CH0B_FLAG_MASK (0x01U<<TIM_M3_CSR_CH0B_FLAG_POS)
#define TIM_M3_CSR_CH0B_FLAG TIM_M3_CSR_CH0B_FLAG_MASK
#define TIM_M3_CSR_CH2A_FLAG_POS 4
#define TIM_M3_CSR_CH2A_FLAG_MASK (0x01U<<TIM_M3_CSR_CH2A_FLAG_POS)
#define TIM_M3_CSR_CH2A_FLAG TIM_M3_CSR_CH2A_FLAG_MASK
#define TIM_M3_CSR_CH1A_FLAG_POS 3
#define TIM_M3_CSR_CH1A_FLAG_MASK (0x01U<<TIM_M3_CSR_CH1A_FLAG_POS)
#define TIM_M3_CSR_CH1A_FLAG TIM_M3_CSR_CH1A_FLAG_MASK
#define TIM_M3_CSR_CH0A_FLAG_POS 2
#define TIM_M3_CSR_CH0A_FLAG_MASK (0x01U<<TIM_M3_CSR_CH0A_FLAG_POS)
#define TIM_M3_CSR_CH0A_FLAG TIM_M3_CSR_CH0A_FLAG_MASK
#define TIM_M3_CSR_UIE_POS 0
#define TIM_M3_CSR_UIE_MASK (0x01U<<TIM_M3_CSR_UIE_POS)
#define TIM_M3_CSR_UIE TIM_M3_CSR_UIE_MASK
//===主从模式控制寄存器
//===CH0B输入选择
#define TIM_M3_MSCR_IB0S_POS 12
#define TIM_M3_MSCR_IB0S_MASK (0x01U<<TIM_M3_MSCR_IB0S_POS)
#define TIM_M3_MSCR_IB0S TIM_M3_MSCR_IB0S_MASK
//===CH0A输入选择
#define TIM_M3_MSCR_IA0S_POS 11
#define TIM_M3_MSCR_IA0S_MASK (0x01U<<TIM_M3_MSCR_IA0S_POS)
#define TIM_M3_MSCR_IA0S TIM_M3_MSCR_IA0S_MASK
//===从模式选择
#define TIM_M3_MSCR_SMS_POS 8
#define TIM_M3_MSCR_SMS_MASK (0x07U<<TIM_M3_MSCR_SMS_POS)
#define TIM_M3_MSCR_SMS TIM_M3_MSCR_SMS_MASK
#define TIM_M3_MSCR_SMS_TCLK (0x00U<<TIM_M3_MSCR_SMS_POS)
#define TIM_M3_MSCR_SMS_RESET (0x01U<<TIM_M3_MSCR_SMS_POS)
#define TIM_M3_MSCR_SMS_TRIG (0x02U<<TIM_M3_MSCR_SMS_POS)
#define TIM_M3_MSCR_SMS_ETR (0x03U<<TIM_M3_MSCR_SMS_POS)
#define TIM_M3_MSCR_SMS_ENCODE_MODE1 (0x04U<<TIM_M3_MSCR_SMS_POS)
#define TIM_M3_MSCR_SMS_ENCODE_MODE2 (0x05U<<TIM_M3_MSCR_SMS_POS)
#define TIM_M3_MSCR_SMS_ENCODE_MODE3 (0x06U<<TIM_M3_MSCR_SMS_POS)
#define TIM_M3_MSCR_SMS_GATE (0x07U<<TIM_M3_MSCR_SMS_POS)
//===触发模式选择
#define TIM_M3_MSCR_TRIG_POS 5
#define TIM_M3_MSCR_TRIG_MASK (0x07U<<TIM_M3_MSCR_TRIG_POS)
#define TIM_M3_MSCR_TRIG TIM_M3_MSCR_TRIG_MASK
#define TIM_M3_MSCR_TRIG_ETRP (0x00U<<TIM_M3_MSCR_TRIG_POS)
#define TIM_M3_MSCR_TRIG_ITR0 (0x01U<<TIM_M3_MSCR_TRIG_POS)
#define TIM_M3_MSCR_TRIG_ITR1 (0x02U<<TIM_M3_MSCR_TRIG_POS)
#define TIM_M3_MSCR_TRIG_ITR2 (0x03U<<TIM_M3_MSCR_TRIG_POS)
#define TIM_M3_MSCR_TRIG_ITR3 (0x04U<<TIM_M3_MSCR_TRIG_POS)
#define TIM_M3_MSCR_TRIG_CH0A (0x05U<<TIM_M3_MSCR_TRIG_POS)
#define TIM_M3_MSCR_TRIG_CH0AP (0x06U<<TIM_M3_MSCR_TRIG_POS)
#define TIM_M3_MSCR_TRIG_CH0BP (0x07U<<TIM_M3_MSCR_TRIG_POS)
//===主从模式选择
#define TIM_M3_MSCR_MSM_POS 4
#define TIM_M3_MSCR_MSM_MASK (0x07U<<TIM_M3_MSCR_MSM_POS)
#define TIM_M3_MSCR_MSM TIM_M3_MSCR_MSM_MASK
//===比较模式下DMA比较触发选择
#define TIM_M3_MSCR_CCDS_POS 3
#define TIM_M3_MSCR_CCDS_MASK (0x07U<<TIM_M3_MSCR_CCDS_POS)
#define TIM_M3_MSCR_CCDS TIM_M3_MSCR_CCDS_MASK
//===主模式输出选择
#define TIM_M3_MSCR_MMS_POS 0
#define TIM_M3_MSCR_MMS_MASK (0x07UL<<TIM_M3_MSCR_MMS_POS)
#define TIM_M3_MSCR_MMS TIM_M3_MSCR_MMS_MASK
#define TIM_M3_MSCR_MMS_UG (0x00U<<TIM_M3_MSCR_MMS_POS)
#define TIM_M3_MSCR_MMS_EN (0x01U<<TIM_M3_MSCR_MMS_POS)
#define TIM_M3_MSCR_MMS_UEV (0x02U<<TIM_M3_MSCR_MMS_POS)
#define TIM_M3_MSCR_MMS_CMPSO (0x03U<<TIM_M3_MSCR_MMS_POS)
#define TIM_M3_MSCR_MMS_OCREF0A (0x04U<<TIM_M3_MSCR_MMS_POS)
#define TIM_M3_MSCR_MMS_OCREF1A (0x05U<<TIM_M3_MSCR_MMS_POS)
#define TIM_M3_MSCR_MMS_OCREF2A (0x06U<<TIM_M3_MSCR_MMS_POS)
#define TIM_M3_MSCR_MMS_OCREF0B (0x07U<<TIM_M3_MSCR_MMS_POS)
//===滤波控制寄存器
//===ETR输入相位
#define TIM_M3_FLTR_ETP_POS 31
#define TIM_M3_FLTR_ETP_MASK (0x01UL<<TIM_M3_FLTR_ETP_POS)
#define TIM_M3_FLTR_ETP TIM_M3_FLTR_ETP_MASK
//===ETR滤波控制
#define TIM_M3_FLTR_ETR_POS 28
#define TIM_M3_FLTR_ETR_MASK (0x07UL<<TIM_M3_FLTR_ETR_POS)
#define TIM_M3_FLTR_ETR TIM_M3_FLTR_ETR_MASK
#define TIM_M3_FLTR_ETR_NONE (0x00U<<TIM_M3_FLTR_ETR_POS)
#define TIM_M3_FLTR_ETR_PCLK_DIV1 (0x04U<<TIM_M3_FLTR_ETR_POS)
#define TIM_M3_FLTR_ETR_PCLK_DIV4 (0x05U<<TIM_M3_FLTR_ETR_POS)
#define TIM_M3_FLTR_ETR_PCLK_DIV16 (0x06U<<TIM_M3_FLTR_ETR_POS)
#define TIM_M3_FLTR_ETR_PCLK_DIV64 (0x07U<<TIM_M3_FLTR_ETR_POS)
//===刹车BK输入相位选择
#define TIM_M3_FLTR_BKP_POS 27
#define TIM_M3_FLTR_BKP_MASK (0x01U<<TIM_M3_FLTR_BKP_POS)
#define TIM_M3_FLTR_BKP TIM_M3_FLTR_BKP_MASK
//===刹车输入滤波控制
#define TIM_M3_FLTR_BKR_POS 24
#define TIM_M3_FLTR_BKR_MASK (0x07UL<<TIM_M3_FLTR_BKR_POS)
#define TIM_M3_FLTR_BKR TIM_M3_FLTR_BKR_MASK
#define TIM_M3_FLTR_BKR_NONE (0x00UL<<TIM_M3_FLTR_BKR_POS)
#define TIM_M3_FLTR_BKR_PCLK_DIV1 (0x04UL<<TIM_M3_FLTR_BKR_POS)
#define TIM_M3_FLTR_BKR_PCLK_DIV4 (0x05UL<<TIM_M3_FLTR_BKR_POS)
#define TIM_M3_FLTR_BKR_PCLK_DIV16 (0x06UL<<TIM_M3_FLTR_BKR_POS)
#define TIM_M3_FLTR_BKR_PCLK_DIV64 (0x07UL<<TIM_M3_FLTR_BKR_POS)
//===CH2B比较输出相位控制
#define TIM_M3_FLTR_CCPB2_POS 23
#define TIM_M3_FLTR_CCPB2_MASK (0x01UL<<TIM_M3_FLTR_CCPB2_POS)
#define TIM_M3_FLTR_CCPB2 TIM_M3_FLTR_CCPB2_MASK
//==CH2B比较输出控制
#define TIM_M3_FLTR_OCMB2_POS 20
#define TIM_M3_FLTR_OCMB2_MASK (0x07UL<<TIM_M3_FLTR_OCMB2_POS)
#define TIM_M3_FLTR_OCMB2 TIM_M3_FLTR_OCMB2_MASK
#define TIM_M3_FLTR_OCMB2_FORCE_LOW (0x00UL<<TIM_M3_FLTR_OCMB2_POS)
#define TIM_M3_FLTR_OCMB2_FORCE_HIGH (0x01UL<<TIM_M3_FLTR_OCMB2_POS)
#define TIM_M3_FLTR_OCMB2_COMP_LOW (0x02UL<<TIM_M3_FLTR_OCMB2_POS)
#define TIM_M3_FLTR_OCMB2_COMP_HIGH (0x03UL<<TIM_M3_FLTR_OCMB2_POS)
#define TIM_M3_FLTR_OCMB2_COMP_TOGGLE (0x04UL<<TIM_M3_FLTR_OCMB2_POS)
#define TIM_M3_FLTR_OCMB2_COMP_KEEP_HIGH (0x05UL<<TIM_M3_FLTR_OCMB2_POS)
#define TIM_M3_FLTR_OCMB2_PWM_MODE1 (0x06UL<<TIM_M3_FLTR_OCMB2_POS)
#define TIM_M3_FLTR_OCMB2_PWM_MODE2 (0x07UL<<TIM_M3_FLTR_OCMB2_POS)
//==CH2B捕获输入滤波控制
#define TIM_M3_FLTR_CH2B_POS 20
#define TIM_M3_FLTR_CH2B_MASK (0x07UL<<TIM_M3_FLTR_CH2B_POS)
#define TIM_M3_FLTR_CH2B TIM_M3_FLTR_CH2B_MASK
#define TIM_M3_FLTR_CH2B_NONE (0x00U<<TIM_M3_FLTR_CH2B_POS)
#define TIM_M3_FLTR_CH2B_PCLK_DIV1 (0x04U<<TIM_M3_FLTR_CH2B_POS)
#define TIM_M3_FLTR_CH2B_PCLK_DIV4 (0x05U<<TIM_M3_FLTR_CH2B_POS)
#define TIM_M3_FLTR_CH2B_PCLK_DIV16 (0x06U<<TIM_M3_FLTR_CH2B_POS)
#define TIM_M3_FLTR_CH2B_PCLK_DIV64 (0x07U<<TIM_M3_FLTR_CH2B_POS)
//===CH2A比较输出相位控制
#define TIM_M3_FLTR_CCPA2_POS 19
#define TIM_M3_FLTR_CCPA2_MASK (0x01UL<<TIM_M3_FLTR_CCPA2_POS)
#define TIM_M3_FLTR_CCPA2 TIM_M3_FLTR_CCPA2_MASK
//==CH2A比较输出控制
#define TIM_M3_FLTR_OCMA2_POS 16
#define TIM_M3_FLTR_OCMA2_MASK (0x07UL<<TIM_M3_FLTR_OCMA2_POS)
#define TIM_M3_FLTR_OCMA2 TIM_M3_FLTR_OCMA2_MASK
#define TIM_M3_FLTR_OCMA2_FORCE_LOW (0x00UL<<TIM_M3_FLTR_OCMA2_POS)
#define TIM_M3_FLTR_OCMA2_FORCE_HIGH (0x01UL<<TIM_M3_FLTR_OCMA2_POS)
#define TIM_M3_FLTR_OCMA2_COMP_LOW (0x02UL<<TIM_M3_FLTR_OCMA2_POS)
#define TIM_M3_FLTR_OCMA2_COMP_HIGH (0x03UL<<TIM_M3_FLTR_OCMA2_POS)
#define TIM_M3_FLTR_OCMA2_COMP_TOGGLE (0x04UL<<TIM_M3_FLTR_OCMA2_POS)
#define TIM_M3_FLTR_OCMA2_COMP_KEEP_HIGH (0x05UL<<TIM_M3_FLTR_OCMA2_POS)
#define TIM_M3_FLTR_OCMA2_PWM_MODE1 (0x06UL<<TIM_M3_FLTR_OCMA2_POS)
#define TIM_M3_FLTR_OCMA2_PWM_MODE2 (0x07UL<<TIM_M3_FLTR_OCMA2_POS)
//==CH2A捕获输入滤波控制
#define TIM_M3_FLTR_CH2A_POS 16
#define TIM_M3_FLTR_CH2A_MASK (0x07UL<<TIM_M3_FLTR_CH2A_POS)
#define TIM_M3_FLTR_CH2A TIM_M3_FLTR_CH2A_MASK
#define TIM_M3_FLTR_CH2A_NONE (0x00UL<<TIM_M3_FLTR_CH2A_POS)
#define TIM_M3_FLTR_CH2A_PCLK_DIV1 (0x04UL<<TIM_M3_FLTR_CH2A_POS)
#define TIM_M3_FLTR_CH2A_PCLK_DIV4 (0x05UL<<TIM_M3_FLTR_CH2A_POS)
#define TIM_M3_FLTR_CH2A_PCLK_DIV16 (0x06UL<<TIM_M3_FLTR_CH2A_POS)
#define TIM_M3_FLTR_CH2A_PCLK_DIV64 (0x07UL<<TIM_M3_FLTR_CH2A_POS)
//===CH1B比较输出相位控制
#define TIM_M3_FLTR_CCPB1_POS 15
#define TIM_M3_FLTR_CCPB1_MASK (0x01UL<<TIM_M3_FLTR_CCPB1_POS)
#define TIM_M3_FLTR_CCPB1 TIM_M3_FLTR_CCPB1_MASK
//==CH1B比较输出控制
#define TIM_M3_FLTR_OCMB1_POS 12
#define TIM_M3_FLTR_OCMB1_MASK (0x07UL<<TIM_M3_FLTR_OCMB1_POS)
#define TIM_M3_FLTR_OCMB1 TIM_M3_FLTR_OCMB1_MASK
#define TIM_M3_FLTR_OCMB1_FORCE_LOW (0x00UL<<TIM_M3_FLTR_OCMB1_POS)
#define TIM_M3_FLTR_OCMB1_FORCE_HIGH (0x01UL<<TIM_M3_FLTR_OCMB1_POS)
#define TIM_M3_FLTR_OCMB1_COMP_LOW (0x02UL<<TIM_M3_FLTR_OCMB1_POS)
#define TIM_M3_FLTR_OCMB1_COMP_HIGH (0x03UL<<TIM_M3_FLTR_OCMB1_POS)
#define TIM_M3_FLTR_OCMB1_COMP_TOGGLE (0x04UL<<TIM_M3_FLTR_OCMB1_POS)
#define TIM_M3_FLTR_OCMB1_COMP_KEEP_HIGH (0x05UL<<TIM_M3_FLTR_OCMB1_POS)
#define TIM_M3_FLTR_OCMB1_PWM_MODE1 (0x06UL<<TIM_M3_FLTR_OCMB1_POS)
#define TIM_M3_FLTR_OCMB1_PWM_MODE2 (0x07UL<<TIM_M3_FLTR_OCMB1_POS)
//==CH1B捕获输入滤波控制
#define TIM_M3_FLTR_CH1B_POS 12
#define TIM_M3_FLTR_CH1B_MASK (0x07UL<<TIM_M3_FLTR_CH1B_POS)
#define TIM_M3_FLTR_CH1B TIM_M3_FLTR_CH1B_MASK
#define TIM_M3_FLTR_CH1B_NONE (0x00UL<<TIM_M3_FLTR_CH1B_POS)
#define TIM_M3_FLTR_CH1B_PCLK_DIV1 (0x04UL<<TIM_M3_FLTR_CH1B_POS)
#define TIM_M3_FLTR_CH1B_PCLK_DIV4 (0x05UL<<TIM_M3_FLTR_CH1B_POS)
#define TIM_M3_FLTR_CH1B_PCLK_DIV16 (0x06UL<<TIM_M3_FLTR_CH1B_POS)
#define TIM_M3_FLTR_CH1B_PCLK_DIV64 (0x07UL<<TIM_M3_FLTR_CH1B_POS)
//===CH1A比较输出相位控制
#define TIM_M3_FLTR_CCPA1_POS 11
#define TIM_M3_FLTR_CCPA1_MASK (0x01UL<<TIM_M3_FLTR_CCPA1_POS)
#define TIM_M3_FLTR_CCPA1 TIM_M3_FLTR_CCPA1_MASK
//==CH1A比较输出控制
#define TIM_M3_FLTR_OCMA1_POS 8
#define TIM_M3_FLTR_OCMA1_MASK (0x07UL<<TIM_M3_FLTR_OCMA1_POS)
#define TIM_M3_FLTR_OCMA1 TIM_M3_FLTR_OCMA1_MASK
#define TIM_M3_FLTR_OCMA1_FORCE_LOW (0x00UL<<TIM_M3_FLTR_OCMA1_POS)
#define TIM_M3_FLTR_OCMA1_FORCE_HIGH (0x01UL<<TIM_M3_FLTR_OCMA1_POS)
#define TIM_M3_FLTR_OCMA1_COMP_LOW (0x02UL<<TIM_M3_FLTR_OCMA1_POS)
#define TIM_M3_FLTR_OCMA1_COMP_HIGH (0x03UL<<TIM_M3_FLTR_OCMA1_POS)
#define TIM_M3_FLTR_OCMA1_COMP_TOGGLE (0x04UL<<TIM_M3_FLTR_OCMA1_POS)
#define TIM_M3_FLTR_OCMA1_COMP_KEEP_HIGH (0x05UL<<TIM_M3_FLTR_OCMA1_POS)
#define TIM_M3_FLTR_OCMA1_PWM_MODE1 (0x06UL<<TIM_M3_FLTR_OCMA1_POS)
#define TIM_M3_FLTR_OCMA1_PWM_MODE2 (0x07UL<<TIM_M3_FLTR_OCMA1_POS)
//==CH1A捕获输入滤波控制
#define TIM_M3_FLTR_CH1A_POS 8
#define TIM_M3_FLTR_CH1A_MASK (0x07UL<<TIM_M3_FLTR_CH1A_POS)
#define TIM_M3_FLTR_CH1A TIM_M3_FLTR_CH1A_MASK
#define TIM_M3_FLTR_CH1A_NONE (0x00UL<<TIM_M3_FLTR_CH1A_POS)
#define TIM_M3_FLTR_CH1A_PCLK_DIV1 (0x04UL<<TIM_M3_FLTR_CH1A_POS)
#define TIM_M3_FLTR_CH1A_PCLK_DIV4 (0x05UL<<TIM_M3_FLTR_CH1A_POS)
#define TIM_M3_FLTR_CH1A_PCLK_DIV16 (0x06UL<<TIM_M3_FLTR_CH1A_POS)
#define TIM_M3_FLTR_CH1A_PCLK_DIV64 (0x07UL<<TIM_M3_FLTR_CH1A_POS)
//===CH0B比较输出相位控制
#define TIM_M3_FLTR_CCPB0_POS 7
#define TIM_M3_FLTR_CCPB0_MASK (0x01UL<<TIM_M3_FLTR_CCPB0_POS)
#define TIM_M3_FLTR_CCPB0 TIM_M3_FLTR_CCPB0_MASK
//==CH0B捕获输入滤波控制
#define TIM_M3_FLTR_OCMB0_POS 4
#define TIM_M3_FLTR_OCMB0_MASK (0x07UL<<TIM_M3_FLTR_OCMB0_POS)
#define TIM_M3_FLTR_OCMB0 TIM_M3_FLTR_OCMB0_MASK
#define TIM_M3_FLTR_OCMB0_FORCE_LOW (0x00UL<<TIM_M3_FLTR_OCMB0_POS)
#define TIM_M3_FLTR_OCMB0_FORCE_HIGH (0x01UL<<TIM_M3_FLTR_OCMB0_POS)
#define TIM_M3_FLTR_OCMB0_COMP_LOW (0x02UL<<TIM_M3_FLTR_OCMB0_POS)
#define TIM_M3_FLTR_OCMB0_COMP_HIGH (0x03UL<<TIM_M3_FLTR_OCMB0_POS)
#define TIM_M3_FLTR_OCMB0_COMP_TOGGLE (0x04UL<<TIM_M3_FLTR_OCMB0_POS)
#define TIM_M3_FLTR_OCMB0_COMP_KEEP_HIGH (0x05UL<<TIM_M3_FLTR_OCMB0_POS)
#define TIM_M3_FLTR_OCMB0_PWM_MODE1 (0x06UL<<TIM_M3_FLTR_OCMB0_POS)
#define TIM_M3_FLTR_OCMB0_PWM_MODE2 (0x07UL<<TIM_M3_FLTR_OCMB0_POS)
//==CH0B捕获输入滤波控制
#define TIM_M3_FLTR_CH0B_POS 4
#define TIM_M3_FLTR_CH0B_MASK (0x07UL<<TIM_M3_FLTR_CH0B_POS)
#define TIM_M3_FLTR_CH0B TIM_M3_FLTR_CH0B_MASK
#define TIM_M3_FLTR_CH0B_NONE (0x00UL<<TIM_M3_FLTR_CH0B_POS)
#define TIM_M3_FLTR_CH0B_PCLK_DIV1 (0x04UL<<TIM_M3_FLTR_CH0B_POS)
#define TIM_M3_FLTR_CH0B_PCLK_DIV4 (0x05UL<<TIM_M3_FLTR_CH0B_POS)
#define TIM_M3_FLTR_CH0B_PCLK_DIV16 (0x06UL<<TIM_M3_FLTR_CH0B_POS)
#define TIM_M3_FLTR_CH0B_PCLK_DIV64 (0x07UL<<TIM_M3_FLTR_CH0B_POS)
//===CH0A比较输出相位控制
#define TIM_M3_FLTR_CCPA0_POS 3
#define TIM_M3_FLTR_CCPA0_MASK (0x01UL<<TIM_M3_FLTR_CCPA0_POS)
#define TIM_M3_FLTR_CCPA0 TIM_M3_FLTR_CCPA0_MASK
//==CH0A比较输出控制
#define TIM_M3_FLTR_OCMA0_POS 0
#define TIM_M3_FLTR_OCMA0_MASK (0x07UL<<TIM_M3_FLTR_OCMA0_POS)
#define TIM_M3_FLTR_OCMA0 TIM_M3_FLTR_OCMA0_MASK
#define TIM_M3_FLTR_OCMA0_FORCE_LOW (0x00UL<<TIM_M3_FLTR_OCMA0_POS)
#define TIM_M3_FLTR_OCMA0_FORCE_HIGH (0x01UL<<TIM_M3_FLTR_OCMA0_POS)
#define TIM_M3_FLTR_OCMA0_COMP_LOW (0x02UL<<TIM_M3_FLTR_OCMA0_POS)
#define TIM_M3_FLTR_OCMA0_COMP_HIGH (0x03UL<<TIM_M3_FLTR_OCMA0_POS)
#define TIM_M3_FLTR_OCMA0_COMP_TOGGLE (0x04UL<<TIM_M3_FLTR_OCMA0_POS)
#define TIM_M3_FLTR_OCMA0_COMP_KEEP_HIGH (0x05UL<<TIM_M3_FLTR_OCMA0_POS)
#define TIM_M3_FLTR_OCMA0_PWM_MODE1 (0x06UL<<TIM_M3_FLTR_OCMA0_POS)
#define TIM_M3_FLTR_OCMA0_PWM_MODE2 (0x07UL<<TIM_M3_FLTR_OCMA0_POS)
//==CH0A捕获输入滤波控制
#define TIM_M3_FLTR_CH0A_POS 0
#define TIM_M3_FLTR_CH0A_MASK (0x07UL<<TIM_M3_FLTR_CH0A_POS)
#define TIM_M3_FLTR_CH0A TIM_M3_FLTR_CH0A_MASK
#define TIM_M3_FLTR_CH0A_NONE (0x00UL<<TIM_M3_FLTR_CH0A_POS)
#define TIM_M3_FLTR_CH0A_PCLK_DIV1 (0x04UL<<TIM_M3_FLTR_CH0A_POS)
#define TIM_M3_FLTR_CH0A_PCLK_DIV4 (0x05UL<<TIM_M3_FLTR_CH0A_POS)
#define TIM_M3_FLTR_CH0A_PCLK_DIV16 (0x06UL<<TIM_M3_FLTR_CH0A_POS)
#define TIM_M3_FLTR_CH0A_PCLK_DIV64 (0x07UL<<TIM_M3_FLTR_CH0A_POS)
//===ADC触发控制寄存器
#define TIM_M3_ADTR_EN_POS 7
#define TIM_M3_ADTR_EN_MASK (0x01UL<<TIM_M3_ADTR_EN_POS)
#define TIM_M3_ADTR_EN TIM_M3_ADTR_EN_MASK
//===CH2B比较匹配触发adc
#define TIM_M3_ADTR_CMB2EN_POS 6
#define TIM_M3_ADTR_CMB2EN_MASK (0x01UL<<TIM_M3_ADTR_CMB2EN_POS)
#define TIM_M3_ADTR_CMB2EN TIM_M3_ADTR_CMB2EN_MASK
//===CH1B比较匹配触发adc
#define TIM_M3_ADTR_CMB1EN_POS 5
#define TIM_M3_ADTR_CMB1EN_MASK (0x01UL<<TIM_M3_ADTR_CMB1EN_POS)
#define TIM_M3_ADTR_CMB1EN TIM_M3_ADTR_CMB1EN_MASK
//===CH0B比较匹配触发adc
#define TIM_M3_ADTR_CMB0EN_POS 4
#define TIM_M3_ADTR_CMB0EN_MASK (0x01UL<<TIM_M3_ADTR_CMB0EN_POS)
#define TIM_M3_ADTR_CMB0EN TIM_M3_ADTR_CMB0EN_MASK
//===CH2A比较匹配触发adc
#define TIM_M3_ADTR_CMA2EN_POS 3
#define TIM_M3_ADTR_CMA2EN_MASK (0x01UL<<TIM_M3_ADTR_CMA2EN_POS)
#define TIM_M3_ADTR_CMA2EN TIM_M3_ADTR_CMA2EN_MASK
//===CH0A比较匹配触发adc
#define TIM_M3_ADTR_CMA1EN_POS 2
#define TIM_M3_ADTR_CMA1EN_MASK (0x01UL<<TIM_M3_ADTR_CMA1EN_POS)
#define TIM_M3_ADTR_CMA1EN TIM_M3_ADTR_CMA1EN_MASK
//===CH0A比较匹配触发adc
#define TIM_M3_ADTR_CMA0EN_POS 1
#define TIM_M3_ADTR_CMA0EN_MASK (0x01UL<<TIM_M3_ADTR_CMA0EN_POS)
#define TIM_M3_ADTR_CMA0EN TIM_M3_ADTR_CMA0EN_MASK
//===事件更新触发adc
#define TIM_M3_ADTR_UEN_POS 0
#define TIM_M3_ADTR_UEN_MASK (0x01UL<<TIM_M3_ADTR_UEN_POS)
#define TIM_M3_ADTR_UEN TIM_M3_ADTR_UEN_MASK
//===通道0控制寄存器
//===捕获比较B软件触发
#define TIM_M3_CRCH0_CCGB_POS 15
#define TIM_M3_CRCH0_CCGB_MASK (0x01UL<<TIM_M3_CRCH0_CCGB_POS)
#define TIM_M3_CRCH0_CCGB TIM_M3_CRCH0_CCGB_MASK
//===捕获比较A软件触发
#define TIM_M3_CRCH0_CCGA_POS 14
#define TIM_M3_CRCH0_CCGA_MASK (0x01UL<<TIM_M3_CRCH0_CCGA_POS)
#define TIM_M3_CRCH0_CCGA TIM_M3_CRCH0_CCGA_MASK
//===B比较模式中断
#define TIM_M3_CRCH0_CISB_POS 13
#define TIM_M3_CRCH0_CISB_MASK (0x03UL<<TIM_M3_CRCH0_CISB_POS)
#define TIM_M3_CRCH0_CISB TIM_M3_CRCH0_CISB_MASK
#define TIM_M3_CRCH0_CISB_EDGE_NONE (0x00UL<<TIM_M3_CRCH0_CISB_POS)
#define TIM_M3_CRCH0_CISB_EDGE_RISE (0x01UL<<TIM_M3_CRCH0_CISB_POS)
#define TIM_M3_CRCH0_CISB_EDGE_FAIL (0x02UL<<TIM_M3_CRCH0_CISB_POS)
#define TIM_M3_CRCH0_CISB_EDGE_ALL (0x03UL<<TIM_M3_CRCH0_CISB_POS)
//===B捕获比较触发DMA使能
#define TIM_M3_CRCH0_CDMABEN_POS 11
#define TIM_M3_CRCH0_CDMABEN_MASK (0x01UL<<TIM_M3_CRCH0_CDMABEN_POS)
#define TIM_M3_CRCH0_CDMABEN TIM_M3_CRCH0_CDMABEN_MASK
//===A捕获比较触发DMA使能
#define TIM_M3_CRCH0_CDMAAEN_POS 10
#define TIM_M3_CRCH0_CDMAAEN_MASK (0x01UL<<TIM_M3_CRCH0_CDMAAEN_POS)
#define TIM_M3_CRCH0_CDMAAEN TIM_M3_CRCH0_CDMAAEN_MASK
//===B捕获比较触发中断
#define TIM_M3_CRCH0_CIEB_POS 9
#define TIM_M3_CRCH0_CIEB_MASK (0x01UL<<TIM_M3_CRCH0_CIEB_POS)
#define TIM_M3_CRCH0_CIEB TIM_M3_CRCH0_CIEB_MASK
//===B捕获比较触发中断
#define TIM_M3_CRCH0_CIEA_POS 8
#define TIM_M3_CRCH0_CIEA_MASK (0x01UL<<TIM_M3_CRCH0_CIEA_POS)
#define TIM_M3_CRCH0_CIEA TIM_M3_CRCH0_CIEA_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M3_CRCH0_BUFEB_POS 7
#define TIM_M3_CRCH0_BUFEB_MASK (0x01UL<<TIM_M3_CRCH0_BUFEB_POS)
#define TIM_M3_CRCH0_BUFEB TIM_M3_CRCH0_BUFEB_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M3_CRCH0_BUFEA_POS 6
#define TIM_M3_CRCH0_BUFEA_MASK (0x01UL<<TIM_M3_CRCH0_BUFEA_POS)
#define TIM_M3_CRCH0_BUFEA TIM_M3_CRCH0_BUFEA_MASK
#define TIM_M3_CRCH0_CSB_POS 5
#define TIM_M3_CRCH0_CSB_MASK (0x01UL<<TIM_M3_CRCH0_CSB_POS)
#define TIM_M3_CRCH0_CSB TIM_M3_CRCH0_CSB_MASK
#define TIM_M3_CRCH0_CSA_POS 4
#define TIM_M3_CRCH0_CSA_MASK (0x01UL<<TIM_M3_CRCH0_CSA_POS)
#define TIM_M3_CRCH0_CSA TIM_M3_CRCH0_CSA_MASK
#define TIM_M3_CRCH0_CFB_POS 3
#define TIM_M3_CRCH0_CFB_MASK (0x01UL<<TIM_M3_CRCH0_CFB_POS)
#define TIM_M3_CRCH0_CFB TIM_M3_CRCH0_CFB_MASK
#define TIM_M3_CRCH0_CRB_POS 2
#define TIM_M3_CRCH0_CRB_MASK (0x01UL<<TIM_M3_CRCH0_CRB_POS)
#define TIM_M3_CRCH0_CRB TIM_M3_CRCH0_CRB_MASK
//===B通道比较输出刹车电平控制
#define TIM_M3_CRCH0_BKSB_POS 2
#define TIM_M3_CRCH0_BKSB_MASK (0x03UL<<TIM_M3_CRCH0_BKSB_POS)
#define TIM_M3_CRCH0_BKSB TIM_M3_CRCH0_BKSB_MASK
#define TIM_M3_CRCH0_BKSB_HZ (0x00UL<<TIM_M3_CRCH0_BKSB_POS)
#define TIM_M3_CRCH0_BKSB_NONE (0x01UL<<TIM_M3_CRCH0_BKSB_POS)
#define TIM_M3_CRCH0_BKSB_LOW (0x02UL<<TIM_M3_CRCH0_BKSB_POS)
#define TIM_M3_CRCH0_BKSB_HIGHT (0x03UL<<TIM_M3_CRCH0_BKSB_POS)
#define TIM_M3_CRCH0_CFA_POS 1
#define TIM_M3_CRCH0_CFA_MASK (0x01UL<<TIM_M3_CRCH0_CFA_POS)
#define TIM_M3_CRCH0_CFA TIM_M3_CRCH0_CFA_MASK
#define TIM_M3_CRCH0_CRA_POS 0
#define TIM_M3_CRCH0_CRA_MASK (0x01UL<<TIM_M3_CRCH0_CRA_POS)
#define TIM_M3_CRCH0_CRA TIM_M3_CRCH0_CRA_MASK
#define TIM_M3_CRCH0_BKSA_POS 0
#define TIM_M3_CRCH0_BKSA_MASK (0x03UL<<TIM_M3_CRCH0_BKSA_POS)
#define TIM_M3_CRCH0_BKSA TIM_M3_CRCH0_BKSA_MASK
#define TIM_M3_CRCH0_BKSA_HZ (0x00UL<<TIM_M3_CRCH0_BKSA_POS)
#define TIM_M3_CRCH0_BKSA_NONE (0x01UL<<TIM_M3_CRCH0_BKSA_POS)
#define TIM_M3_CRCH0_BKSA_LOW (0x02UL<<TIM_M3_CRCH0_BKSA_POS)
#define TIM_M3_CRCH0_BKSA_HIGHT (0x03UL<<TIM_M3_CRCH0_BKSA_POS)
//===通道1控制寄存器
//===捕获比较B软件触发
#define TIM_M3_CRCH1_CCGB_POS 15
#define TIM_M3_CRCH1_CCGB_MASK (0x01UL<<TIM_M3_CRCH1_CCGB_POS)
#define TIM_M3_CRCH1_CCGB TIM_M3_CRCH1_CCGB_MASK
//===捕获比较A软件触发
#define TIM_M3_CRCH1_CCGA_POS 14
#define TIM_M3_CRCH1_CCGA_MASK (0x01UL<<TIM_M3_CRCH1_CCGA_POS)
#define TIM_M3_CRCH1_CCGA TIM_M3_CRCH1_CCGA_MASK
//===B比较模式中断
#define TIM_M3_CRCH1_CISB_POS 13
#define TIM_M3_CRCH1_CISB_MASK (0x03UL<<TIM_M3_CRCH1_CISB_POS)
#define TIM_M3_CRCH1_CISB TIM_M3_CRCH1_CISB_MASK
#define TIM_M3_CRCH1_CISB_EDGE_NONE (0x00UL<<TIM_M3_CRCH1_CISB_POS)
#define TIM_M3_CRCH1_CISB_EDGE_RISE (0x01UL<<TIM_M3_CRCH1_CISB_POS)
#define TIM_M3_CRCH1_CISB_EDGE_FAIL (0x02UL<<TIM_M3_CRCH1_CISB_POS)
#define TIM_M3_CRCH1_CISB_EDGE_ALL (0x03UL<<TIM_M3_CRCH1_CISB_POS)
//===B捕获比较触发DMA使能
#define TIM_M3_CRCH1_CDMABEN_POS 11
#define TIM_M3_CRCH1_CDMABEN_MASK (0x01UL<<TIM_M3_CRCH1_CDMABEN_POS)
#define TIM_M3_CRCH1_CDMABEN TIM_M3_CRCH1_CDMABEN_MASK
//===A捕获比较触发DMA使能
#define TIM_M3_CRCH1_CDMAAEN_POS 10
#define TIM_M3_CRCH1_CDMAAEN_MASK (0x01UL<<TIM_M3_CRCH1_CDMAAEN_POS)
#define TIM_M3_CRCH1_CDMAAEN TIM_M3_CRCH1_CDMAAEN_MASK
//===B捕获比较触发中断
#define TIM_M3_CRCH1_CIEB_POS 9
#define TIM_M3_CRCH1_CIEB_MASK (0x01UL<<TIM_M3_CRCH1_CIEB_POS)
#define TIM_M3_CRCH1_CIEB TIM_M3_CRCH1_CIEB_MASK
//===B捕获比较触发中断
#define TIM_M3_CRCH1_CIEA_POS 8
#define TIM_M3_CRCH1_CIEA_MASK (0x01UL<<TIM_M3_CRCH1_CIEA_POS)
#define TIM_M3_CRCH1_CIEA TIM_M3_CRCH1_CIEA_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M3_CRCH1_BUFEB_POS 7
#define TIM_M3_CRCH1_BUFEB_MASK (0x01UL<<TIM_M3_CRCH1_BUFEB_POS)
#define TIM_M3_CRCH1_BUFEB TIM_M3_CRCH1_BUFEB_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M3_CRCH1_BUFEA_POS 6
#define TIM_M3_CRCH1_BUFEA_MASK (0x01UL<<TIM_M3_CRCH1_BUFEA_POS)
#define TIM_M3_CRCH1_BUFEA TIM_M3_CRCH1_BUFEA_MASK
#define TIM_M3_CRCH1_CSB_POS 5
#define TIM_M3_CRCH1_CSB_MASK (0x01UL<<TIM_M3_CRCH1_CSB_POS)
#define TIM_M3_CRCH1_CSB TIM_M3_CRCH1_CSB_MASK
#define TIM_M3_CRCH1_CSA_POS 4
#define TIM_M3_CRCH1_CSA_MASK (0x01UL<<TIM_M3_CRCH1_CSA_POS)
#define TIM_M3_CRCH1_CSA TIM_M3_CRCH1_CSA_MASK
#define TIM_M3_CRCH1_CFB_POS 3
#define TIM_M3_CRCH1_CFB_MASK (0x01UL<<TIM_M3_CRCH1_CFB_POS)
#define TIM_M3_CRCH1_CFB TIM_M3_CRCH1_CFB_MASK
#define TIM_M3_CRCH1_CRB_POS 2
#define TIM_M3_CRCH1_CRB_MASK (0x01UL<<TIM_M3_CRCH1_CRB_POS)
#define TIM_M3_CRCH1_CRB TIM_M3_CRCH1_CRB_MASK
//===B通道比较输出刹车电平控制
#define TIM_M3_CRCH1_BKSB_POS 2
#define TIM_M3_CRCH1_BKSB_MASK (0x03UL<<TIM_M3_CRCH1_BKSB_POS)
#define TIM_M3_CRCH1_BKSB TIM_M3_CRCH1_BKSB_MASK
#define TIM_M3_CRCH1_BKSB_HZ (0x00UL<<TIM_M3_CRCH1_BKSB_POS)
#define TIM_M3_CRCH1_BKSB_NONE (0x01UL<<TIM_M3_CRCH1_BKSB_POS)
#define TIM_M3_CRCH1_BKSB_LOW (0x02UL<<TIM_M3_CRCH1_BKSB_POS)
#define TIM_M3_CRCH1_BKSB_HIGHT (0x03UL<<TIM_M3_CRCH1_BKSB_POS)
#define TIM_M3_CRCH1_CFA_POS 1
#define TIM_M3_CRCH1_CFA_MASK (0x01UL<<TIM_M3_CRCH1_CFA_POS)
#define TIM_M3_CRCH1_CFA TIM_M3_CRCH1_CFA_MASK
#define TIM_M3_CRCH1_CRA_POS 0
#define TIM_M3_CRCH1_CRA_MASK (0x01UL<<TIM_M3_CRCH1_CRA_POS)
#define TIM_M3_CRCH1_CRA TIM_M3_CRCH1_CRA_MASK
#define TIM_M3_CRCH1_BKSA_POS 0
#define TIM_M3_CRCH1_BKSA_MASK (0x03UL<<TIM_M3_CRCH1_BKSA_POS)
#define TIM_M3_CRCH1_BKSA TIM_M3_CRCH1_BKSA_MASK
#define TIM_M3_CRCH1_BKSA_HZ (0x00UL<<TIM_M3_CRCH1_BKSA_POS)
#define TIM_M3_CRCH1_BKSA_NONE (0x01UL<<TIM_M3_CRCH1_BKSA_POS)
#define TIM_M3_CRCH1_BKSA_LOW (0x02UL<<TIM_M3_CRCH1_BKSA_POS)
#define TIM_M3_CRCH1_BKSA_HIGHT (0x03UL<<TIM_M3_CRCH1_BKSA_POS)
//===通道2控制寄存器
//===捕获比较B软件触发
#define TIM_M3_CRCH2_CCGB_POS 15
#define TIM_M3_CRCH2_CCGB_MASK (0x01UL<<TIM_M3_CRCH2_CCGB_POS)
#define TIM_M3_CRCH2_CCGB TIM_M3_CRCH2_CCGB_MASK
//===捕获比较A软件触发
#define TIM_M3_CRCH2_CCGA_POS 14
#define TIM_M3_CRCH2_CCGA_MASK (0x01UL<<TIM_M3_CRCH2_CCGA_POS)
#define TIM_M3_CRCH2_CCGA TIM_M3_CRCH2_CCGA_MASK
//===B比较模式中断
#define TIM_M3_CRCH2_CISB_POS 13
#define TIM_M3_CRCH2_CISB_MASK (0x03UL<<TIM_M3_CRCH2_CISB_POS)
#define TIM_M3_CRCH2_CISB TIM_M3_CRCH2_CISB_MASK
#define TIM_M3_CRCH2_CISB_EDGE_NONE (0x00UL<<TIM_M3_CRCH2_CISB_POS)
#define TIM_M3_CRCH2_CISB_EDGE_RISE (0x01UL<<TIM_M3_CRCH2_CISB_POS)
#define TIM_M3_CRCH2_CISB_EDGE_FAIL (0x02UL<<TIM_M3_CRCH2_CISB_POS)
#define TIM_M3_CRCH2_CISB_EDGE_ALL (0x03UL<<TIM_M3_CRCH2_CISB_POS)
//===B捕获比较触发DMA使能
#define TIM_M3_CRCH2_CDMABEN_POS 11
#define TIM_M3_CRCH2_CDMABEN_MASK (0x01UL<<TIM_M3_CRCH2_CDMABEN_POS)
#define TIM_M3_CRCH2_CDMABEN TIM_M3_CRCH2_CDMABEN_MASK
//===A捕获比较触发DMA使能
#define TIM_M3_CRCH2_CDMAAEN_POS 10
#define TIM_M3_CRCH2_CDMAAEN_MASK (0x01UL<<TIM_M3_CRCH2_CDMAAEN_POS)
#define TIM_M3_CRCH2_CDMAAEN TIM_M3_CRCH2_CDMAAEN_MASK
//===B捕获比较触发中断
#define TIM_M3_CRCH2_CIEB_POS 9
#define TIM_M3_CRCH2_CIEB_MASK (0x01UL<<TIM_M3_CRCH2_CIEB_POS)
#define TIM_M3_CRCH2_CIEB TIM_M3_CRCH2_CIEB_MASK
//===B捕获比较触发中断
#define TIM_M3_CRCH2_CIEA_POS 8
#define TIM_M3_CRCH2_CIEA_MASK (0x01UL<<TIM_M3_CRCH2_CIEA_POS)
#define TIM_M3_CRCH2_CIEA TIM_M3_CRCH2_CIEA_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M3_CRCH2_BUFEB_POS 7
#define TIM_M3_CRCH2_BUFEB_MASK (0x01UL<<TIM_M3_CRCH2_BUFEB_POS)
#define TIM_M3_CRCH2_BUFEB TIM_M3_CRCH2_BUFEB_MASK
//===比较功能，B比较缓存使能控制
#define TIM_M3_CRCH2_BUFEA_POS 6
#define TIM_M3_CRCH2_BUFEA_MASK (0x01UL<<TIM_M3_CRCH2_BUFEA_POS)
#define TIM_M3_CRCH2_BUFEA TIM_M3_CRCH2_BUFEA_MASK
#define TIM_M3_CRCH2_CSB_POS 5
#define TIM_M3_CRCH2_CSB_MASK (0x01UL<<TIM_M3_CRCH2_CSB_POS)
#define TIM_M3_CRCH2_CSB TIM_M3_CRCH2_CSB_MASK
#define TIM_M3_CRCH2_CSA_POS 4
#define TIM_M3_CRCH2_CSA_MASK (0x01UL<<TIM_M3_CRCH2_CSA_POS)
#define TIM_M3_CRCH2_CSA TIM_M3_CRCH2_CSA_MASK
#define TIM_M3_CRCH2_CFB_POS 3
#define TIM_M3_CRCH2_CFB_MASK (0x01UL<<TIM_M3_CRCH2_CFB_POS)
#define TIM_M3_CRCH2_CFB TIM_M3_CRCH2_CFB_MASK
#define TIM_M3_CRCH2_CRB_POS 2
#define TIM_M3_CRCH2_CRB_MASK (0x01UL<<TIM_M3_CRCH2_CRB_POS)
#define TIM_M3_CRCH2_CRB TIM_M3_CRCH2_CRB_MASK
//===B通道比较输出刹车电平控制
#define TIM_M3_CRCH2_BKSB_POS 2
#define TIM_M3_CRCH2_BKSB_MASK (0x03UL<<TIM_M3_CRCH2_BKSB_POS)
#define TIM_M3_CRCH2_BKSB TIM_M3_CRCH2_BKSB_MASK
#define TIM_M3_CRCH2_BKSB_HZ (0x00UL<<TIM_M3_CRCH2_BKSB_POS)
#define TIM_M3_CRCH2_BKSB_NONE (0x01UL<<TIM_M3_CRCH2_BKSB_POS)
#define TIM_M3_CRCH2_BKSB_LOW (0x02UL<<TIM_M3_CRCH2_BKSB_POS)
#define TIM_M3_CRCH2_BKSB_HIGHT (0x03UL<<TIM_M3_CRCH2_BKSB_POS)
#define TIM_M3_CRCH2_CFA_POS 1
#define TIM_M3_CRCH2_CFA_MASK (0x01UL<<TIM_M3_CRCH2_CFA_POS)
#define TIM_M3_CRCH2_CFA TIM_M3_CRCH2_CFA_MASK
#define TIM_M3_CRCH2_CRA_POS 0
#define TIM_M3_CRCH2_CRA_MASK (0x01UL<<TIM_M3_CRCH2_CRA_POS)
#define TIM_M3_CRCH2_CRA TIM_M3_CRCH2_CRA_MASK
#define TIM_M3_CRCH2_BKSA_POS 0
#define TIM_M3_CRCH2_BKSA_MASK (0x03UL<<TIM_M3_CRCH2_BKSA_POS)
#define TIM_M3_CRCH2_BKSA TIM_M3_CRCH2_BKSA_MASK
#define TIM_M3_CRCH2_BKSA_HZ (0x00UL<<TIM_M3_CRCH2_BKSA_POS)
#define TIM_M3_CRCH2_BKSA_NONE (0x01UL<<TIM_M3_CRCH2_BKSA_POS)
#define TIM_M3_CRCH2_BKSA_LOW (0x02UL<<TIM_M3_CRCH2_BKSA_POS)
#define TIM_M3_CRCH2_BKSA_HIGHT (0x03UL<<TIM_M3_CRCH2_BKSA_POS)
//===死区控制寄存器
#define TIM_M3_DTR_VCEN_POS 14
#define TIM_M3_DTR_VCEN_MASK (0x01UL<<TIM_M3_DTR_VCEN_POS)
#define TIM_M3_DTR_VCEN TIM_M3_DTR_VCEN_MASK
//===Safety刹车控制使能
#define TIM_M3_DTR_SAFETYEN_POS 13
#define TIM_M3_DTR_SAFETYEN_MASK (0x01UL<<TIM_M3_DTR_SAFETYEN_POS)
#define TIM_M3_DTR_SAFETYEN TIM_M3_DTR_SAFETYEN_MASK
//===PWM输出控制使能
#define TIM_M3_DTR_MOEN_POS 12
#define TIM_M3_DTR_MOEN_MASK (0x01UL<<TIM_M3_DTR_MOEN_POS)
#define TIM_M3_DTR_MOEN TIM_M3_DTR_MOEN_MASK
//===PWM输出自动控制使能
#define TIM_M3_DTR_AOEN_POS 11
#define TIM_M3_DTR_AOEN_MASK (0x01UL<<TIM_M3_DTR_AOEN_POS)
#define TIM_M3_DTR_AOEN TIM_M3_DTR_AOEN_MASK
//===刹车控制使能
#define TIM_M3_DTR_BKE_POS 10
#define TIM_M3_DTR_BKE_MASK (0x01UL<<TIM_M3_DTR_BKE_POS)
#define TIM_M3_DTR_BKE TIM_M3_DTR_BKE_MASK
//===死区控制使能
#define TIM_M3_DTR_DTEN_POS 9
#define TIM_M3_DTR_DTEN_MASK (0x01UL<<TIM_M3_DTR_DTEN_POS)
#define TIM_M3_DTR_DTEN TIM_M3_DTR_DTEN_MASK
//===刹车选择
#define TIM_M3_DTR_BKSEL_POS 8
#define TIM_M3_DTR_BKSEL_MASK (0x01UL<<TIM_M3_DTR_BKSEL_POS)
#define TIM_M3_DTR_BKSEL TIM_M3_DTR_BKSEL_MASK
//===死区控制
#define TIM_M3_DTR_TIM_POS 0
#define TIM_M3_DTR_TIM_MASK (0xFFUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM TIM_M3_DTR_TIM_MASK
//===死区时间
#define TIM_M3_DTR_TIM_2 (0x00UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_3 (0x01UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_4 (0x02UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_5 (0x03UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_6 (0x04UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_7 (0x05UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_8 (0x06UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_9 (0x07UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_10 (0x08UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_11 (0x09UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_12 (0x0AUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_13 (0x0BUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_14 (0x0CUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_15 (0x0DUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_16 (0x0EUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_17 (0x0FUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_18 (0x10UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_19 (0x11UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_20 (0x12UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_21 (0x13UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_22 (0x14UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_23 (0x15UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_24 (0x16UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_25 (0x17UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_26 (0x18UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_27 (0x19UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_28 (0x1AUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_29 (0x1BUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_30 (0x1CUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_31 (0x1DUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_32 (0x1EUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_33 (0x1FUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_34 (0x20UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_35 (0x21UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_36 (0x22UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_37 (0x23UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_38 (0x24UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_39 (0x25UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_40 (0x26UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_41 (0x27UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_42 (0x28UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_43 (0x29UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_44 (0x2AUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_45 (0x2BUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_46 (0x2CUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_47 (0x2DUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_48 (0x2EUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_49 (0x2FUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_50 (0x30UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_51 (0x31UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_52 (0x32UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_53 (0x33UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_54 (0x34UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_55 (0x35UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_56 (0x36UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_57 (0x37UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_58 (0x38UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_59 (0x39UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_60 (0x3AUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_61 (0x3BUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_62 (0x3CUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_63 (0x3DUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_64 (0x3EUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_65 (0x3FUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_66 (0x40UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_67 (0x41UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_68 (0x42UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_69 (0x43UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_70 (0x44UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_71 (0x45UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_72 (0x46UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_73 (0x47UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_74 (0x48UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_75 (0x49UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_76 (0x4AUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_77 (0x4BUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_78 (0x4CUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_79 (0x4DUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_80 (0x4EUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_81 (0x4FUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_82 (0x50UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_83 (0x51UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_84 (0x52UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_85 (0x53UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_86 (0x54UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_87 (0x55UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_88 (0x56UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_89 (0x57UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_90 (0x58UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_91 (0x59UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_92 (0x5AUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_93 (0x5BUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_94 (0x5CUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_95 (0x5DUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_96 (0x5EUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_97 (0x5FUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_98 (0x60UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_99 (0x61UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_100 (0x62UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_101 (0x63UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_102 (0x64UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_103 (0x65UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_104 (0x66UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_105 (0x67UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_106 (0x68UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_107 (0x69UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_108 (0x6AUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_109 (0x6BUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_110 (0x6CUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_111 (0x6DUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_112 (0x6EUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_113 (0x6FUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_114 (0x70UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_115 (0x71UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_116 (0x72UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_117 (0x73UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_118 (0x74UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_119 (0x75UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_120 (0x76UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_121 (0x77UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_122 (0x78UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_123 (0x79UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_124 (0x7AUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_125 (0x7BUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_126 (0x7CUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_127 (0x7DUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_128 (0x7EUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_129 (0x7FUL<<TIM_M3_DTR_TIM_POS)
\
#define TIM_M3_DTR_TIM_130 (0x80UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_132 (0x81UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_134 (0x82UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_136 (0x83UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_138 (0x84UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_140 (0x85UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_142 (0x86UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_144 (0x87UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_146 (0x88UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_148 (0x89UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_150 (0x8AUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_152 (0x8BUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_154 (0x8CUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_156 (0x8DUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_158 (0x8EUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_160 (0x8FUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_162 (0x90UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_164 (0x91UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_166 (0x92UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_168 (0x93UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_170 (0x94UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_172 (0x95UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_174 (0x96UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_176 (0x97UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_178 (0x98UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_180 (0x99UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_182 (0x9AUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_184 (0x9BUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_186 (0x9CUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_188 (0x9DUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_190 (0x9EUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_192 (0x9FUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_194 (0xA0UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_196 (0xA1UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_198 (0xA2UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_200 (0xA3UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_202 (0xA4UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_204 (0xA5UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_206 (0xA6UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_208 (0xA8UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_210 (0xA9UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_212 (0xAAUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_214 (0xABUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_216 (0xACUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_218 (0xADUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_220 (0xAEUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_222 (0xAFUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_224 (0xB0UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_226 (0xB1UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_228 (0xB2UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_230 (0xB3UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_232 (0xB4UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_234 (0xB5UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_236 (0xB6UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_238 (0xB7UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_240 (0xB8UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_242 (0xB9UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_246 (0xBAUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_248 (0xBBUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_250 (0xBCUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_252 (0xBDUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_254 (0xBEUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_256 (0xBFUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_258 (0xC0UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_266 (0xC1UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_274 (0xC2UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_282 (0xC3UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_290 (0xC4UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_296 (0xC5UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_302 (0xC6UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_308 (0xC7UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_314 (0xC8UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_322 (0xC9UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_330 (0xCAUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_338 (0xCBUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_346 (0xCCUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_354 (0xCDUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_362 (0xCEUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_370 (0xCFUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_378 (0xD0UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_386 (0xD1UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_394 (0xD2UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_402 (0xD3UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_410 (0xD4UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_418 (0xD5UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_426 (0xD6UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_434 (0xD7UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_442 (0xD8UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_450 (0xD9UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_458 (0xDAUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_466 (0xDBUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_474 (0xDCUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_482 (0xDDUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_490 (0xDEUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_498 (0xDFUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_514 (0xE0UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_530 (0xE1UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_546 (0xE2UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_547 (0xE3UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_562 (0xE4UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_578 (0xE5UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_594 (0xE6UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_610 (0xE7UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_642 (0xE8UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_658 (0xE9UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_674 (0xEAUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_690 (0xEBUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_706 (0xECUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_722 (0xEDUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_738 (0xEEUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_754 (0xEFUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_770 (0xF0UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_786 (0xF1UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_802 (0xF2UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_818 (0xF3UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_834 (0xF4UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_850 (0xF5UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_866 (0xF6UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_882 (0xF7UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_898 (0xF8UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_914 (0xF9UL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_930 (0xFAUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_946 (0xFBUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_962 (0xFCUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_978 (0xFDUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_994 (0xFEUL<<TIM_M3_DTR_TIM_POS)
#define TIM_M3_DTR_TIM_1010 (0xFFUL<<TIM_M3_DTR_TIM_POS)
//===重复周期设置值
#define TIM_M3_RCR_RCR_POS 0
#define TIM_M3_RCR_RCR_MASK (0xFFUL<<TIM_M3_RCR_RCR_POS)
#define TIM_M3_RCR_RCR TIM_M3_RCR_RCR_MASK
//===通道0比较捕获寄存器
#define TIM_M3_CCR_CCR0A_POS 0
#define TIM_M3_CCR_CCR0A_MASK (0xFFFFUL<<TIM_M3_CCR_CCR0A_POS)
#define TIM_M3_CCR_CCR0A TIM_M3_CCR_CCR0A_MASK
#define TIM_M3_CCR_CCR0B_POS 0
#define TIM_M3_CCR_CCR0B_MASK (0xFFFFUL<<TIM_M3_CCR_CCR0A_POS)
#define TIM_M3_CCR_CCR0B TIM_M3_CCR_CCR0B_MASK
//===通道1比较捕获寄存器
#define TIM_M3_CCR_CCR1A_POS 0
#define TIM_M3_CCR_CCR1A_MASK (0xFFFFUL<<TIM_M3_CCR_CCR1A_POS)
#define TIM_M3_CCR_CCR1A TIM_M3_CCR_CCR1A_MASK
#define TIM_M3_CCR_CCR1B_POS 0
#define TIM_M3_CCR_CCR1B_MASK (0xFFFFUL<<TIM_M3_CCR_CCR1B_POS)
#define TIM_M3_CCR_CCR1B TIM_M3_CCR_CCR1B_MASK
//===通道2比较捕获寄存器
#define TIM_M3_CCR_CCR2A_POS 0
#define TIM_M3_CCR_CCR2A_MASK (0xFFFFUL<<TIM_M3_CCR_CCR2A_POS)
#define TIM_M3_CCR_CCR2A TIM_M3_CCR_CCR2A_MASK
#define TIM_M3_CCR_CCR2B_POS 0
#define TIM_M3_CCR_CCR2B_MASK (0xFFFFUL<<TIM_M3_CCR_CCR2B_POS)
#define TIM_M3_CCR_CCR2B TIM_M3_CCR_CCR2B_MASK
#pragma endregion
#pragma endregion
#pragma region TIMP
//===高级定时器
typedef struct
{
__IO uint32_t CNTER; //---重载寄存器
__IO uint32_t PERAR; //---16位模式计数寄存器
__IO uint32_t PERBR; //---32位模式计数寄存器
uint32_t RESERVED1; //---保留字节
__IO uint32_t GCMAR; //---控制寄存器
__IO uint32_t GCMBR; //---中断标志
__IO uint32_t GCMCR; //---中断标志清除
__IO uint32_t GCMDR; //---中断标志
uint32_t RESERVED2[2]; //---保留字节
__IO uint32_t SCMAR; //---主从模式控制
__IO uint32_t SCMBR; //---滤波控制
uint32_t RESERVED3[4]; //---保留字节
__IO uint32_t DTUAR; //---ADC触发控制
__IO uint32_t DTDAR; //---比较单元0控制寄存器
uint32_t RESERVED4[2]; //---保留字节
__IO uint32_t GCONR; //---比较单元1控制寄存器
__IO uint32_t ICONR; //---比较单元2控制寄存器
__IO uint32_t PCONR; //---死区寄存器
__IO uint32_t BCONR; //---重复计数寄存器
__IO uint32_t DCONT; //---控制寄存器1
__IO uint32_t FCONR; //---比较0A寄存器
__IO uint32_t VPERR; //---比较0B寄存器
__IO uint32_t STFLR; //---比较1A寄存器
__IO uint32_t HSTAR; //---比较1B寄存器
__IO uint32_t HSTPR; //---比较2A寄存器
__IO uint32_t HCELR; //---比较2B寄存器
__IO uint32_t HCPAR; //---比较0A寄存器
__IO uint32_t HCPBR; //---比较0B寄存器
__IO uint32_t HCUPR; //---比较1A寄存器
__IO uint32_t HCDOR; //---比较1B寄存器
uint32_t RESERVED5[28]; //---保留字节
__IO uint32_t SR; //---比较2A寄存器
__IO uint32_t CSR; //---比较2B寄存器
__IO uint32_t CR; //---比较2B寄存器
uint32_t RESERVED6; //---保留字节
__IO uint32_t AOSSR; //---比较1B寄存器
__IO uint32_t AOSCL; //---比较2A寄存器
__IO uint32_t PTBKS; //---比较2B寄存器
__IO uint32_t TTRIG; //---比较0A寄存器
__IO uint32_t ITRIG; //---比较0B寄存器
__IO uint32_t PTBKP; //---比较1A寄存器
uint32_t RESERVED7[179]; //---保留字节
__IO uint32_t SSTAR; //---比较1B寄存器
__IO uint32_t SSTPR; //---比较2A寄存器
__IO uint32_t SCLRR; //---比较2B寄存器
} TIMP_TypeDef;
#pragma endregion
#pragma region LPTIM
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CNT; //---控制寄存器1
__IO uint32_t ARR; //---控制寄存器1
uint32_t RESERVED; //---保留字节
__IO uint32_t CR; //---控制寄存器1
__IO uint32_t SR; //---控制寄存器1
__IO uint32_t CSR; //---控制寄存器1
} LPTIM_TypeDef;
#define LPTIM_ARR_ARR_POS 0
#define LPTIM_ARR_ARR_MASK (0xFFFFUL<<LPTIM_ARR_ARR_POS)
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_MASK
#define LPTIM_CNT_CNT_POS 0
#define LPTIM_CNT_CNT_MASK (0xFFFFUL<<LPTIM_CNT_CNT_POS)
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_MASK
//===低功耗定时器控制模式
#define LPTIM_CR_PRS_POS 11
#define LPTIM_CR_PRS_MASK (0x07UL<<LPTIM_CR_PRS_POS)
#define LPTIM_CR_PRS LPTIM_CR_PRS_MASK
#define LPTIM_CR_PRS_1 (0x00UL<<LPTIM_CR_PRS_POS)
#define LPTIM_CR_PRS_2 (0x01UL<<LPTIM_CR_PRS_POS)
#define LPTIM_CR_PRS_4 (0x02UL<<LPTIM_CR_PRS_POS)
#define LPTIM_CR_PRS_8 (0x03UL<<LPTIM_CR_PRS_POS)
#define LPTIM_CR_PRS_16 (0x04UL<<LPTIM_CR_PRS_POS)
#define LPTIM_CR_PRS_32 (0x05UL<<LPTIM_CR_PRS_POS)
#define LPTIM_CR_PRS_64 (0x06UL<<LPTIM_CR_PRS_POS)
#define LPTIM_CR_PRS_256 (0x07UL<<LPTIM_CR_PRS_POS)
//===中断使能控制
#define LPTIM_CR_IE_POS 10
#define LPTIM_CR_IE_MASK (0x01UL<<LPTIM_CR_IE_POS)
#define LPTIM_CR_IE LPTIM_CR_IE_MASK
//===门控端口极性
#define LPTIM_CR_GATEP_POS 9
#define LPTIM_CR_GATEP_MASK (0x01UL<<LPTIM_CR_GATEP_POS)
#define LPTIM_CR_GATEP LPTIM_CR_GATEP_MASK
//===定时器门控使能
#define LPTIM_CR_GATEN_POS 8
#define LPTIM_CR_GATEN_MASK (0x01UL<<LPTIM_CR_GATEN_POS)
#define LPTIM_CR_GATEN LPTIM_CR_GATEN_MASK
//===同步标志
#define LPTIM_CR_WT_FLAG_POS 7
#define LPTIM_CR_WT_FLAG_MASK (0x01UL<<LPTIM_CR_WT_FLAG_POS)
#define LPTIM_CR_WT_FLAG LPTIM_CR_WT_FLAG_MASK
//===时钟选择
#define LPTIM_CR_TCK_SEL_POS 4
#define LPTIM_CR_TCK_SEL_MASK (0x03UL<<LPTIM_CR_TCK_SEL_POS)
#define LPTIM_CR_TCK_SEL LPTIM_CR_TCK_SEL_MASK
#define LPTIM_CR_TCK_SEL_PCLK (0x00UL<<LPTIM_CR_TCK_SEL_POS)
#define LPTIM_CR_TCK_SEL_XTL (0x02UL<<LPTIM_CR_TCK_SEL_POS)
#define LPTIM_CR_TCK_SEL_RCL (0x03UL<<LPTIM_CR_TCK_SEL_POS)
//===TOG使能控制
#define LPTIM_CR_TOGEN_POS 3
#define LPTIM_CR_TOGEN_MASK (0x01UL<<LPTIM_CR_TOGEN_POS)
#define LPTIM_CR_TOGEN LPTIM_CR_TOGEN_MASK
//===定时/计数模式选择
#define LPTIM_CR_CT_POS 2
#define LPTIM_CR_CT_MASK (0x01UL<<LPTIM_CR_CT_POS)
#define LPTIM_CR_CT LPTIM_CR_CT_MASK
//===自由/自动重载模式选择
#define LPTIM_CR_MD_POS 1
#define LPTIM_CR_MD_MASK (0x01UL<<LPTIM_CR_MD_POS)
#define LPTIM_CR_MD LPTIM_CR_MD_MASK
//===定时器使能
#define LPTIM_CR_EN_POS 0
#define LPTIM_CR_EN_MASK (0x01UL<<LPTIM_CR_EN_POS)
#define LPTIM_CR_EN LPTIM_CR_EN_MASK
//===中断标志寄存器
#define LPTIM_SR_IE_POS 0
#define LPTIM_SR_IE_MASK (0x01U<<LPTIM_SR_IE_POS)
#define LPTIM_SR_IE LPTIM_SR_IE_MASK
//===中断标志清除寄存器
#define LPTIM_CSR_IE_POS 0
#define LPTIM_CSR_IE_MASK (0x01U<<LPTIM_SR_IE_POS)
#define LPTIM_CSR_IE LPTIM_SR_IE_MASK
#pragma endregion
#pragma region TRIM
//===时钟校准模块
typedef struct
{
__IO uint32_t CR; //---配置寄存器
__IO uint32_t REFCON; //---参考计数器初值配置寄存器
__IO uint32_t REFCNT; //---参考计数器值
__IO uint32_t CALCNT; //---校准计数器值
__IO uint32_t SR; //---中断标志位寄存器
__IO uint32_t CSR; //---中断标志位清除计数器
__IO uint32_t CALCON; //---校准计数器溢出值配置寄存器
} TRIM_TypeDef;
//===待校准/监测时钟选择高位寄存器
#define TRIM_CR_CALCLK_H_POS 8
#define TRIM_CR_CALCLK_H_MASK (0x01UL<<TRIM_CR_CALCLK_H_POS)
#define TRIM_CR_CALCLK_H TRIM_CR_CALCLK_H_MASK
#define TRIM_CR_CALCLK_L_POS 4
#define TRIM_CR_CALCLK_L_MASK (0x03UL<<TRIM_CR_CALCLK_L_POS)
#define TRIM_CR_CALCLK_L TRIM_CR_CALCLK_L_MASK
//===校准时钟选择
#define TRIM_CR_CALCLK_MASK ((0x01UL<<TRIM_CR_CALCLK_H_POS)|(0x03UL<<TRIM_CR_CALCLK_L_POS))
#define TRIM_CR_CALCLK_RCH ((0x00UL<<TRIM_CR_CALCLK_H_POS)|(0x00UL<<TRIM_CR_CALCLK_L_POS))
#define TRIM_CR_CALCLK_XTH ((0x00UL<<TRIM_CR_CALCLK_H_POS)|(0x01UL<<TRIM_CR_CALCLK_L_POS))
#define TRIM_CR_CALCLK_RCL ((0x00UL<<TRIM_CR_CALCLK_H_POS)|(0x02UL<<TRIM_CR_CALCLK_L_POS))
#define TRIM_CR_CALCLK_XTL ((0x00UL<<TRIM_CR_CALCLK_H_POS)|(0x03UL<<TRIM_CR_CALCLK_L_POS))
#define TRIM_CR_CALCLK_PLL ((0x01UL<<TRIM_CR_CALCLK_H_POS)|(0x00UL<<TRIM_CR_CALCLK_L_POS))
//===校准中断使能位
#define TRIM_CR_IE_POS 7
#define TRIM_CR_IE_MASK (0x01UL<<TRIM_CR_IE_POS)
#define TRIM_CR_IE TRIM_CR_IE_MASK
//===监测模式使能位
#define TRIM_CR_EN_POS 6
#define TRIM_CR_EN_MASK (0x01UL<<TRIM_CR_EN_POS)
#define TRIM_CR_EN TRIM_CR_EN_MASK
//===参考时钟选择
#define TRIM_CR_REFCLK_POS 1
#define TRIM_CR_REFCLK_MASK (0x07UL<<TRIM_CR_REFCLK_POS)
#define TRIM_CR_REFCLK TRIM_CR_REFCLK_MASK
#define TRIM_CR_REFCLK_RCH (0x00UL<<TRIM_CR_REFCLK_POS)
#define TRIM_CR_REFCLK_XTH (0x01UL<<TRIM_CR_REFCLK_POS)
#define TRIM_CR_REFCLK_RCL (0x02UL<<TRIM_CR_REFCLK_POS)
#define TRIM_CR_REFCLK_XTL (0x03UL<<TRIM_CR_REFCLK_POS)
#define TRIM_CR_REFCLK_IRC10K (0x04UL<<TRIM_CR_REFCLK_POS)
#define TRIM_CR_REFCLK_EXCLK (0x05UL<<TRIM_CR_REFCLK_POS)
//===校准/监测开始寄存器
#define TRIM_CR_START_POS 0
#define TRIM_CR_START_MASK (0x01UL<<TRIM_CR_START_POS)
#define TRIM_CR_START TRIM_CR_START_MASK
//===PLL失效标注
#define TRIM_SR_PLL_POS 4
#define TRIM_SR_PLL_MASK (0x01UL<<TRIM_SR_PLL_POS)
#define TRIM_SR_PLL TRIM_SR_PLL_MASK
//===XTH失效标志
#define TRIM_SR_XTH_POS 3
#define TRIM_SR_XTH_MASK (0x01UL<<TRIM_SR_XTH_POS)
#define TRIM_SR_XTH TRIM_SR_XTH_MASK
//===XTL失效标志
#define TRIM_SR_XTL_POS 2
#define TRIM_SR_XTL_MASK (0x01UL<<TRIM_SR_XTL_POS)
#define TRIM_SR_XTL TRIM_SR_XTL_MASK
//===校准溢出标志
#define TRIM_SR_CALOF_POS 1
#define TRIM_SR_CALOF_MASK (0x01UL<<TRIM_SR_CALOF_POS)
#define TRIM_SR_CALOF TRIM_SR_CALOF_MASK
//===参考计数器停止标志
#define TRIM_SR_REFSTOP_POS 0
#define TRIM_SR_REFSTOP_MASK (0x01UL<<TRIM_SR_REFSTOP_POS)
#define TRIM_SR_REFSTOP TRIM_SR_REFSTOP_MASK
//===清除PLL失效标注
#define TRIM_CSR_PLL_POS 4
#define TRIM_CSR_PLL_MASK (0x01UL<<TRIM_CSR_PLL_POS)
#define TRIM_CSR_PLL TRIM_CSR_PLL_MASK
//===清除XTH失效标志
#define TRIM_CSR_XTH_POS 3
#define TRIM_CSR_XTH_MASK (0x01UL<<TRIM_CSR_XTH_POS)
#define TRIM_CSR_XTH TRIM_CSR_XTH_MASK
//===清除XTL失效标志
#define TRIM_CSR_XTL_POS 2
#define TRIM_CSR_XTL_MASK (0x01UL<<TRIM_CSR_XTL_POS)
#define TRIM_CSR_XTL TRIM_CSR_XTL_MASK
#pragma endregion
#pragma region OPA
//===运算放大器
typedef struct
{
__IO uint32_t CR; //---配置寄存器
} OPA_TypeDef;
#define OPA_CR_CH4_EN_POS 6
#define OPA_CR_CH4_EN_MASK (0x01UL<<OPA_CR_CH4_EN_POS)
#define OPA_CR_CH4_EN OPA_CR_CH4_EN_MASK
#define OPA_CR_CH3_EN_POS 5
#define OPA_CR_CH3_EN_MASK (0x01UL<<OPA_CR_CH3_EN_POS)
#define OPA_CR_CH3_EN OPA_CR_CH3_EN_MASK
#define OPA_CR_CH2_EN_POS 4
#define OPA_CR_CH2_EN_MASK (0x01UL<<OPA_CR_CH2_EN_POS)
#define OPA_CR_CH2_EN OPA_CR_CH2_EN_MASK
#define OPA_CR_CH1_EN_POS 3
#define OPA_CR_CH1_EN_MASK (0x01UL<<OPA_CR_CH1_EN_POS)
#define OPA_CR_CH1_EN OPA_CR_CH1_EN_MASK
#define OPA_CR_BUFFER_EN_POS 2
#define OPA_CR_BUFFER_EN_MASK (0x01UL<<OPA_CR_BUFFER_EN_POS)
#define OPA_CR_BUFFER_EN OPA_CR_BUFFER_EN_MASK
#define OPA_CR_EN_POS 0
#define OPA_CR_EN_MASK (0x01UL<<OPA_CR_EN_POS)
#define OPA_CR_EN OPA_CR_EN_MASK
#pragma endregion
#pragma region PCA
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CCON; //---控制寄存器1
__IO uint32_t CMOD; //---控制寄存器1
__IO uint32_t CNT; //---控制寄存器1
__IO uint32_t CSR; //---控制寄存器1
__IO uint32_t CCAPM0; //---控制寄存器1
__IO uint32_t CCAPM1; //---控制寄存器1
__IO uint32_t CCAPM2; //---控制寄存器1
__IO uint32_t CCAPM3; //---控制寄存器1
__IO uint32_t CCAPM4; //---控制寄存器1
__IO uint32_t CCAP0H; //---控制寄存器1
__IO uint32_t CCAP0L; //---控制寄存器1
__IO uint32_t CCAP1H; //---控制寄存器1
__IO uint32_t CCAP1L; //---控制寄存器1
__IO uint32_t CCAP2H; //---控制寄存器1
__IO uint32_t CCAP2L; //---控制寄存器1
__IO uint32_t CCAP3H; //---控制寄存器1
__IO uint32_t CCAP3L; //---控制寄存器1
__IO uint32_t CCAP4H; //---控制寄存器1
__IO uint32_t CCAP4L; //---控制寄存器1
__IO uint32_t CCAPO; //---控制寄存器1
__IO uint32_t CCAP0; //---控制寄存器1
__IO uint32_t CCAP1; //---控制寄存器1
__IO uint32_t CCAP2; //---控制寄存器1
__IO uint32_t CCAP3; //---控制寄存器1
__IO uint32_t CCAP4; //---控制寄存器1
__IO uint32_t CARR; //---控制寄存器1
__IO uint32_t EPWM; //---控制寄存器1
} PCA_TypeDef;
#pragma endregion
#pragma region WDT
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t RST; //---控制寄存器1
__IO uint32_t CON; //---控制寄存器1
} WDT_TypeDef;
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t RST; //---控制寄存器1
__IO uint32_t CON; //---控制寄存器1
} IWDG_TypeDef;
//===WDT中断标志
#define IWDG_CON_INT_FLAG_POS 7
#define IWDG_CON_INT_FLAG_MASK (0x01UL<<IWDG_CON_INT_FLAG_POS)
#define IWDG_CON_INT_FLAG IWDG_CON_INT_FLAG_MASK
//===WDT溢出后的工作配置
#define IWDG_CON_INT_EN_POS 5
#define IWDG_CON_INT_EN_MASK (0x01UL<<IWDG_CON_INT_EN_POS)
#define IWDG_CON_INT_EN IWDG_CON_INT_EN_MASK
//===WDT运行标志
#define IWDG_CON_READY_POS 4
#define IWDG_CON_READY_MASK (0x01UL<<IWDG_CON_READY_POS)
#define IWDG_CON_READY IWDG_CON_READY_MASK
//===WDT定时器的溢出时间配置
#define IWDG_CON_WOV_POS 0
#define IWDG_CON_WOV_MASK (0x0FUL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV IWDG_CON_WOV_MASK
//===看门狗溢出时间
#define IWDG_CON_WOV_MS_1P6 (0x00UL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_3P2 (0x01UL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_6P4 (0x02UL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_13 (0x03UL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_26 (0x04UL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_51 (0x05UL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_102 (0x06UL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_205 (0x07UL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_500 (0x08UL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_820 (0x09UL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_1640 (0x0AUL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_3280 (0x0BUL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_6550 (0x0CUL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_13100 (0x0DUL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_26200 (0x0EUL<<IWDG_CON_WOV_POS)
#define IWDG_CON_WOV_MS_52400 (0x0FUL<<IWDG_CON_WOV_POS)
#pragma endregion
#pragma region ADC
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR0; //---控制寄存器1
__IO uint32_t CR1; //---控制寄存器1 08
uint32_t RESERVED1[13]; //---保留字节
__IO uint32_t SQR[3]; //---顺序扫描转换通道配置寄存器
__IO uint32_t JQR; //---插队扫描转换通道配置寄存器
__IO uint32_t SQRDR[16]; //---顺序扫描装换结果配置寄存器
__IO uint32_t JQRDR[4]; //---插队扫描装换结果配置寄存器
__I uint32_t DR; //---转换结果
__I uint32_t DRACC; //---转换累加结果
__IO uint32_t HT; //---比较上阈值
__IO uint32_t LT; //---比较下阈值
__IO uint32_t SR; //---标志寄存器
__IO uint32_t CSR; //---清除标志寄存器
__IO uint32_t EXTRIG0; //---外部触发源0
__IO uint32_t EXTRIG1; //---外部触发源1
__IO uint32_t SGLSTART; //---单次转换开始
__IO uint32_t SQRSTART; //---顺序转换开始
__IO uint32_t JQRSTART; //---插队转换开始
__IO uint32_t ALLSTART; //---全部转换开始
} ADC_TypeDef;
//===配置寄存器0
#define ADC_CR0_IE_POS 15
#define ADC_CR0_IE_MASK (0x01UL<<ADC_CR0_IE_POS)
#define ADC_CR0_IE ADC_CR0_IE_MASK
#define ADC_CR0_INREF_POS 14
#define ADC_CR0_INREF_MASK (0x01UL<<ADC_CR0_INREF_POS)
#define ADC_CR0_INREF ADC_CR0_INREF_MASK
#define ADC_CR0_SAM_POS 12
#define ADC_CR0_SAM_MASK (0x03UL<<ADC_CR0_SAM_POS)
#define ADC_CR0_SAM ADC_CR0_SAM_MASK
#define ADC_CR0_SAM_CYCLE_4 (0x00UL<<ADC_CR0_SAM_POS)
#define ADC_CR0_SAM_CYCLE_6 (0x01UL<<ADC_CR0_SAM_POS)
#define ADC_CR0_SAM_CYCLE_8 (0x02UL<<ADC_CR0_SAM_POS)
#define ADC_CR0_SAM_CYCLE_12 (0x03UL<<ADC_CR0_SAM_POS)
#define ADC_CR0_BUFFER_POS 11
#define ADC_CR0_BUFFER_MASK (0x01UL<<ADC_CR0_BUFFER_POS)
#define ADC_CR0_BUFFER ADC_CR0_BUFFER_MASK
#define ADC_CR0_REF_POS 9
#define ADC_CR0_REF_MASK (0x03UL<<ADC_CR0_REF_POS)
#define ADC_CR0_REF ADC_CR0_REF_MASK
#define ADC_CR0_REF_IN1P5 (0x00UL<<ADC_CR0_REF_POS)
#define ADC_CR0_REF_IN2P5 (0x01UL<<ADC_CR0_REF_POS)
#define ADC_CR0_REF_EXREF (0x02UL<<ADC_CR0_REF_POS)
#define ADC_CR0_REF_AVCC (0x03UL<<ADC_CR0_REF_POS)
#define ADC_CR0_CH_POS 4
#define ADC_CR0_CH_MASK (0x1FUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH ADC_CR0_CH_MASK
#define ADC_CR0_CH_AIN0 (0x00UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN1 (0x01UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN2 (0x02UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN3 (0x03UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN4 (0x04UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN5 (0x05UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN6 (0x06UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN7 (0x07UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN8 (0x08UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN9 (0x09UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN10 (0x0AUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN11 (0x0BUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN12 (0x0CUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN13 (0x0DUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN14 (0x0EUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN15 (0x0FUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN16 (0x10UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN17 (0x11UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN18 (0x12UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN19 (0x13UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN20 (0x14UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN21 (0x15UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN22 (0x16UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN23 (0x17UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN24 (0x18UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AIN25 (0x19UL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_DAC (0x1AUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_AVCC_P3 (0x1BUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_TEMP (0x1CUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CH_IN1P2 (0x1DUL<<ADC_CR0_CH_POS)
#define ADC_CR0_CLK_POS 2
#define ADC_CR0_CLK_MASK (0x03UL<<ADC_CR0_CLK_POS)
#define ADC_CR0_CLK ADC_CR0_CLK_MASK
#define ADC_CR0_CLK_DIV1 (0x00UL<<ADC_CR0_CLK_POS)
#define ADC_CR0_CLK_DIV2 (0x01UL<<ADC_CR0_CLK_POS)
#define ADC_CR0_CLK_DIV4 (0x02UL<<ADC_CR0_CLK_POS)
#define ADC_CR0_CLK_DIV8 (0x03UL<<ADC_CR0_CLK_POS)
#define ADC_CR0_EN_POS 0
#define ADC_CR0_EN_MASK (0x01UL<<ADC_CR0_EN_POS)
#define ADC_CR0_EN ADC_CR0_EN_MASK
//===配置寄存器1
#define ADC_CR1_ACC_CLR_POS 15
#define ADC_CR1_ACC_CLR_MASK (0x01UL<<ADC_CR1_ACC_CLR_POS)
#define ADC_CR1_ACC_CLR ADC_CR1_ACC_CLR_MASK
#define ADC_CR1_REG_CMP_POS 14
#define ADC_CR1_REG_CMP_MASK (0x01UL<<ADC_CR1_REG_CMP_POS)
#define ADC_CR1_REG_CMP ADC_CR1_REG_CMP_MASK
#define ADC_CR1_HT_CMP_POS 13
#define ADC_CR1_HT_CMP_MASK (0x01UL<<ADC_CR1_HT_CMP_POS)
#define ADC_CR1_HT_CMP ADC_CR1_HT_CMP_MASK
#define ADC_CR1_LT_CMP_POS 12
#define ADC_CR1_LT_CMP_MASK (0x01UL<<ADC_CR1_LT_CMP_POS)
#define ADC_CR1_LT_CMP ADC_CR1_LT_CMP_MASK
#define ADC_CR1_ACC_EN_POS 11
#define ADC_CR1_ACC_EN_MASK (0x01UL<<ADC_CR1_ACC_EN_POS)
#define ADC_CR1_ACC_EN ADC_CR1_ACC_EN_MASK
#define ADC_CR1_MODE_POS 10
#define ADC_CR1_MODE_MASK (0x01UL<<ADC_CR1_MODE_POS)
#define ADC_CR1_MODE ADC_CR1_MODE_MASK
#define ADC_CR1_DMA_JQR_POS 9
#define ADC_CR1_DMA_JQR_MASK (0x01UL<<ADC_CR1_DMA_JQR_POS)
#define ADC_CR1_DMA_JQR ADC_CR1_DMA_JQR_MASK
#define ADC_CR1_DMA_SQR_POS 8
#define ADC_CR1_DMA_SQR_MASK (0x01UL<<ADC_CR1_DMA_SQR_POS)
#define ADC_CR1_DMA_SQR ADC_CR1_DMA_SQR_MASK
#define ADC_CR1_TH_CH_POS 3
#define ADC_CR1_TH_CH_MASK (0x1FUL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH ADC_CR1_TH_CH_MASK
#define ADC_CR1_TH_CH_AIN0 (0x00UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN1 (0x01UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN2 (0x02UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN3 (0x03UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN4 (0x04UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN5 (0x05UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN6 (0x06UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN7 (0x07UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN8 (0x08UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN9 (0x09UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN10 (0x0AUL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN11 (0x0BUL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN12 (0x0CUL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN13 (0x0DUL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN14 (0x0EUL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN15 (0x0FUL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN16 (0x10UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN17 (0x11UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN18 (0x12UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN19 (0x13UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN20 (0x14UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN21 (0x15UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN22 (0x16UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN23 (0x17UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN24 (0x18UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN25 (0x19UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN26 (0x11UL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN27 (0x1BUL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN28 (0x1CUL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_TH_CH_AIN29 (0x1DUL<<ADC_CR1_TH_CH_POS)
#define ADC_CR1_ALIGN_POS 2
#define ADC_CR1_ALIGN_MASK (0x01UL<<ADC_CR1_ALIGN_POS)
#define ADC_CR1_ALIGN ADC_CR1_ALIGN_MASK
//===转换通道配置寄存器
#define ADC_SQR_MUX0_MASK (0x1FUL<<0)
#define ADC_SQR_MUX0_POS 0
#define ADC_SQR_MUX1_MASK (0x1FUL<<5)
#define ADC_SQR_MUX1_POS 5
#define ADC_SQR_MUX2_MASK (0x1FUL<<10)
#define ADC_SQR_MUX2_POS 10
#define ADC_SQR_MUX3_MASK (0x1FUL<<15)
#define ADC_SQR_MUX3_POS 15
#define ADC_SQR_MUX4_MASK (0x1FUL<<20)
#define ADC_SQR_MUX4_POS 20
#define ADC_SQR_MUX5_MASK (0x1FUL<<25)
#define ADC_SQR_MUX5_POS 25
#define ADC_SQR_CNT_MASK (0x0FUL<<20)
#define ADC_SQR_CNT_POS 20
#define ADC_JQR_MUX0_MASK (0x1FUL<<0)
#define ADC_JQR_MUX0_POS 0
#define ADC_JQR_MUX1_MASK (0x1FUL<<5)
#define ADC_JQR_MUX1_POS 5
#define ADC_JQR_MUX2_MASK (0x1FUL<<10)
#define ADC_JQR_MUX2_POS 10
#define ADC_JQR_MUX3_MASK (0x1FUL<<15)
#define ADC_JQR_MUX3_POS 15
#define ADC_JQR_CNT_MASK (0x03UL<<20)
#define ADC_JQR_CNT_POS 20
//===ADC转换结果
#define ADC_DR_MASK (0x0FFFUL<<0)
#define ADC_DR_ACC_MASK (0xFFFFFUL<<0)
//===ADC上下阈值
#define ADC_DR_HT_MASK (0x0FFFUL<<0)
#define ADC_DR_LT_ACC_MASK (0x0FFFUL<<0)
//===中断标志
#define ADC_SR_JQR_POS 5
#define ADC_SR_JQR_MASK (0x01UL<<ADC_SR_JQR_POS)
#define ADC_SR_JQR ADC_SR_JQR_MASK
#define ADC_SR_SQR_POS 4
#define ADC_SR_SQR_MASK (0x01UL<<ADC_SR_SQR_POS)
#define ADC_SR_SQR ADC_SR_SQR_MASK
#define ADC_SR_CMP_POS 3
#define ADC_SR_CMP_MASK (0x01UL<<ADC_SR_CMP_POS)
#define ADC_SR_CMP ADC_SR_CMP_MASK
#define ADC_SR_HT_POS 2
#define ADC_SR_HT_MASK (0x01UL<<ADC_SR_HT_POS)
#define ADC_SR_HT ADC_SR_HT_MASK
#define ADC_SR_LT_POS 1
#define ADC_SR_LT_MASK (0x01UL<<ADC_SR_LT_POS)
#define ADC_SR_LT ADC_SR_LT_MASK
#define ADC_SR_SGL_POS 0
#define ADC_SR_SGL_MASK (0x01UL<<ADC_SR_SGL_POS)
#define ADC_SR_SGL ADC_SR_SGL_MASK
//===清除中断标志
#define ADC_CSR_JQR_POS 5
#define ADC_CSR_JQR_MASK (0x01UL<<ADC_CSR_JQR_POS)
#define ADC_CSR_JQR ADC_CSR_JQR_MASK
#define ADC_CSR_SQR_POS 4
#define ADC_CSR_SQR_MASK (0x01UL<<ADC_CSR_SQR_POS)
#define ADC_CSR_SQR ADC_CSR_SQR_MASK
#define ADC_CSR_CMP_POS 3
#define ADC_CSR_CMP_MASK (0x01UL<<ADC_CSR_CMP_POS)
#define ADC_CSR_CMP ADC_CSR_CMP_MASK
#define ADC_CSR_HT_POS 2
#define ADC_CSR_HT_MASK (0x01UL<<ADC_CSR_HT_POS)
#define ADC_CSR_HT ADC_CSR_HT_MASK
#define ADC_CSR_LT_POS 1
#define ADC_CSR_LT_MASK (0x01UL<<ADC_CSR_LT_POS)
#define ADC_CSR_LT ADC_CSR_LT_MASK
#define ADC_CSR_SGL_POS 0
#define ADC_CSR_SGL_MASK (0x01UL<<ADC_CSR_SGL_POS)
#define ADC_CSR_SGL ADC_CSR_SGL_MASK
//===单次转换启动
#define ADC_SGL_START_POS 0
#define ADC_SGL_START_MASK (0x01UL<<ADC_SGL_START_POS)
#define ADC_SGL_START ADC_SGL_START_MASK
//===顺序转换启动
#define ADC_SQR_START_POS 0
#define ADC_SQR_START_MASK (0x01UL<<ADC_SQR_START_POS)
#define ADC_SQR_START ADC_SQR_START_MASK
//===插队转换启动
#define ADC_JQR_START_POS 0
#define ADC_JQR_START_MASK (0x01UL<<ADC_JQR_START_POS)
#define ADC_JQR_START ADC_JQR_START_MASK
//===全部转换启动
#define ADC_ALL_START_POS 0
#define ADC_ALL_START_MASK (0x01UL<<ADC_ALL_START_POS)
#define ADC_ALL_START ADC_ALL_START_MASK
#pragma endregion
#pragma region VC
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR; //---控制寄存器1
__IO uint32_t CR0; //---控制寄存器1
__IO uint32_t CR1; //---控制寄存器1
__IO uint32_t OUT0; //---控制寄存器1
__IO uint32_t OUT1; //---控制寄存器1
__IO uint32_t SR; //---控制寄存器1
uint32_t RESERVED[75]; //---保留字节
__IO uint32_t CR2; //---控制寄存器1
__IO uint32_t OUT2; //---控制寄存器1
} VC_TypeDef;
#pragma endregion
#pragma region BGR
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR; //---配置寄存器
} BGR_TypeDef;
//===内部温度传感器使能控制
#define BGR_TS_EN_POS 1
#define BGR_TS_EN_MASK (0x01UL<<BGR_TS_EN_POS)
#define BGR_TS_EN BGR_TS_EN_MASK
//===BGA使能控制
#define BGR_CR_EN_POS 0
#define BGR_CR_EN_MASK (0x01UL<<BGR_CR_EN_POS)
#define BGR_CR_EN BGR_CR_EN_MASK
#pragma endregion
#pragma region PCNT
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t RUN; //---控制寄存器1
__IO uint32_t CTRL; //---控制寄存器1
__IO uint32_t FLT; //---控制寄存器1
__IO uint32_t TOCR; //---控制寄存器1
__IO uint32_t CMD; //---控制寄存器1
__IO uint32_t SR1; //---控制寄存器1
__IO uint32_t CNT; //---控制寄存器1
__IO uint32_t TOP; //---控制寄存器1
__IO uint32_t BUF; //---控制寄存器1
__IO uint32_t SR; //---控制寄存器1
__IO uint32_t CSR; //---控制寄存器1
__IO uint32_t IEN; //---控制寄存器1
__IO uint32_t SR2; //---控制寄存器1
__IO uint32_t DBG; //---控制寄存器1
} PCNT_TypeDef;
#pragma endregion
#pragma region LCD
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR0; //---控制寄存器1
__IO uint32_t CR1; //---控制寄存器1
__IO uint32_t CSR; //---控制寄存器1
__IO uint32_t P0EN0; //---控制寄存器1
__IO uint32_t P0EN1; //---控制寄存器1 10
uint32_t RESERVED2[11]; //---保留字节 14 18 1C 20 24 28 2C 30 34 38 3C
__IO uint32_t RAM0; //---控制寄存器1
__IO uint32_t RAM1; //---控制寄存器1
__IO uint32_t RAM2; //---控制寄存器1
__IO uint32_t RAM3; //---控制寄存器1
__IO uint32_t RAM4; //---控制寄存器1
__IO uint32_t RAM5; //---控制寄存器1
__IO uint32_t RAM6; //---控制寄存器1
__IO uint32_t RAM7; //---控制寄存器1
__IO uint32_t RAM8; //---控制寄存器1
__IO uint32_t RAM9; //---控制寄存器1
__IO uint32_t RAMA; //---控制寄存器1
__IO uint32_t RAMB; //---控制寄存器1
__IO uint32_t RAMC; //---控制寄存器1
__IO uint32_t RAMD; //---控制寄存器1
__IO uint32_t RAME; //---控制寄存器1
__IO uint32_t RAMF; //---控制寄存器1
} LCD_TypeDef;
#pragma endregion
#pragma region AES
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR; //---控制寄存器 0x00
uint32_t RESERVED[3]; //---保留字节 04 08 0C
__IO uint32_t DR[4]; //---数据寄存器 10 14 18 1C
__IO uint32_t KEY[8]; //---秘钥寄存器 20 24 28 2C 30 34 38 3C
} AES_TypeDef;
#define AES_CR_KEYSIZE_POS 3
#define AES_CR_KEYSIZE_MASK (0x03UL<<AES_CR_KEYSIZE_POS)
#define AES_CR_KEYSIZE AES_CR_KEYSIZE_MASK
#define AES_CR_KEYSIZE_128 (0x00UL<<AES_CR_KEYSIZE_POS)
#define AES_CR_KEYSIZE_192 (0x01UL<<AES_CR_KEYSIZE_POS)
#define AES_CR_KEYSIZE_256 (0x02UL<<AES_CR_KEYSIZE_POS)
#define AES_CR_MODE_POS 1
#define AES_CR_MODE_MASK (0x01UL<<AES_CR_MODE_POS)
#define AES_CR_MODE AES_CR_MODE_MASK
#define AES_CR_START_POS 0
#define AES_CR_START_MASK (0x01UL<<AES_CR_START_POS)
#define AES_CR_START AES_CR_START_MASK
#define AES_DR_DATA_POS 0
#define AES_DR_DATA_MASK (0xFFFFFFFFUL<<AES_DR_DATA_POS)
#define AES_DR_DATA AES_DR_DATA_MASK
#define AES_KEY_KEY_POS 0
#define AES_KEY_KEY_MASK (0xFFFFFFFFUL<<AES_KEY_KEY_POS)
#define AES_KEY_KEY AES_KEY_KEY_MASK
#pragma endregion
#pragma region DAC
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR; //---控制寄存器1
__IO uint32_t SWTR; //---控制寄存器1
__IO uint32_t DHR12R0; //---控制寄存器1
__IO uint32_t DHR12L0; //---控制寄存器1
__IO uint32_t DHR8R0; //---控制寄存器1 10 1C 18 1C 20 24 28
uint32_t RESERVED1[6]; //---保留字节 2C
__IO uint32_t DOR; //---控制寄存器1
uint32_t RESERVED2; //---保留字节
__IO uint32_t SR; //---控制寄存器1
__IO uint32_t ETRS; //---控制寄存器1
} DAC_TypeDef;
//===DAC参考电压选择
#define DAC_CR_SREF_POS 14
#define DAC_CR_SREF_MASK (0x03UL<<DAC_CR_SREF_POS)
#define DAC_CR_SREF DAC_CR_SREF_MASK
#define DAC_CR_DMAIE_POS 13
#define DAC_CR_DMAIE_MASK (0x01UL<<DAC_CR_DMAIE_POS)
#define DAC_CR_DMAIE DAC_CR_DMAIE_MASK
#define DAC_CR_DMAEN_POS 12
#define DAC_CR_DMAEN_MASK (0x01UL<<DAC_CR_DMAIE_POS)
#define DAC_CR_DMAEN DAC_CR_DMAIE_MASK
#define DAC_CR_WAVE_POS 6
#define DAC_CR_WAVE_MASK (0x03UL<<DAC_CR_DMAIE_POS)
#define DAC_CR_WAVE DAC_CR_DMAIE_MASK
#define DAC_CR_TRIGSEL_POS 3
#define DAC_CR_TRIGSEL_MASK (0x07UL<<DAC_CR_DMAIE_POS)
#define DAC_CR_TRIGSEL DAC_CR_DMAIE_MASK
#define DAC_CR_TRIGEN_POS 2
#define DAC_CR_TRIGEN_MASK (0x07UL<<DAC_CR_DMAIE_POS)
#define DAC_CR_TRIGEN DAC_CR_DMAIE_MASK
#define DAC_CR_BUFFER_POS 1
#define DAC_CR_BUFFER_MASK (0x01UL<<DAC_CR_DMAIE_POS)
#define DAC_CR_BUFFER DAC_CR_DMAIE_MASK
#define DAC_CR_EN_POS 0
#define DAC_CR_EN_MASK (0x01UL<<DAC_CR_DMAIE_POS)
#define DAC_CR_EN DAC_CR_DMAIE_MASK
//===端口触发选择
#define DAC_ETRS_TRIGSEL_POS 4
#define DAC_ETRS_TRIGSEL_MASK (0x07UL<<DAC_CR_DMAIE_POS)
#define DAC_ETRS_TRIGSEL DAC_CR_DMAIE_MASK
#pragma endregion
#pragma region LVD
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CR; //---配置寄存器
__IO uint32_t SR; //---状态寄存器
} LVD_TypeDef;
//===LVD中断使能控制
#define LVD_CR_IE_POS 15
#define LVD_CR_IE_MASK (0x01UL<<LVD_CR_IE_POS)
#define LVD_CR_IE LVD_CR_IE_MASK
//===LVD触发方式
#define LVD_CR_HT_POS 14
#define LVD_CR_HT_MASK (0x01UL<<LVD_CR_HT_POS)
#define LVD_CR_HT LVD_CR_HT_MASK
//===LVD触发方式
#define LVD_CR_RT_POS 13
#define LVD_CR_RT_MASK (0x01UL<<LVD_CR_RT_POS)
#define LVD_CR_RT LVD_CR_RT_MASK
//===LVD触发方式
#define LVD_CR_FT_POS 12
#define LVD_CR_FT_MASK (0x01UL<<LVD_CR_FT_POS)
#define LVD_CR_FT LVD_CR_FT_MASK
//===LVD中断触发方式
#define LVD_CR_IRQ_POS 12
#define LVD_CR_IRQ_MASK (0x07UL<<LVD_CR_IRQ_POS)
#define LVD_CR_IRQ LVD_CR_IRQ_MASK
//===数字滤波时间
#define LVD_CR_FITLER_TIME_POS 9
#define LVD_CR_FITLER_TIME_MASK (0x07UL<<LVD_CR_FITLER_TIME_POS)
#define LVD_CR_FITLER_TIME LVD_CR_FITLER_TIME_MASK
#define LVD_CR_FITLER_US_7 (0x00UL<<LVD_CR_FITLER_TIME_POS)
#define LVD_CR_FITLER_US_14 (0x01UL<<LVD_CR_FITLER_TIME_POS)
#define LVD_CR_FITLER_US_28 (0x02UL<<LVD_CR_FITLER_TIME_POS)
#define LVD_CR_FITLER_US_112 (0x03UL<<LVD_CR_FITLER_TIME_POS)
#define LVD_CR_FITLER_US_450 (0x04UL<<LVD_CR_FITLER_TIME_POS)
#define LVD_CR_FITLER_US_1800 (0x05UL<<LVD_CR_FITLER_TIME_POS)
#define LVD_CR_FITLER_US_7200 (0x06UL<<LVD_CR_FITLER_TIME_POS)
#define LVD_CR_FITLER_US_28800 (0x07UL<<LVD_CR_FITLER_TIME_POS)
//===数字滤波使能配置
#define LVD_CR_FITLER_EN_POS 8
#define LVD_CR_FITLER_EN_MASK (0x07UL<<LVD_CR_FITLER_EN_POS)
#define LVD_CR_FITLER_EN LVD_CR_FITLER_EN_MASK
//===LVD阈值电压选择
#define LVD_CR_LVDS_POS 4
#define LVD_CR_LVDS_MASK (0x0FUL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS LVD_CR_LVDS_MASK
#define LVD_CR_LVDS_V_1P8 (0x00UL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_1P9 (0x01UL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_2P0 (0x02UL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_2P1 (0x03UL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_2P2 (0x04UL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_2P3 (0x05UL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_2P4 (0x06UL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_2P5 (0x07UL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_2P6 (0x08UL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_2P7 (0x09UL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_2P8 (0x0AUL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_2P9 (0x0BUL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_3P0 (0x0CUL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_3P1 (0x0DUL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_3P2 (0x0EUL<<LVD_CR_LVDS_POS)
#define LVD_CR_LVDS_V_3P3 (0x0FUL<<LVD_CR_LVDS_POS)
//===LVD监测来源
#define LVD_CR_SOURCE_POS 2
#define LVD_CR_SOURCE_MASK (0x03UL<<LVD_CR_SOURCE_POS)
#define LVD_CR_SOURCE LVD_CR_SOURCE_MASK
#define LVD_CR_SOURCE_PB07 (0x03UL<<LVD_CR_SOURCE_POS)
#define LVD_CR_SOURCE_PB08 (0x02UL<<LVD_CR_SOURCE_POS)
#define LVD_CR_SOURCE_PC13 (0x01UL<<LVD_CR_SOURCE_POS)
#define LVD_CR_SOURCE_AVCC (0x00UL<<LVD_CR_SOURCE_POS)
//===LVD触发动作选择
#define LVD_CR_ACT_POS 1
#define LVD_CR_ACT_MASK (0x01UL<<LVD_CR_ACT_POS)
#define LVD_CR_ACT LVD_CR_ACT_MASK
#define LVD_CR_ACT_RESET LVD_CR_ACT
#define LVD_CR_ACT_NVIC (~LVD_CR_ACT)
//===LVD使能控制
#define LVD_CR_EN_POS 0
#define LVD_CR_EN_MASK (0x01UL<<LVD_CR_EN_POS)
#define LVD_CR_EN LVD_CR_EN_MASK
//===中断标志
#define LVD_SR_INTF_POS 0
#define LVD_SR_INTF_MASK (0x01UL<<LVD_SR_INTF_POS)
#define LVD_SR_INTF LVD_SR_INTF_MASK
#pragma endregion
#pragma region DMA
//===端口通用功能配置寄存器
typedef struct
{
__IO uint32_t CONF; //---配置寄存器
__IO uint32_t CONFA0; //---状态寄存器
__IO uint32_t CONFB0; //---状态寄存器
__IO uint32_t SRCADR0; //---状态寄存器
__IO uint32_t DSTADR0; //---状态寄存器
__IO uint32_t CONFA1; //---状态寄存器
__IO uint32_t CONFB1; //---状态寄存器
__IO uint32_t SRCADR1; //---状态寄存器
__IO uint32_t DSTADR1; //---状态寄存器
} DMA_TypeDef;
#pragma endregion
#define FLASH_BASE 0x00000000U
#define FLASH_END 0x0001FFFFU
#define FLASH_BANK1_END 0x0001FFFFU
#define SRAM_BASE 0x20000000U
#define SRAM_ENDsss 0x20003FFFU
#define PERIPH_BASE 0x40000000U
//#define SRAM_BB_BASE 0x22000000U
//#define PERIPH_BB_BASE 0x42000000U
#define DBGMCU_BASE 0x04002038U
#define GPIO_SEL_OFFSET (0x100/4)
//===产品身份标识
#define UID_BASE 0x00100E74U
//===产品型号
#define PID_BASE 0x00100C60U
//===Flash容量
#define FLASH_SIZE_BASE 0x00100C70U
//===SRAM容量
#define SRAM_SIZE_BASE 0x00100C74U
//===引脚数量
#define PIN_NUM_BASE 0x00100C7AU
//===总线基地址
#define APB0PERIPH_BASE PERIPH_BASE
#define APB1PERIPH_BASE (PERIPH_BASE + 0x00004000U)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
//===外设基地址
#define UART0_BASE (APB0PERIPH_BASE + 0x00000000U)
#define UART1_BASE (APB0PERIPH_BASE + 0x00000100U)
#define LPUART0_BASE (APB0PERIPH_BASE + 0x00000200U)
#define I2C0_BASE (APB0PERIPH_BASE + 0x00000400U)
#define SPI0_BASE (APB0PERIPH_BASE + 0x00000800U)
#define TIM0_BASE (APB0PERIPH_BASE + 0x00000C00U)
#define TIM1_BASE (APB0PERIPH_BASE + 0x00000D00U)
#define TIM2_BASE (APB0PERIPH_BASE + 0x00000E00U)
#define LPTIM0_BASE (APB0PERIPH_BASE + 0x00000F00U)
#define LPTIM1_BASE (APB0PERIPH_BASE + 0x00000F40U)
#define WDT_BASE (APB0PERIPH_BASE + 0x00000F80U)
#define PCA_BASE (APB0PERIPH_BASE + 0x00001000U)
#define RTC_BASE (APB0PERIPH_BASE + 0x00001400U)
//===时钟校准
#define TRIM_BASE (APB0PERIPH_BASE + 0x00001800U)
#define RCC_BASE (APB0PERIPH_BASE + 0x00002000U)
#define BGR_BASE (APB0PERIPH_BASE + 0x00002400U)
#define ADC0_BASE (APB0PERIPH_BASE + 0x00002404U)
#define ADC_BASE (APB0PERIPH_BASE + 0x00002404U)
#define VC_BASE (APB0PERIPH_BASE + 0x00002410U)
#define OPA_BASE (APB0PERIPH_BASE + 0x00002430U)
#define LVD_BASE (APB0PERIPH_BASE + 0x00002428U)
#define DAC0_BASE (APB0PERIPH_BASE + 0x00002500U)
#define DAC_BASE (APB0PERIPH_BASE + 0x00002500U)
#define TIMP4_BASE (APB0PERIPH_BASE + 0x00003000U)
#define TIMP5_BASE (APB0PERIPH_BASE + 0x00003400U)
#define TIMP6_BASE (APB0PERIPH_BASE + 0x00003800U)
#define LPUART1_BASE (APB0PERIPH_BASE + 0x00004000U)
#define I2C1_BASE (APB0PERIPH_BASE + 0x00004400U)
#define SPI1_BASE (APB0PERIPH_BASE + 0x00004800U)
#define RNG_BASE (APB0PERIPH_BASE + 0x00004C00U)
#define PCNT_BASE (APB0PERIPH_BASE + 0x00005400U)
#define TIM3_BASE (APB0PERIPH_BASE + 0x00005800U)
#define LCD_BASE (APB0PERIPH_BASE + 0x00005C00U)
#define UART2_BASE (APB0PERIPH_BASE + 0x00006000U)
#define UART3_BASE (APB0PERIPH_BASE + 0x00006400U)
#define FLASH_CTR_BASE (APB0PERIPH_BASE + 0x00020000U)
#define RAM_CTR_BASE (APB0PERIPH_BASE + 0x00020400U)
#define CRC_BASE (APB0PERIPH_BASE + 0x00020900U)
#define DMAC_BASE (APB0PERIPH_BASE + 0x00021000U)
#define AES_BASE (APB0PERIPH_BASE + 0x00021400U)
//===端口功能选择寄存器
#define GPIOA_AF_BASE (APB0PERIPH_BASE + 0x00020C00U)
#define GPIOB_SEL_BASE (APB0PERIPH_BASE + 0x00020C40U)
#define GPIOC_SEL_BASE (APB0PERIPH_BASE + 0x00020C80U)
#define GPIOD_SEL_BASE (APB0PERIPH_BASE + 0x00020CC0U)
#define GPIOE_SEL_BASE (APB0PERIPH_BASE + 0x00021C00U)
#define GPIOF_SEL_BASE (APB0PERIPH_BASE + 0x00021C40U)
//===端口特殊功能，辅助功能寄存器
#define GPIO_AF_BASE (APB0PERIPH_BASE + 0x00020F04U)
//===端口通用寄存器
#define GPIOA_BASE (APB0PERIPH_BASE + 0x00020D00U)
#define GPIOB_BASE (APB0PERIPH_BASE + 0x00020D40U)
#define GPIOC_BASE (APB0PERIPH_BASE + 0x00020D80U)
#define GPIOD_BASE (APB0PERIPH_BASE + 0x00020DC0U)
#define GPIOE_BASE (APB0PERIPH_BASE + 0x00021D00U)
#define GPIOF_BASE (APB0PERIPH_BASE + 0x00021D40U)
#define GPIOA_AF_BASE (APB0PERIPH_BASE + 0x00020C00U)
#define GPIOB_AF_BASE (APB0PERIPH_BASE + 0x00020C40U)
#define GPIOC_AF_BASE (APB0PERIPH_BASE + 0x00020C80U)
#define GPIOD_AF_BASE (APB0PERIPH_BASE + 0x00020CC0U)
#define GPIOE_AF_BASE (APB0PERIPH_BASE + 0x00020CA0U)
#define GPIOF_AF_BASE (APB0PERIPH_BASE + 0x00020CC0U)
#define GPIO_SUB_BASE (APB0PERIPH_BASE + 0x00020F04U)
//===端口中断配置寄存器
#define EXITA_BASE (APB0PERIPH_BASE + 0x00020D30U)
#define EXITB_BASE (APB0PERIPH_BASE + 0x00020D70U)
#define EXITC_BASE (APB0PERIPH_BASE + 0x00020DB0U)
#define EXITD_BASE (APB0PERIPH_BASE + 0x00020DF0U)
#define EXITE_BASE (APB0PERIPH_BASE + 0x00021D30U)
#define EXITF_BASE (APB0PERIPH_BASE + 0x00021D70U)
//===定义端口功能
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIO_SELA ((GPIO_AF_TypeDef *) GPIOA_AF_BASE)
#define GPIO_SELB ((GPIO_AF_TypeDef *) GPIOB_AF_BASE)
#define GPIO_SELC ((GPIO_AF_TypeDef *) GPIOC_AF_BASE)
#define GPIO_SELD ((GPIO_AF_TypeDef *) GPIOD_AF_BASE)
#define GPIO_SELE ((GPIO_AF_TypeDef *) GPIOE_AF_BASE)
#define GPIO_SELF ((GPIO_AF_TypeDef *) GPIOF_AF_BASE)
#define GPIO_SUB ((GPIO_Sub_TypeDef *) GPIO_SUB_BASE)
#define EXITA ((EXIT_TypeDef *) EXITA_BASE)
#define EXITB ((EXIT_TypeDef *) EXITB_BASE)
#define EXITC ((EXIT_TypeDef *) EXITC_BASE)
#define EXITD ((EXIT_TypeDef *) EXITD_BASE)
#define EXITE ((EXIT_TypeDef *) EXITE_BASE)
#define EXITF ((EXIT_TypeDef *) EXITF_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_CTR_BASE)
#define RAM ((RAM_TypeDef *) RAM_CTR_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define SPI0 ((SPI_TypeDef *) SPI0_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define UART0 ((USART_TypeDef *) UART0_BASE)
#define UART1 ((USART_TypeDef *) UART1_BASE)
#define UART2 ((USART_TypeDef *) UART2_BASE)
#define UART3 ((USART_TypeDef *) UART3_BASE)
#define LPUART0 ((LPUSART_TypeDef *) LPUART0_BASE)
#define LPUART1 ((LPUSART_TypeDef *) LPUART1_BASE)
#define LPTIM0 ((LPTIM_TypeDef *) LPTIM0_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define TRIM ((TRIM_TypeDef *) TRIM_BASE)
#define TIM0 ((TIM_TypeDef *) TIM0_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM0_M0 ((TIM_M0_TypeDef *) TIM0_BASE)
#define TIM1_M0 ((TIM_M0_TypeDef *) TIM1_BASE)
#define TIM2_M0 ((TIM_M0_TypeDef *) TIM2_BASE)
#define TIM3_M0 ((TIM_M0_TypeDef *) TIM3_BASE)
#define TIM0_M1 ((TIM_M1_TypeDef *) TIM0_BASE)
#define TIM1_M1 ((TIM_M1_TypeDef *) TIM1_BASE)
#define TIM2_M1 ((TIM_M1_TypeDef *) TIM2_BASE)
#define TIM3_M1 ((TIM_M1_TypeDef *) TIM3_BASE)
#define TIM0_M2 ((TIM_M2_TypeDef *) TIM0_BASE)
#define TIM1_M2 ((TIM_M2_TypeDef *) TIM1_BASE)
#define TIM2_M2 ((TIM_M2_TypeDef *) TIM2_BASE)
#define TIM3_M2 ((TIM_M2_TypeDef *) TIM3_BASE)
#define TIM0_M3 ((TIM_M3_TypeDef *) TIM0_BASE)
#define TIM1_M3 ((TIM_M3_TypeDef *) TIM1_BASE)
#define TIM2_M3 ((TIM_M3_TypeDef *) TIM2_BASE)
#define TIM3_M3 ((TIM_M3_TypeDef *) TIM3_BASE)
#define TIMP4 ((TIMP_TypeDef *) TIMP4_BASE)
#define TIMP5 ((TIMP_TypeDef *) TIMP5_BASE)
#define TIMP6 ((TIMP_TypeDef *) TIMP6_BASE)
#define OPA ((OPA_TypeDef *) OPA_BASE)
#define PCA ((PCA_TypeDef *) PCA_BASE)
#define WDT ((WDT_TypeDef *) WDT_BASE)
#define IWDG ((IWDG_TypeDef *) WDT_BASE)
#define BGR ((BGR_TypeDef *)BGR_BASE)
#define ADC0 ((ADC_TypeDef *) ADC0_BASE)
#define ADC ((ADC_TypeDef *) ADC_BASE)
#define DAC0 ((DAC_TypeDef *) DAC0_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define VC ((VC_TypeDef *) VC_BASE)
#define PCNT ((PCNT_TypeDef *) PCNT_BASE)
#define LCD ((LCD_TypeDef *) LCD_BASE)
#define AES ((AES_TypeDef *) AES_BASE)
#define LVD ((LVD_TypeDef *) LVD_BASE)
#define DMA ((DMA_TypeDef *) DMAC_BASE)
///
#ifdef __cplusplus
}
#endif
#endif /* HC32L17XA_H */
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