Computer composition and design work09 ——fifth verson

5.12.1-2

In this exercise, we will examine space/time optimizations for page tables. The following list provides parameters of a virtual memory system.

Virtual Address (bits)	Physical DRAM Installed	Page Size	PTE Size (byte)
43	16 GiB	4 KiB	4

5.12.1 [10] <§5.7> For a single-level page table, how many page table entries (PTEs) are needed? How much physical memory is needed for storing the page table?

最坏的情况是 $2^{43-12}$页表项，所以需要$2^{43-12}\times 4byte=2^{3}3=8GB$

5.12.2 [10] <§5.7> Using a multilevel page table can reduce the physical memory consumption of page tables, by only keeping active PTEs in physical memory. How many levels of page tables will be needed in this case? And how many memory references are needed for address translation if missing in TLB?

若页表只有只有两个级别的话，可以自行设置每个页表段的大小。
而如果设计成多级，读取PTE需要依次访问表的每一个级

5.12.4-6

Th e following table shows the contents of a 4-entry TLB.

Entry-ID	Valid	VA Page	Modifi ed	Protection	PA Page
1	1	140	1	RW	30
2	0	40	0	RX	34
3	1	200	1	RO	32
4	1	280	0	RW	31

5.12.4 [5] <§5.7> Under what scenarios would entry 2’s valid bit be set to zero?

如果将其调出到磁盘，则无效（设置为0）

5.12.5 [5] <§5.7> What happens when an instruction writes to VA page 30? When would a soft ware managed TLB be faster than a hardware managed TLB?

写入第30页会导致TLB失效。
如果软件可以预取TLB条目，软件管理的TLB速度更快

5.12.6 [5] <§5.7> What happens when an instruction writes to VA page 200?

由于该页标记为只读。当N指令写入VA第200页时，将生成中断，

5.13.1

In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may fi nd it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.”

Address of MemoryBlock Accessed	Hit or Miss	Evicted Block	Set 0	Set 0	Set 1	Set 1
0	Miss		Mem[0]
1	Miss		Mem[0]		Mem[1]
2	Miss		Mem[0]	Mem[2]	Mem[1]
3	Miss		Mem[0]	Mem[2]	Mem[1]	Mem[3]
4	Miss	0	Mem[4]	Mem[2]	Mem[1]	Mem[3

Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 16, 0

5.13.1 [5] <§§5.4, 5.8> Assuming an LRU replacement policy, how many hits does this address sequence exhibit?

0 hits

5.13.3-5

5.13.3 [5] <§§5.4, 5.8> Simulate a random replacement policy by fl ipping a coin. For example, “heads” means to evict the fi rst block in a set and “tails” means to evict the second block in a set. How many hits does this address sequence exhibit?

1 hit或者更少

5.13.4 [10] <§§5.4, 5.8> Which address should be evicted at each replacement to maximize the number of hits? How many hits does this address sequence exhibit if you follow this “optimal” policy?

1 hit 只要点击次数正确，任何地址序列都可以

5.13.5 [10] <§§5.4, 5.8> Describe why it is diffi cult to implement a cache replacement policy that is optimal for all address sequences.

要驱逐的最佳区块是将来造成最少未命中的区块。然而，cache控制器无法预知未来，最好的选择是做出“优秀”的预测