接到客户一个项目是基本GD32F301C8XX的,尝试用手上的劳特巴赫仿真器对它进行开发操作,发现总是提示“FLASH algorithm did not execute completely”
怀疑是底层调用用烧录固件“~~/demo/arm/flash/word/stm32f300.bin”与芯片不兼容造成的,于是有了这编研究文档,多的不说直接上代码吧,具体的操作,请自行查代码理解。另外发了一篇C语言版本的在付费专栏
以下是反汇编代码
;-------------------------------------------------------------------------------
;---- DISASSEMBLE INFORMATION :
;---- File Name: ~~/demo/arm/flash/word/stm32f300.bin
;---- CPU Family: ARM
;---- CPU Factory: STM
;---- CPU Model: STM32F300C8
;---- Time Stamp: 621073228816300
;----
;---- Writen by: beacon_light@163.com
;---- Wechat: JingtongACT
;---- QQ: 351217023
;-------------------------------------------------------------------------------
AREA ROM, CODE, READWRITE, ALIGN=0
CODE16
; =========================================================
reset_0
PUSH {R4,LR}
LDR R1, [R0,#0x1C]
CMP R1, #1
BEQ ll_C
CMP R1, #0x21 ; '!'
BNE ll_12
ll_C
BL respond_program_60
POP {R4,PC}
ll_12
CMP R1, #2
BEQ ll_1A
CMP R1, #0x22 ; '"'
BNE ll_20
ll_1A
BL respond_erase_page_FE
POP {R4,PC}
ll_20
CMP R1, #5
BEQ ll_28
CMP R1, #0x25 ; '%'
BNE ll_2E
ll_28
BL respond_erase_chip_13A
POP {R4,PC}
ll_2E
CMP R1, #8
BNE ll_38
BL respond_unsuppond_1_174
POP {R4,PC}
ll_38
CMP R1, #9
BNE ll_42
BL respond_unsuppond_2_17A
POP {R4,PC}
ll_42
CMP R1, #0xA
BEQ ll_4A
CMP R1, #0xC
BNE ll_50
ll_4A
BL respond_verify_180
POP {R4,PC}
ll_50
CMP R1, #4
BNE ll_5A
BL respond_unsuppond_3_204
POP {R4,PC}
ll_5A
MOVS R1, #0x8D
STR R1, [R0,#0x1C]
POP {R4,PC}
; ====================================
respond_program_60
PUSH {R4-R7,LR}
MOVS R7, R0
MOVS R0, #0
SUB SP, SP, #0xC
STR R0, [SP,#8]
LDR R0, off_20C
LDR R0, [R0,#0x10]
MOVS R1, #0x80
ANDS R0, R1
STR R0, [SP,#4]
BL flash_unlock_246
MOVS R0, #0x35 ; '5'
BL set_flash_sts_670
LDR R4, [R7,#0x10]
LDR R5, [R7,#0x14]
MOVS R0, R4
ORRS R0, R5
MOVS R6, R7
LSLS R0, R0, #0x1E
ADDS R6, #0x20 ; ' '
CMP R0, #0
BEQ ll_BE
CMP R5, #0
BLE ll_EC
ll_94
LDRH R1, [R6]
MOVS R0, R4
BL program_word_34A
CMP R0, #4
BNE ll_A8
LDRH R1, [R4]
LDRH R2, [R6]
CMP R1, R2
BEQ ll_B2
ll_A8
MOVS R1, #0x68 ; 'h'
CMP R0, #2
BEQ ll_DC
ll_AE
MOVS R1, #0x64 ; 'd'
B ll_DC
ll_B2
ADDS R4, R4, #2
SUBS R5, R5, #2
ADDS R6, R6, #2
CMP R5, #0
BGT ll_94
B ll_EC
ll_BE
CMP R5, #0
BLE ll_EC
ll_C2
LDR R1, [R6]
MOVS R0, R4
BL program_off_30C
CMP R0, #4
BNE ll_D6
LDR R1, [R4]
LDR R2, [R6]
CMP R1, R2
BEQ ll_E2
ll_D6
MOVS R1, #0x68 ; 'h'
CMP R0, #2
BNE ll_AE
ll_DC
STR R1, [SP,#0x20+var_18]
STR R4, [R7,#0x10]
B ll_EC
ll_E2
ADDS R4, R4, #4
SUBS R5, R5, #4
ADDS R6, R6, #4
CMP R5, #0
BGT ll_C2
ll_EC
LDR R0, [SP,#0x20+var_1C]
CMP R0, #0
BEQ ll_F6
BL flash_lock_258
ll_F6
LDR R0, [SP,#0x20+var_18]
STR R0, [R7,#0x1C]
ADD SP, SP, #0xC
POP {R4-R7,PC}
; ====================================
respond_erase_page_FE
PUSH {R4-R6,LR}
MOVS R4, R0
LDR R0, off_20C
LDR R6, [R0,#0x10]
MOVS R0, #0x80
ANDS R6, R0
BL flash_unlock_246
MOVS R0, #0x35 ; '5'
BL set_flash_sts_670
LDR R0, [R4,#0x10]
BL erase_page_2A8
MOVS R5, R0
CMP R6, #0
BEQ ll_124
BL flash_lock_258
ll_124
CMP R5, #4
BNE ll_12E
MOVS R0, #0
STR R0, [R4,#0x1C]
POP {R4-R6,PC}
ll_12E
MOVS R1, #0x68 ; 'h'
CMP R5, #2
BEQ ll_136
MOVS R1, #0x65 ; 'e'
ll_136
STR R1, [R4,#0x1C]
POP {R4-R6,PC}
; ====================================
respond_erase_chip_13A
PUSH {R4-R6,LR}
MOVS R4, R0
LDR R0, off_20C
LDR R6, [R0,#0x10]
MOVS R0, #0x80
ANDS R6, R0
BL flash_unlock_246
MOVS R0, #0x35 ; '5'
BL set_flash_sts_670
BL erase_chip_2DC
MOVS R5, R0
CMP R6, #0
BEQ ll_15E
BL flash_lock_258
ll_15E
CMP R5, #4
BNE ll_168
MOVS R0, #0
STR R0, [R4,#0x1C]
POP {R4-R6,PC}
ll_168
MOVS R1, #0x68 ; 'h'
CMP R5, #2
BEQ ll_170
MOVS R1, #0x66 ; 'f'
ll_170
STR R1, [R4,#0x1C]
POP {R4-R6,PC}
; ====================================
respond_unsuppond_1_174
MOVS R1, #0x8D
STR R1, [R0,#0x1C]
BX LR
; ====================================
respond_unsuppond_2_17A
MOVS R1, #0x8D
STR R1, [R0,#0x1C]
BX LR
; ====================================
respond_verify_180
PUSH {R0,R4-R7,LR}
SUB SP, SP, #4
LDR R0, [SP,#4]
LDR R0, [R0,#0x18]
STR R0, [SP]
LDR R0, [SP,#4]
LDR R5, [R0,#0x10]
MOVS R2, R0
LDR R0, [SP]
ADDS R2, #0x20 ; ' '
CMP R0, #0
BLT ll_1FA
ll_198
MOVS R6, #0
LDR R0, [SP,#4]
MOVS R4, R6
LDR R3, [R0,#0x14]
MOVS R1, R6
CMP R3, #0
MOV R12, R6
MOV LR, R6
BEQ ll_1D6
ll_1AA
LDR R0, [R5]
ADDS R7, R0, #1
BEQ ll_1B4
MOVS R7, #1
MOV LR, R7
ll_1B4
MOV R7, R12
EORS R7, R0
MOV R12, R7
LSRS R7, R4, #0x1F
LSLS R4, R4, #1
ORRS R4, R7
ADDS R6, R6, R0
EORS R4, R0
CMP R7, #0
BEQ ll_1CE
LSRS R7, R1, #0x1F
LSLS R1, R1, #1
ORRS R1, R7
ll_1CE
ADDS R1, R1, R0
ADDS R5, R5, #4
SUBS R3, R3, #4
BNE ll_1AA
ll_1D6
MOVS R0, #0xB4
MOV R3, LR
CMP R3, #0
BEQ ll_1E0
MOVS R0, #0xB5
ll_1E0
STR R0, [R2]
MOVS R0, #1
ADDS R3, R2, #4
STM R3!, {R0,R6}
STR R4, [R2,#0x10]
MOV R0, R12
STR R1, [R2,#0x14]
STR R0, [R2,#0xC]
LDR R0, [SP]
ADDS R2, #0x18
SUBS R0, R0, #1
STR R0, [SP]
BPL ll_198
ll_1FA
LDR R0, [SP,#4]
MOVS R1, #0xB7
STR R1, [R0,#0x1C]
ADD SP, SP, #8
POP {R4-R7,PC}
; ====================================
respond_unsuppond_3_204
MOVS R1, #0x8D
STR R1, [R0,#0x1C]
BX LR
; ------------------------------------------------------
DCB 0
DCB 0
off_20C DCD 0x40022000
; ====================================
set_flash_delay_210
LDR R2, off_5FC
LDR R1, [R2]
LSRS R1, R1, #2
LSLS R1, R1, #2
ORRS R1, R0
STR R1, [R2]
BX LR
; ====================================
sub_21E
LDR R1, off_5FC
MOVS R2, #8
CMP R0, #0
LDR R0, [R1]
BEQ ll_22C
ORRS R0, R2
B ll_22E
ll_22C
BICS R0, R2
ll_22E
STR R0, [R1]
BX LR
; ====================================
set_preFlushBuffer_232
LDR R1, off_5FC
MOVS R2, #0x10
CMP R0, #0
LDR R0, [R1]
BEQ ll_240
ORRS R0, R2
B ll_242
ll_240
BICS R0, R2
ll_242
STR R0, [R1]
BX LR
; ====================================
flash_unlock_246
LDR R0, off_5FC
LDR R1, [R0,#0x10]
LSLS R1, R1, #0x18
BPL ll_256
LDR R1, off_600
STR R1, [R0,#4]
LDR R1, off_604
STR R1, [R0,#4]
ll_256
BX LR
; ====================================
flash_lock_258
LDR R0, off_5FC
LDR R1, [R0,#0x10]
MOVS R2, #0x80
ORRS R1, R2
STR R1, [R0,#0x10]
BX LR
; ====================================
test_flash_sts_264
LDR R1, off_5FC
MOVS R0, #4
LDR R2, [R1,#0xC]
LSLS R2, R2, #0x1F
BEQ ll_272
MOVS R0, #1
BX LR
ll_272
LDR R2, [R1,#0xC]
LSLS R2, R2, #0x1B
BPL ll_27C
MOVS R0, #2
ll_27A
BX LR
ll_27C
LDR R1, [R1,#0xC]
LSLS R1, R1, #0x1D
BPL ll_27A
MOVS R0, #3
BX LR
; ====================================
wait_flash_success_286
PUSH {LR}
MOVS R3, R0
BL test_flash_sts_264
B ll_296
ll_290
BL test_flash_sts_264
SUBS R3, R3, #1
ll_296
CMP R0, #1
BNE ll_2A0
CMP R3, #0
BNE ll_290
B ll_2A4
ll_2A0
CMP R3, #0
BNE ll_2A6
ll_2A4
MOVS R0, #5
ll_2A6
POP {PC}
; ====================================
erase_page_2A8
PUSH {R4-R7,LR}
MOVS R7, #0xB
MOVS R6, R0
LSLS R7, R7, #0x10
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_2DA
LDR R4, off_5FC
LDR R0, [R4,#0x10]
MOVS R5, #2
ORRS R0, R5
STR R0, [R4,#0x10]
STR R6, [R4,#0x14]
LDR R0, [R4,#0x10]
MOVS R1, #0x40 ; '@'
ORRS R0, R1
STR R0, [R4,#0x10]
MOVS R0, R7
BL wait_flash_success_286
LDR R1, [R4,#0x10]
BICS R1, R5
STR R1, [R4,#0x10]
ll_2DA
POP {R4-R7,PC}
; ====================================
erase_chip_2DC
PUSH {R4-R6,LR}
MOVS R5, #0xB0000
MOVS R0, R5
BL wait_flash_success_286
CMP R0, #4
BNE ll_30A
LDR R4, off_5FC
LDR R0, [R4,#0x10]
MOVS R6, #4
ORRS R0, R6
STR R0, [R4,#0x10]
LDR R0, [R4,#0x10]
MOVS R1, #0x40 ; '@'
ORRS R0, R1
STR R0, [R4,#0x10]
MOVS R0, R5
BL wait_flash_success_286
LDR R1, [R4,#0x10]
BICS R1, R6
STR R1, [R4,#0x10]
ll_30A
POP {R4-R6,PC}
; ====================================
program_off_30C
PUSH {R4-R7,LR}
MOVS R7, #0xB
MOVS R5, R0
LSLS R7, R7, #0x10
MOVS R6, R1
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_348
LDR R4, off_5FC
LDR R0, [R4,#0x10]
MOVS R1, #1
ORRS R0, R1
STR R0, [R4,#0x10]
STRH R6, [R5]
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_340
LSRS R0, R6, #0x10
STRH R0, [R5,#2]
MOVS R0, R7
BL wait_flash_success_286
ll_340
LDR R1, [R4,#0x10]
LSRS R1, R1, #1
LSLS R1, R1, #1
STR R1, [R4,#0x10]
ll_348
POP {R4-R7,PC}
; ====================================
program_word_34A
PUSH {R4-R7,LR}
MOVS R7, #0x0000000B
MOVS R5, R0
LSLS R7, R7, #0x10
MOVS R6, R1
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_378
LDR R4, off_5FC
LDR R0, [R4,#0x10]
MOVS R1, #1
ORRS R0, R1
STR R0, [R4,#0x10]
STRH R6, [R5]
MOVS R0, R7
BL wait_flash_success_286
LDR R1, [R4,#0x10]
LSRS R1, R1, #1
LSLS R1, R1, #1
STR R1, [R4,#0x10]
ll_378
POP {R4-R7,PC}
; ====================================
flash_unlock_37A
LDR R0, off_5FC
LDR R1, [R0,#0x10]
LSLS R1, R1, #0x16
BMI ll_38A
LDR R1, off_600
STR R1, [R0,#8]
LDR R1, off_604
STR R1, [R0,#8]
ll_38A
BX LR
; ====================================
flash_lock_option_38C
LDR R1, off_5FC
LDR R0, [R1,#0x10]
ASRS R2, R1, #0x15
BICS R0, R2
STR R0, [R1,#0x10]
BX LR
; ====================================
sub_398
LDR R0, off_5FC
LDR R1, [R0,#0x10]
MOVS R2, #0x2000
ORRS R1, R2
STR R1, [R0,#0x10]
BX LR
; ====================================
check_rdp1_statu_3A6
LDR R1, off_5FC
MOVS R0, #0
LDR R1, [R1,#0x1C]
LSLS R1, R1, #0x1D
LSRS R1, R1, #0x1E
BEQ ll_3B4
MOVS R0, #1
ll_3B4
BX LR
; ====================================
program_option_user_3B6
PUSH {R4-R7,LR}
MOVS R4, #0xAA
BL check_rdp1_statu_3A6
CMP R0, #0
BEQ ll_3C4
MOVS R4, #0
ll_3C4
MOVS R7, #0xB0000
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_412
LDR R5, off_5FC
LDR R0, [R5,#0x10]
MOVS R6, #0x20 ; ' '
ORRS R0, R6
STR R0, [R5,#0x10]
LDR R0, [R5,#0x10]
MOVS R1, #0x40 ; '@'
ORRS R0, R1
STR R0, [R5,#0x10]
MOVS R0, R7
BL wait_flash_success_286
MOVS R1, #0x10
CMP R0, #4
BNE ll_414
LDR R0, [R5,#0x10]
BICS R0, R6
STR R0, [R5,#0x10]
LDR R0, [R5,#0x10]
MOVS R6, R1
ORRS R0, R1
STR R0, [R5,#0x10]
LDR R0, off_608
STRH R4, [R0]
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #5
BEQ ll_412
LDR R1, [R5,#0x10]
BICS R1, R6
STR R1, [R5,#0x10]
ll_412
POP {R4-R7,PC}
ll_414
CMP R0, #5
BEQ ll_412
LDR R2, [R5,#0x10]
BICS R2, R1
STR R2, [R5,#0x10]
POP {R4-R7,PC}
; ====================================
write_option_wrpn_420
PUSH {R4-R7,LR}
MVNS R0, R0
LSLS R4, R0, #0x18
LSLS R0, R0, #0x10
LSRS R5, R0, #0x18
MOVS R0, #0xB
LSRS R4, R4, #0x18
LSLS R0, R0, #0x10
BL wait_flash_success_286
CMP R0, #4
BNE ll_470
LDR R6, off_5FC
LDR R1, [R6,#0x10]
MOVS R2, #0x10
ORRS R1, R2
STR R1, [R6,#0x10]
LDR R7, off_608
CMP R4, #0xFF
BEQ ll_456
STRH R4, [R7,#8]
MOVS R0, #0xB0000
BL wait_flash_success_286
CMP R0, #4
BNE ll_464
ll_456
CMP R5, #0xFF
BEQ ll_468
STRH R5, [R7,#0xA]
MOVS R0, #0xB0000
BL wait_flash_success_286
ll_464
CMP R0, #5
BEQ ll_470
ll_468
LDR R1, [R6,#0x10]
MOVS R2, #0x10
BICS R1, R2
STR R1, [R6,#0x10]
ll_470
POP {R4-R7,PC}
; ====================================
reprogram_option_472
PUSH {R4-R7,LR}
MOVS R7, #0xB
MOVS R6, R0
LSLS R7, R7, #0x10
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_4C2
LDR R4, off_5FC
LDR R0, [R4,#0x10]
MOVS R5, #0x20 ; ' '
ORRS R0, R5
STR R0, [R4,#0x10]
LDR R0, [R4,#0x10]
MOVS R1, #0x40 ; '@'
ORRS R0, R1
STR R0, [R4,#0x10]
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_4B8
LDR R0, [R4,#0x10]
BICS R0, R5
STR R0, [R4,#0x10]
LDR R0, [R4,#0x10]
MOVS R5, #0x10
ORRS R0, R5
STR R0, [R4,#0x10]
LDR R0, off_608
STRH R6, [R0]
MOVS R0, R7
BL wait_flash_success_286
ll_4B8
CMP R0, #5
BEQ ll_4C2
LDR R1, [R4,#0x10]
BICS R1, R5
STR R1, [R4,#0x10]
ll_4C2
POP {R4-R7,PC}
; ====================================
set_1ffff802_to_f8_4C4
PUSH {R4-R7,LR}
MOVS R6, R0
LDR R0, off_600
LDR R4, off_5FC
MOVS R7, R1
MOV R12, R2
STR R0, [R4,#8]
LDR R0, off_604
STR R0, [R4,#8]
MOVS R0, #0xB0000
BL wait_flash_success_286
CMP R0, #4
BNE ll_50A
LDR R0, [R4,#0x10]
MOVS R5, #0x10
ORRS R0, R5
STR R0, [R4,#0x10]
ORRS R6, R7
MOV R0, R12
ORRS R6, R0
MOVS R0, #0xF8
ORRS R6, R0
LDR R0, off_608
STRH R6, [R0,#2]
MOVS R0, #0xB0000
BL wait_flash_success_286
CMP R0, #5
BEQ ll_50A
LDR R1, [R4,#0x10]
BICS R1, R5
STR R1, [R4,#0x10]
ll_50A
POP {R4-R7,PC}
; ====================================
set_1ffff802_to_ef_50C
PUSH {R4-R7,LR}
MOVS R6, R0
LDR R0, off_600
LDR R4, off_5FC
STR R0, [R4,#8]
LDR R0, off_604
STR R0, [R4,#8]
MOVS R7, #0xB0000
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_548
LDR R0, [R4,#0x10]
MOVS R5, #0x10
ORRS R0, R5
STR R0, [R4,#0x10]
MOVS R0, #0xEF
ORRS R6, R0
LDR R0, off_608
STRH R6, [R0,#2]
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #5
BEQ ll_548
LDR R1, [R4,#0x10]
BICS R1, R5
STR R1, [R4,#0x10]
ll_548
POP {R4-R7,PC}
; ====================================
set_1ffff802_to_df_54A
PUSH {R4-R7,LR}
MOVS R6, R0
LDR R0, off_600
LDR R4, off_5FC
STR R0, [R4,#8]
LDR R0, off_604
STR R0, [R4,#8]
MOVS R7, #0xB0000
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_586
LDR R0, [R4,#0x10]
MOVS R5, #0x10
ORRS R0, R5
STR R0, [R4,#0x10]
MOVS R0, #0xDF
ORRS R6, R0
LDR R0, off_608
STRH R6, [R0,#2]
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #5
BEQ ll_586
LDR R1, [R4,#0x10]
BICS R1, R5
STR R1, [R4,#0x10]
ll_586
POP {R4-R7,PC}
; ====================================
write_option_user_to_bf_588
PUSH {R4-R7,LR}
MOVS R7, #0xB
MOVS R6, R0
LSLS R7, R7, #0x10
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_5BC
LDR R4, off_5FC
LDR R0, [R4,#0x10]
MOVS R5, #0x10
ORRS R0, R5
STR R0, [R4,#0x10]
MOVS R0, #0xBF
ORRS R6, R0
LDR R0, off_608
STRH R6, [R0,#2]
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #5
BEQ ll_5BC
LDR R1, [R4,#0x10]
BICS R1, R5
STR R1, [R4,#0x10]
ll_5BC
POP {R4-R7,PC}
; ====================================
write_option_user_to_88_5BE
PUSH {R4-R7,LR}
MOVS R6, R0
LDR R0, off_600
LDR R4, off_5FC
STR R0, [R4,#8]
LDR R0, off_604
STR R0, [R4,#8]
MOVS R7, #0xB0000
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #4
BNE ll_5FA
LDR R0, [R4,#0x10]
MOVS R5, #0x10
ORRS R0, R5
STR R0, [R4,#0x10]
MOVS R0, #0x88
ORRS R6, R0
LDR R0, off_608
STRH R6, [R0,#2]
MOVS R0, R7
BL wait_flash_success_286
CMP R0, #5
BEQ ll_5FA
LDR R1, [R4,#0x10]
BICS R1, R5
STR R1, [R4,#0x10]
ll_5FA
POP {R4-R7,PC}
; ------------------------------------------------------
off_5FC DCD 0x40022000
off_600 DCD 0x45670123
off_604 DCD 0xCDEF89AB
off_608 DCD 0x1FFFF800
; ====================================
write_option_byte_60C
PUSH {R4-R7,LR}
MOVS R6, R0
MOVS R0, #0xB
MOVS R7, R1
LSLS R0, R0, #0x10
BL wait_flash_success_286
CMP R0, #4
BNE ll_5FA
LDR R4, off_678
LDR R0, [R4,#0x10]
MOVS R5, #0x10
ORRS R0, R5
STR R0, [R4,#0x10]
STRH R7, [R6]
MOVS R0, #0xB0000
BL wait_flash_success_286
CMP R0, #5
BEQ ll_5FA
LDR R1, [R4,#0x10]
BICS R1, R5
STR R1, [R4,#0x10]
B ll_5FA
; ====================================
get_flash_ob_high_63E
LDR R0, off_678
LDR R0, [R0,#0x1C]
LSLS R0, R0, #0x10
LSRS R0, R0, #0x18
BX LR
; ====================================
get_flash_wrp_648
LDR R0, off_678
LDR R0, [R0,#0x20]
BX LR
; ====================================
update_flash_ctrll_64E
LDR R2, off_678
CMP R1, #0
LDR R1, [R2,#0x10]
BEQ ll_65A
ORRS R1, R0
B ll_65C
ll_65A
BICS R1, R0
ll_65C
STR R1, [R2,#0x10]
BX LR
; ====================================
test_flash_sts_660
LDR R1, off_678
MOVS R2, R0
LDR R1, [R1,#0xC]
MOVS R0, #0
TST R1, R2
BEQ ll_66E
MOVS R0, #1
ll_66E
BX LR
; ====================================
set_flash_sts_670
LDR R1, off_678
STR R0, [R1,#0xC]
BX LR
; ------------------------------------------------------
DCB 0
DCB 0
off_678 DCD 0x40022000
rightlight DCB "(C) Lauterbach - $Rev: 2382 $"
END