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相关结构体
typedef struct
{
uint32_t FSMC_Bank; //指定FSMC NOR/SRAM的存储区 块一的1~4区
uint32_t FSMC_DataAddressMux; //数据地址总线复用位设置
uint32_t FSMC_MemoryType; //存储器类型定义
uint32_t FSMC_MemoryDataWidth; //数据总线宽度
uint32_t FSMC_BurstAccessMode; //成组模式使能设置
uint32_t FSMC_AsynchronousWait; //手册中这一位保留
uint32_t FSMC_WaitSignalPolarity; //设置存储器产生的等待信号的极性
uint32_t FSMC_WrapMode; //支持非对齐的成组模式
uint32_t FSMC_WaitSignalActive; //配置等待时序
uint32_t FSMC_WriteOperation; //写使能
uint32_t FSMC_WaitSignal; //等待模式使能
uint32_t FSMC_ExtendedMode; //扩展模式使能
uint32_t FSMC_WriteBurst; //成组写使能位
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; //BTRx
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; //BWTRx
}FSMC_NORSRAMInitTypeDef;
typedef struct
{
uint32_t FSMC_AddressSetupTime; //地址建立时间 0~F
uint32_t FSMC_AddressHoldTime; //地址保持时间 0~F
uint32_t FSMC_DataSetupTime; //数据保持时间 0~FF
uint32_t FSMC_BusTurnAroundDuration; //总线恢复时间 0~F
uint32_t FSMC_CLKDivision; //时钟分频比(CLK信号)
uint32_t FSMC_DataLatency; //(同步成组式NOR闪存的)数据保持时间
uint32_t FSMC_AccessMode; //访问模式
}FSMC_NORSRAMTimingInitTypeDef;
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相关参数的结构体及宏定义
/**************FSMC_NORSRAMInit()函数结构体参数***********************/
/*FSMC_Bank bank1 区位寄存器选择参数*/
typedef struct
{
__IO uint32_t BTCR[8];
} FSMC_Bank1_TypeDef;
/*偏移 寄存器名称 复位值 说明
000h FSMC_BCR1 0x000030DB SRAM/NOR闪存片选控制寄存器 1
004h FSMC_BTR1 0x0FFFFFFF SRAM/NOR闪存片选时序寄存器 1
008h FSMC_BCR2 0x000030D2 SRAM/NOR闪存片选控制寄存器 2
00Ch FSMC_BTR2 0x0FFFFFFF SRAM/NOR闪存片选时序寄存器 2
010h FSMC_BCR3 0x000030D2 SRAM/NOR闪存片选控制寄存器 3
014h FSMC_BTR3 0x0FFFFFFF SRAM/NOR闪存片选时序寄存器 3
018h FSMC_BCR4 0x000030D2 SRAM/NOR闪存片选控制寄存器 4
01Ch FSMC_BTR4 0x0FFFFFFF SRAM/NOR闪存片选时序寄存器 4*/
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
/*FSMC_DataAddressMux 地址数据复用使能参数相关定义*/
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
((MUX) == FSMC_DataAddressMux_Enable))
/*FSMC_MemoryType 控制内存类型选择参数相关定义*/
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
((MEMORY) == FSMC_MemoryType_NOR))
/*FSMC_MemoryDataWidth 数据总线宽度相关参数定义*/
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/*FSMC_BurstAccessMode 成组模式使能位相关参数定义*/
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
((STATE) == FSMC_BurstAccessMode_Enable))
/*FSMC_WaitSignalPolarity 等待信号极性控制相关参数定义*/
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
((POLARITY) == FSMC_WaitSignalPolarity_High))
/*FSMC_WrapMode 非对其成组模式设置相关参数定义*/
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
((MODE) == FSMC_WrapMode_Enable))
/*FSMC_WaitSignalActive 配置等待时序相关参数定义*/
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
/*FSMC_WriteOperation 写使能位相关参数定义*/
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
((OPERATION) == FSMC_WriteOperation_Enable))
/*FSMC_WaitSignal 等待使能位设置相关参数定义*/
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
((SIGNAL) == FSMC_WaitSignal_Enable))
/*FSMC_ExtendedMode 扩展模式使能相关参数定义*/
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
((MODE) == FSMC_ExtendedMode_Enable))
/*FSMC_WriteBurst 成组写使能位相关参数设置*/
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
((BURST) == FSMC_WriteBurst_Enable))
/*地址建立时间*/
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
/*地址保持时间*/
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
/*数据保持时间*/
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
/*总线恢复时间*/
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
/*时钟分频比(CLK信号)*/
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
/*(同步成组式NOR闪存的)数据保持时间*/
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
/*访问模式 (Access mode)*/
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
((MODE) == FSMC_AccessMode_B) || \
((MODE) == FSMC_AccessMode_C) || \
((MODE) == FSMC_AccessMode_D))
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函数体
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* 检查参数*/
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
/*Bank1 NOR / SRAM 控制寄存器配置 BCRx */
/*根据FSMC_NORSRAMInitStruct->FSMC_Bank的值选择相应区的控制寄存器*/
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | /*数据地址总线复用设置 BCRx 1 */
FSMC_NORSRAMInitStruct->FSMC_MemoryType | /*控制内存类型设置 BCRx 3:2*/
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | /*选择数据总线宽度 BCRx 5:4*/
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | /*设置成组模式使能位 BCRx 8*/
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | /*手册中这一位保留*/
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | /*设置存储器产生的等待信号的极性 BCRx 9*/
FSMC_NORSRAMInitStruct->FSMC_WrapMode | /*支持非对齐的成组模式 BCRx 10*/
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | /*配置等待时序 BCRx 11*/
FSMC_NORSRAMInitStruct->FSMC_WriteOperation | /*写使能 BCRx 12*/
FSMC_NORSRAMInitStruct->FSMC_WaitSignal | /*成组模式下等待使能位设置 BCRx 13*/
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | /*扩展模式使能设置 BCRx 14*/
FSMC_NORSRAMInitStruct->FSMC_WriteBurst; /*成组写使能位相关参数设置 BCRx 19*/
/*如果是NOR闪存 使能内存访问使能位 BCRx 6*/
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
}
/* Bank1 NOR/SRAM 时序寄存器配置 BTRx */
/*根据FSMC_NORSRAMInitStruct->FSMC_Bank的值选择相应区的时序寄存器*/
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | /*地址建立时间*/
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | /*地址保持时间*/
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | /*数据保持时间*/
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | /*总线恢复时间*/
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | /*时钟分频比*/
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | /*(同步成组式NOR闪存的)数据保持时间*/
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; /*访问模式*/
/* 如果使用 BWTRx 寄存器 */
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
{
/*检查参数*/
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
/*设置同上*/
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
}
else
{
/*若没有用 BWTRx 复位寄存器 复位值 0X 0FFF FFFF*/
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
}
}