ARM 学习笔记之4： 常用指令1) AND 、BIC、TST

AND
             Logical AND.
Syntax
             AND{S}{cond} Rd, Rn, Operand2
where:
S
            is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.
cond
            is an optional condition code.
Rd
            is the destination register.
Rn
            is the register holding the first operand.
Operand2
            is a flexible second operand.\

Operation
The AND instruction performs bitwise AND operations on the values in Rn and Operand2.
In certain circumstances, the assembler can substitute BIC for AND, or AND for BIC. Be aware of this when
reading disassembly listings.
Rd = Rn and Operand2

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BIC
            Bit Clear.
            Syntax
                     BIC{S}{cond} Rd, Rn, Operand2
            where:
             S
                      is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.
            cond
                      is an optional condition code.
            Rd
                      is the destination register.
            Rn
                      is the register holding the first operand.
            Operand2
                      is a flexible second operand.

            Operation
                      The BIC (Bit Clear) instruction performs an AND operation on the bits in Rn with the complements of

                      the corresponding bits in the value of Operand2.

                      Rd = Rn and Operand2

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TST
            Test bits.
Syntax
            TST{cond} Rn, Operand2
where:
cond
            is an optional condition code.
Rn
            is the general-purpose register holding the first operand.
Operand2
            is a flexible second operand.
Operation
This instruction tests the value in a register against Operand2. It updates the condition flags on the result,
but does not place the result in any register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2.
This is the same as an ANDS instruction, except that the result is discarded

 Rn  and  Operand2