网卡数据手册阅读:ixgbe 网卡初始化流程

Initialization Sequence

Disable interrupts.

Most drivers disable interrupts during initialization to prevent re-entrance. Interrupts are
disabled by writing to the EIMC registers. Note that the interrupts also need to be
disabled after issuing a global reset, so a typical driver initialization flow is:

1. Disable interrupts.
2. Issue a global reset.
3. Disable interrupts (again).

Issue global reset and perform general configuration (see Section 4.6.3.2).

Global Reset = software reset + link reset.

Following a Global Reset the Software driver should wait at least 10msec to enable
smooth initialization flow.

To enable flow control, program the FCTTV, FCRTL, FCRTH, FCRTV and FCCFG registers

100 Mb/s, 1 GbE, and 10 GbE Link Initialization

1. BX/SGMII Link Setup Flow

2. XAUI/BX4/CX4/SFI Link Setup Flow

3. KX/KX4/KR Link Setup Flow without AutoNegotiation

4. KX/KX4/KR Link Setup Flow with AutoNegotiation

Initialization of Statistics

Statistics registers are hardware-initialized to values as detailed in each particular
register’s description. The initialization of these registers begins upon transition to D0
active power state (when internal registers become accessible, as enabled by setting the
Memory Access Enable field of the PCIe Command register), and is guaranteed to be
completed within 1 ms of this transition. Note that access to statistics registers prior to
this interval might return indeterminate values.

All of the statistical counters are cleared on read and a typical device driver reads them
(thus making them zero) as a part of the initialization sequence.

Interrupt Initialization

Operating with Legacy or MSI Interrupts:

• The software driver associates between Tx and Rx interrupt causes and the EICR
  register by setting the IVAR[n] registers.
• Program SRRCTL[n].RDMTS (per receive queue) if software uses the receive
  descriptor minimum threshold interrupt.
• All interrupts should be set to 0b (no auto clear in the EIAC register). Following an
  interrupt, software might read the EICR register to check for the interrupt causes.
• Set the auto mask in the EIAM register according to the preferred mode of operation.
• Set the interrupt throttling in EITR[n] and GPIE according to the preferred mode of
  operation.
• Software clears EICR by writing all ones to clear old interrupt causes.
• Software enables the required interrupt causes by setting the EIMS register.

Operating with MSI-X:

• The operating system / BIOS sets the hardware to MSI-X mode and programs the
  MSI-X table as part of the device enumeration procedure.
• The software driver associates between interrupt causes and MSI-X vectors and the
  throttling timers EITR[n] by programming the IVAR[n] and IVAR_MISC registers.
• Program SRRCTL[n].RDMTS (per receive queue) if software uses the receive
  descriptor minimum threshold interrupt.
• The EIAC[n] registers should be set to auto clear for transmit and receive interrupt
  causes (for best performance). The EIAC bits that control the other and TCP timer
  interrupt causes should be set to 0b (no auto clear).
• Set the auto mask in the EIAM and EIAM[n] registers according to the preferred
  mode of operation.
• Set the interrupt throttling in EITR[n] and GPIE according to the preferred mode of
  operation.
• Software enables the required interrupt causes by setting the EIMS[n] registers.

Receive Initialization

Initialize the following register tables before receive and transmit is enabled:

• Receive Address (RAL[n] and RAH[n]) for used addresses.
• Receive Address High (RAH[n].VAL = 0b) for unused addresses.
• Unicast Table Array (PFUTA).
• VLAN Filter Table Array (VFTA[n]).
• VLAN Pool Filter (PFVLVF[n]).
• MAC Pool Select Array (MPSAR[n]).
• VLAN Pool Filter Bitmap (PFVLVFB[n]).

The following should be done per each receive queue:

1. Allocate a region of memory for the receive descriptor list.
2. Receive buffers of appropriate size should be allocated and pointers to these buffers
   should be stored in the descriptor ring.
3. Program the descriptor base address with the address of the region (registers RDBAL,
   RDBAL).
4. Set the length register to the size of the descriptor ring (register RDLEN).
5. Program SRRCTL associated with this queue according to the size of the buffers and
   the required header control.
6. If header split is required for this queue, program the appropriate PSRTYPE for the
   appropriate headers.
7. Program RSC mode for the queue via the RSCCTL register.
8. Program RXDCTL with appropriate values including the queue Enable bit. Note that
   packets directed to a disabled queue are dropped.
9. Poll the RXDCTL register until the Enable bit is set. The tail should not be bumped
   before this bit was read as 1b.
10. Bump the tail pointer (RDT) to enable descriptors fetching by setting it to the ring
    length minus one.
11. Enable the receive path by setting RXCTRL.RXEN. This should be done only after all
    other settings are done following the steps below.
    — Halt the receive data path by setting SECRXCTRL.RX_DIS bit.
    — Wait for the data paths to be emptied by HW. Poll the SECRXSTAT.SECRX_RDY bit
    until it is asserted by HW.
    — Set RXCTRL.RXEN
    — Clear the SECRXCTRL.SECRX_DIS bits to enable receive data path
    — If software uses the receive descriptor minimum threshold Interrupt, that value
    should be set.
    Set bit 16 of the CTRL_EXT register and clear bit 12 of the DCA_RXCTRL[n] register[n].

Dynamic Enabling and Disabling of Receive Queues

Transmit Initialization

• Program the HLREG0 register according to the required MAC behavior.
• Program TCP segmentation parameters via registers DMATXCTL (while maintaining
  TE bit cleared), DTXTCPFLGL, and DTXTCPFLGH; and DCA parameters via
  DCA_TXCTRL.
• Set RTTDCS.ARBDIS to 1b.
• Program DTXMXSZRQ, TXPBSIZE, TXPBTHRESH, MTQC, and MNGTXMAP, according
  to the DCB and virtualization modes (see Section 4.6.11.3).
• Clear RTTDCS.ARBDIS to 0b.

1. Allocate a region of memory for the transmit descriptor list.
2. Program the descriptor base address with the address of the region (TDBAL, TDBAH).
3. Set the length register to the size of the descriptor ring (TDLEN).
4. Program the TXDCTL register with the desired Tx descriptor write back policy (see
   Section 8.2.3.9.10 for recommended values).
5. If needed, set TDWBAL/TWDBAH to enable head write back.
6. Enable transmit path by setting DMATXCTL.TE. This step should be executed only for
   the first enabled transmit queue and does not need to be repeated for any following
   queues.
7. Enable the queue using TXDCTL.ENABLE. Poll the TXDCTL register until the Enable bit
   is set.

Enable interrupts (see Section 4.6.3.1).