AXI 理解

一、burst传输和burstlength

Burst address

Use these equations to determine addresses of transfers within a burst:

Start_Address = ADDR

Number_Bytes = 2^Size;

Burst_Length = LEN +1

Aligned_Address =(INT( Start_Address / Number_Bytes )) x Number_Bytes

 

    eg,data[127:0]，即data宽度16byte,Burst_type=2'b01,(INCR)，则size=3'b100; 2^4=16； 一次burst最大有16个beat，即发一次cmd后，能有16个data transaction，一次transaction能传data_width=16byte的数据， 一次burst能传data_width * 16 = 256byte数据；
data[31:0],data_width=4byte，则size=3'b010,2^2=4，一次burst最大有16个beat，每个data transaction传4byte数据，一次burst能传4*16=64byte数据。
note：AWEN或者ARLEN= 实际需要传输的burst次数-1； eg,若实际剩余需要传输的data大于256byte,(dta[127:0])，则一次burst有16个beat，AWLEN或者ARLEN=15；
二、WSTRB[[3:0]
     WSTRB[n:0]用来表示WDATA[(8xn)+7:8xn]的哪些byte有效，eg，(1)data_width[127:0]，即WDTA[127:0],一beat传16byte数据，那么WSTRB[15:0], WSTRB[0]=1,则WDATA[7:0]有效传输，其他bit数据不会传输；WSTRB[1:0]=2'b11,表示WDATA[15:0] 有效；  (2)
data_width[31:0],一beat传4byte数据，则WSTRB[3:0].
三、Out-Standing and Out-Order
    The ability to issue multiple outstanding addresses means that masters can issue transaction addresses without waiting for earlier transactions to complete. This feature can improve system performance because it enables parallel processing of transactions.
即一次可以发多个cmd，无需等到前一次transaction完成，就可以发下一次transaction的cmd,即pipe line；
The ability to complete transactions out of order means that transactions to faster memory regions can complete without waiting for earlier transactions to slower memory regions. This feature can also improve system performance because it reduces the effect of transaction latency.
即通过WID,RID 实现多个master-slave间的乱序传输。