1)内存映射
MPC8377所有内存映射寄存器的范围为1Mbyte,内存映射寄存器基址寄存器(IMMRBAR)默认值为0xFF40_0000,该值也可由硬件配置字RCWH[ROMLOC]来重新设置,如下图所示:
2)复位后硬件信号配置状态
CFG_RESET_SOURCE[0:3]:TESC1_TXD[3:0]_0000
CFG_CLKIN_DIV:EC_MDC_1
CFG_LBMUX:TSEC1_TX_ER_1
3)硬件配置字
硬件配置字为:RCWLR_64040000,RCWHR_a0500002
意义:
RCWL_LBCM:0 csb_clk ratio is 1:1
RCWL_DDRCM:0 csb_clk ratio is 1:1
RCWL_SVCOD:10 VCO Division Factor = 2
RCWL_SPMF:0100
RCWL_COREPLL:0000100.
RCWL最终配置结果
RCWH_PCIHOST:1 The device acts as the host processor (default).
RCWH_PCIARB:0 0 On-chip PCI arbiter is disabled. External arbitration is required.
RCWH_COREDIS:0 0 The core can boot without waiting for configuration by an external master.
RCWH_BMS:0
RCWH_BOOTSEQ:00 Boot sequencer is disabled. No I2C ROM is accessed.
RCWH_SWEN:0 Software watchdog disabled.
RCWH_ROMLOC:101
RCWH_RLEXT:00 Legacy mode—allows for booting from on-chip peripherals. Refer to Table 4-16 for more information.
RCWH_TSEC1M:000 The eTSEC1 controller operates in the MII protocol, using only four transmit data signals and four receive data signals.
RCWH_TSEC1M:000 The eTSEC1 controller operates in the MII protocol, using only four transmit data signals and four receive data signals.
RCWH_TLE:0 Big-endian mode
RCWH_LDP:0 Initial value of SICRL[LDP_A] and SICRL[LDP_B] is 1, meaning thatLDP0–LDP3 are used for local data parity.
4) Clock
csb_clk = [PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)] × SPMF = 33MHZ x (1+1) x 4 = 198MHZ
ddr_clk = csb_clk;(RCWL_LBCM:0 csb_clk ratio is 1:1)
lbc_clk = csb_clk;(RCWL_DDRCM:0 csb_clk ratio is 1:1)
其它时钟是通过寄存器SCCR设置
5)System Configuration
MPC8377的local Memory 总共包括11部分
Window0_IMMR是整个8377的寄存器访问空间,共1Mbyte大小,其基地址为0xFF40_0000或0xFFF0_0000,由硬件配置字RCWH[ROMLOC]确定;
Window1~4为localBus空间,其基地址和大小由LBLAWBAR0~LBLAWBAR3和LBLAWAR0~LBLAWAR3配置
Window5~6为PCI空间,其基地址和大小由PCILWBAR0~PCILAWBAR1和PCILWAR0~PCILWAR1配置
Window7~8为DDR SDRAM空间,其基地址和大小由DDRLAWBAR0~DDRLAWBAR1和DDRLAWAR0~DDRLAWAR1配置
Window9~10为PCI Express空间,其基地址和大小由PCIEXP1WBAR~PCIEXP2WBAR和PCIEXP1WAR~PCIEXP2WAR配置
Local Memory Map Overview and Example: