1. Lead/Senior Physical Design Engineer (Location: SH)
Position Description:
Focus on high speed digital DDR and HBM IP physical implementation
Have good physical design experiences in the digital implementation domain including Floorplan, P&R, Physical verification, DFM.
Have a solid background in circuits, electronics & physics & should be very willing to learn new technology for advance node and design methodology
Skilled in scripting language, such as Perl, C shell, Make file
Feeling responsible for technical delivery, good team played, design quality/schedule focus
Position Requirements:
Essential Qualifications: Have MS degree with 2 ~4+ years of applicable experience, MS degree with 4 ~ 6+years of applicable experience in electrical engineering, microelectronics.
Essential that the individual demonstrates strong communication skill
Requires good communication skills in English.
2. Lead/Senior Frontend Implementation Engineer (Location: SH/BJ)
Position Description:
In charge of DDR and HBM IP Front End Implementation.
Daily duties include: RTL design Integration, Logic Synthesis, DFT, Static Timing Analysis and Verilog Simulation.
HDL language Knowledge, like verilog is necessary.
C/C++/perl/tcl/csh/python, UNIX, Linux experience are plus.
Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical and complex topics.
Excellent communication skills and the uncanny ability in a cooperative team environment are required.
Self-motivated, result-oriented, can take ownership and follow-through on tasks.
Position Requirements:
Essential Qualifications:
Master degree or above, 2-5 year working experience
Major in Micro-electronics, Electronic Engineering, Computer Science, Information Technology or equivalent
Ability to work effectively alone or as well as in the team.
Essential that the individual demonstrates strong communication, verbal and written
Requires good communication skills in English.
Desirable Qualifications:
Good at any following skill sets: ASIC design, FPGA design, Computer architecture, SOC design based on ARM/MIPS.
Experience of DDR or memory IPs
3. Lead Product Engineer- DDR PHY (Location: SH)
Position Description:
Cadence is looking for an individual to work in an established memory controller design IP team. The group provides configurable DDR memory controller and PHY IP for ASICs. The job will be mainly focused on providing technical support to customers, however there will be a variety of other engineering tasks that will allow the candidate to expand skills and responsibilities.
Provide technical support to customers for integration of IP into ASICs including:
Debugging of customers’ simulation or silicon issues.
Reviewing of customers’ integration of our IP.
Reviewing static timing reports to assist with customers’ timing closure.
Answering technical questions about IP operation.
Train field engineers in IP operation.
Interface with the R&D Team to bridge product improvements and resolve customer issues.
Position Requirements:
Excellent oral and written communication.
BS + 5 years of prior work-experience or MS + 2 years of prior work-experience
All front-end skills – RTL design & verification in Verilog, synthesis, static-timing analysis, DFT
Back-end skills – place & route, physical verification, timing closure
Time management skills sufficient to balance multiple high-priority projects.
Willingness to learn new skills and perform tasks that often go outside area of current expertise.
Additional Desirable Qualifications:
Experience with Static Timing scripts and report analysis
Familiarity with DDR memory operation, system applications, AXI, OCP, AHB
Familiarity with Frame maker
Scripting – in Perl, TCL, etc.
4. Senior Program Manager (Location: SH)
Position Description:
We are looking for a Senior Program Manager who will be responsible for the overall coordination of Key Customer Engagements and R&D Development Projects within the Design IP Group. The candidate must have experience in IP and/or SoC Design and a history in successfully program managing complex IP/SoC Programs with end customers. A PMP Certification or equivalent is desirable.
Main Job Tasks and Responsibilities
lead the planning and track the implementation of project
facilitate the definition of project scope, goals and deliverables
define project tasks and resource requirements
develop full scale project plans
manage/track project resource allocation
plan and schedule project timelines
track project deliverables using appropriate tools
provide direction and support to project team
support quality assurance
constantly monitor and report on progress of the project to all stakeholders
present reports defining project progress, problems and solutions
implement and manage project changes and interventions to achieve project outputs
manage customer engagement – project and relationship management
collaborate with Sales, Marketing, Finance and Engineering to assure effective and efficient project execution
Position Requirements:
Education and Experience
knowledge of both theoretical and practical aspects of project management
knowledge of project management techniques and tools
direct work experience in project management capacity
proven experience in people management
proven experience in strategic planning
proven experience in risk management
proven experience in change management
proficient in project management software
min 7+ years verifiable successes managing SoC/IP deliverables
BSEE at a min. MSEE & MBA preferred
Key competencies
critical thinking and problem solving skills
planning and organizing
decision-making
communication skills
influencing and leading
team work
conflict management
adaptability
5. Principal Design Engineer (Location: BJ)
Position Description:
Cadence/Tensilica is a leading provider of configurable embedded processor technology and DSPs for various markets. As a member of the DSP engineering group you will be responsible for verification of advanced DSP cores and their instruction set architectures and hardware implementations. You will implement architectural simulation test benches in C/C++/RTL, write C/assembly language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test plans, debugging failures and analyzing coverage information. You will work closely with the market-specific DSP teams, Design Verification, and RTL and EDA teams.
Position Requirements:
Knowledge of DSPs, instructions sets, computer arithmetic concepts, and processor architecture concepts
Good knowledge of C (C++ will be a plus)
Working knowledge of Verilog and popular EDA simulators and testbench methodologies
Knowledge of scripting languages such as Makefile/Perl is desired
Knowledge of assembly programming and programming in a high level language such as C
Good English communication skills – both written and verbal
Strong problem solving skills along with an ability to work independently and in cooperation with global teams
MS degree in EE/CS with 3 to 5 years industry experience required.
6. Principal R&D Application Engineer (Location: SH)
Position Description:
The Applications Engineer is responsible for working directly with customers, the internal development organization, sales/FAEs and other members of Cadence’s Xtensa Applications Engineering team. In this capacity, it is the direct responsibility of this individual to provide technical support, applications know how and training to use Cadence Tensilica’s microprocessor in SoCs.
Responsibilities:
Provide support for Cadence’s Tensilica IP products, specifically hardware flow and verification for SoC implementation
Become an expert and provide guidance on using Tensilica provided scripts for synthesis, place and route and layout. Also guide customers to use verification environment, power analysis scripts for Tensilica processors in stand-alone and/or embedded in an SoC.
Provide customer training for general Xtensa architecture and tools.
Provide quality solutions to customer issues in timely manner
Influence future Xtensa products by providing customer feedback back to the hardware and software development groups.
Work closely with Applications Engineering group located in San Jose, CA USA and Pune India to stay up-to-date with the latest tools and architecture.
Position Requirements:
BS in EE/CS (MS preferred) or equivalent plus 8 to 12 years work experience.
In-depth understanding of Computer architecture/ RISC processors/ DSPs
Hands-on experience in DSP processor implementation in SoC.
Hands-on experience in synthesis using latest technology libraries
Expert knowledge hardware design basics, Verilog language and of using various hardware design products like Cadence RTL compiler
Experience in development or testing of any of complex SoC using RISC or DSP processors. Deep knowledge of SoC system architecture, interfaces, and interconnects.
Experience in SoC system simulation and verification.
Familiar with on-chip bus protocols such as AMBA (AXI, AHB, APB), and on-chip trace and debug (JTAG, CoreSight).
Knowledge of DSP processors like audio processing, image processing will be plus.
Must have good English written and verbal communication skills as well as good problem solving skills.
Able to travel occasionally within China and 2 to 4-weeks per year to International locations.
，数字后端，数字前端，模拟layout，软件工程师，机器学习等相关人才
marco3260@163.com
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