FEATURES
Pin compatible upgrade of ADuC812/ADuC831/ADuC832 Increased performance
Single-cycle 20 MIPS 8052 core High speed 420 kSPS 12-bit ADC
Increased memory
Up to 62 kBytes on-chip Flash/EE program memory 4 kBytes on-chip Flash/EE data memory
In-circuit reprogrammable
Flash/EE, 100 year retention, 100 kCycle endurance 2304 bytes on-chip data RAM
Smaller package
8 mm × 8 mm chip scale package
52-lead PQFP—pin-compatible upgrade Analog I/O
8-channel, 420 kSPS high accuracy, 12-bit ADC On-chip, 15 ppm/°C voltage reference
DMA controller, high speed ADC-to-RAM capture Two 12-bit voltage output DACs1
Dual output PWM ∑-∆ DACs
On-chip temperature monitor function 8052 based core
8051 compatible instruction set (20 MHz max) High performance single-cycle core
32 kHz external crystal, on-chip programmable PLL
12 interrupt sources, 2 priority levels
Dual data pointers, extended 11-bit stack pointer On-chip peripherals
Time interval counter (TIC) UART, I2C®, and SPI® Serial I/O Watchdog timer (WDT) Power supply monitor (PSM)
Power
Normal: 4.5 mA @ 3 V (core CLK = 2.098 MHz)
Power-down: 10 µA @ 3 V2 Development tools
Low cost, comprehensive development system incorporating nonintrusive single-pin emulation,
IDE based assembly and C source debugging
APPLICATIONS
Optical networking—laser power control
Base station systems
Precision instrumentation, smart sensors
Transient capture systems
DAS and communications systems
2 ADuC842/ADuC843 only, ADuC841 driven directly by external crystal.
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
| ADuC841/ADuC842/ADuC843 |
| 12-BIT | BUF | DAC1 | ||
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| DAC | |||||
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| 12-BIT | BUF | DAC1 |
| ADC0 |
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| DAC | ||
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| ADC1 | T/H | 12-BIT ADC |
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| 16-BIT |
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| MUX |
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| Σ-∆ DAC |
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| ADC5 |
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| ADC6 |
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| 16-BIT |
| PWM0 |
| ADC7 |
| HARDWARE | Σ-∆ DAC |
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| MUX |
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| CALIBRATON |
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| TEMP |
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| 16-BIT |
| PWM1 |
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| PWM |
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| SENSOR |
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| 16-BIT |
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| PWM |
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| 20 MIPS 8052 BASED MCU WITH ADDITIONAL |
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| PERIPHERALS |
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| PLL2 | 62 kBYTES FLASH/EE PROGRAM MEMORY |
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| 4 kBYTES FLASH/EE DATA MEMORY |
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| 2304 BYTES USER RAM |
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| 3 × 16 BIT TIMERS |
| POWER SUPPLY MON |
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| INTERNAL | OSC | 1 × REAL TIME CLOCK | WATCHDOG TIMER | -0-001 | ||
| BAND GAP | 4 × PARALLEL |
| UART, I2 C, AND SPI | |||
| VREF |
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| PORTS |
| SERIAL I/O | 03260 | |
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| CREF | XTAL1 XTAL2 |
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Figure 1.
GENERAL DESCRIPTION
The ADuC841/ADuC842/ADuC8431 are complete smart transducer front ends, that integrates a high performance self-calibrating multichannel ADC, a dual DAC, and an optimized single-cycle 20 MHz 8-bit MCU (8051 instruction set compatible) on a single chip.
The ADuC841 and ADuC842 are identical with the exception of the clock oscillator circuit; the ADuC841 is clocked directly from an external crystal up to 20 MHz whereas the ADuC842 uses a 32 kHz crystal with an on-chip PLL generating a programmable core clock up to 16.78 MHz.
The ADuC843 is identical to the ADuC842 except that the ADuC843 has no analog DAC outputs.
The microcontroller is an optimized 8052 core offering up to 20 MIPS peak performance. Three different memory options are available offering up to 62 kBytes of nonvolatile Flash/EE program memory. Four kBytes of nonvolatile Flash/EE data memory, 256 bytes RAM, and 2 kBytes of extended RAM are also integrated on-chip.
1 Protected by U.S. Patent No. 5,969,657.
(continued on page 23)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
REVISION HISTORY
6/2017—Rev. A to Rev. B
Change to Notes, Figure 4 14
Changes to Figure 96 95
4/2016—Rev. 0 to Rev. A
Added Patent Note, Note 1 1
Changes to Figure 3 and Table 3 9
Changes to Figure 4 14
Added Table 4; Renumbered Sequentially 14
Changes to Using the DAC Section 47
Updated Outline Dimensions 94
Changes to Ordering Guide 95
11/2003—Revision 0: Initial Version
Rev. B | Page 2 of 95
Data Sheet ADuC841/ADuC842/ADuC843
SPECIFICATIONS1
Table 1. AVDD = DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; VREF = 2.5 V internal reference, fCORE = 16.78 MHz @ 5 V 8.38 MHz @ 3 V; all specifications TA = TMIN to TMAX, unless otherwise noted
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| Parameter | VDD = 5 V | VDD = 3 V | Unit | Test Conditions/Comments |
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| ADC CHANNEL SPECIFICATIONS |
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| DC ACCURACY2, 3 |
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| fSAMPLE = 120 kHz, see the Typical |
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| Performance Characteristics for typical |
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| performance at other values of fSAMPLE |
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| Resolution | 12 | 12 | Bits |
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| Integral Nonlinearity | ±1 | ±1 | LSB max | 2.5 V internal reference |
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| ±0.3 | ±0.3 | LSB typ |
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| Differential Nonlinearity | +1/–0.9 | +1/–0.9 | LSB max | 2.5 V internal reference |
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| ±0.3 | ±0.3 | LSB typ |
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| Integral Nonlinearity4 | ±2 | ±1.5 | LSB max | 1 V external reference |
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| Differential Nonlinearity4 | +1.5/–0.9 | +1.5/–0.9 | LSB max | 1 V external reference |
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| Code Distribution | 1 | 1 | LSB typ | ADC input is a dc voltage |
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| CALIBRATED ENDPOINT ERRORS5, 6 |
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| Offset Error | ±3 | ±2 | LSB max |
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| Offset Error Match | ±1 | ±1 | LSB typ |
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| Gain Error | ±3 | ±2 | LSB max |
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| Gain Error Match | ±1 | ±1 | LSB typ |
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| DYNAMIC PERFORMANCE |
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| fIN = 10 kHz sine wave |
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| fSAMPLE = 120 kHz |
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| Signal-to-Noise Ratio (SNR)7 | 71 | 71 | dB typ |
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| Total Harmonic Distortion (THD) | –85 | –85 | dB typ |
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| Peak Harmonic or Spurious Noise | –85 | –85 | dB typ |
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| Channel-to-Channel Crosstalk8 | –80 | –80 | dB typ |
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| ANALOG INPUT |
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| Input Voltage Range | 0 to VREF | 0 to VREF | V |
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| Leakage Current | ±1 | ±1 | µA max |
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| Input Capacitance | 32 | 32 | pF typ |
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| TEMPERATURE SENSOR9 |
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| Voltage Output at 25°C | 700 | 700 | mV typ |
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| Voltage TC | –1.4 | –1.4 | mV/°C typ |
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| Accuracy | ±1.5 | ±1.5 | °C typ | Internal/External 2.5 V VREF |
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| DAC CHANNEL SPECIFICATIONS |
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| DAC load to AGND |
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| Internal Buffer Enabled |
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| RL = 10 kΩ, CL = 100 pF |
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| DC ACCURACY10 |
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| Resolution | 12 | 12 | Bits |
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| Relative Accuracy | ±3 | ±3 | LSB typ |
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| Differential Nonlinearity11 | –1 | –1 | LSB max | Guaranteed 12-bit monotonic |
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| ±1/2 | ±1/2 | LSB typ |
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| Offset Error | ±50 | ±50 | mV max | VREF range |
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| Gain Error | ±1 | ±1 | % max | AVDD range |
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| ±1 | ±1 | % typ | VREF range |
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| Gain Error Mismatch | 0.5 | 0.5 | % typ | % of full-scale on DAC1 |
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| ANALOG OUTPUTS |
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| Voltage Range_0 | 0 to VREF | 0 to VREF | V typ | DAC VREF = 2.5 V |
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| Voltage Range_1 | 0 to VDD | 0 to VDD | V typ | DAC VREF = VDD |
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| Output Impedance | 0.5 | 0.5 | Ω typ |
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Rev. B | Page 3 of 95
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| Data Sheet | |||
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| Parameter | VDD = 5 V | VDD = 3 V | Unit | Test Conditions/Comments | ||
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| DAC AC CHARACTERISTICS |
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| Voltage Output Settling Time | 15 | 15 | µs typ | Full-scale settling time to within | ||
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| ½ LSB of final value |
| Digital-to-Analog Glitch Energy | 10 | 10 | nV-sec typ | 1 LSB change at major carry | ||
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| DAC CHANNEL SPECIFICATIONS12, 13 |
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| DC ACCURACY10 |
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| Resolution | 12 | 12 | Bits |
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| Relative Accuracy | ±3 | ±3 | LSB typ |
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| Differential Nonlinearity11 | –1 | –1 | LSB max | Guaranteed 12-bit monotonic | ||
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| ±1/2 | ±1/2 | LSB typ |
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| Offset Error | ±5 | ±5 | mV max | VREF range | ||
| Gain Error | ±0.5 | ±0.5 | % typ | VREF range | ||
| Gain Error Mismatch4 | 0.5 | 0.5 | % typ | % of full-scale on DAC1 | ||
| ANALOG OUTPUTS |
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| Voltage Range_0 | 0 to VREF | 0 to VREF | V typ | DAC VREF = 2.5 V | ||
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| REFERENCE INPUT/OUTPUT REFERENCE OUTPUT14 |
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| Output Voltage (VREF) | 2.5 | 2.5 | V |
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| Accuracy | ±10 | ±10 | mV Max | Of VREF measured at the CREF pin | ||
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| TA = 25°C |
| Power Supply Rejection | 65 | 67 | dB typ |
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| Reference Temperature Coefficient | ±15 | ±15 | ppm/°C typ |
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| Internal VREF Power-On Time | 2 | 2 | ms typ |
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| EXTERNAL REFERENCE INPUT15 |
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| Voltage Range (VREF) 4 | 1 | 1 | V min |
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| VDD | VDD | V max |
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| Input Impedance | 20 | 20 | kΩ typ |
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| Input Leakage | 1 | 1 | µA max | Internal band gap deselected via | ||
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| ADCCON1.6 |
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| POWER SUPPLY MONITOR (PSM) |
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| DVDD Trip Point Selection Range |
| 2.93 | V min | Two trip points selectable in this | ||
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| 3.08 | V max | range programmed via TPD1–0 in |
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| PSMCON, 3 V part only |
| DVDD Power Supply Trip Point Accuracy |
| ±2.5 | % max |
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| WATCHDOG TIMER (WDT) 4 |
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| Timeout Period | 0 | 0 | ms min | Nine timeout periods selectable in | ||
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| 2000 | 2000 | ms max | this range |
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| FLASH/EE MEMORY RELIABILITY CHARACTERISTICS16 |
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| Endurance17 | 100,000 | 100,000 | Cycles min |
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| Data Retention18 | 100 | 100 | Years min |
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| DIGITAL INPUTS |
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| ±10 | ±10 | µA max | VIN = 0 V or VDD | ||
| Input Leakage Current (Port 0, | EA | ) | ||||
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| ±1 | ±1 | µA typ | VIN = 0 V or VDD |
| Logic 1 Input Current |
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| (All Digital Inputs), SDATA, SCLOCK | ±10 | ±10 | µA max | VIN = VDD | ||
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| ±1 | ±1 | µA typ | VIN = VDD |
| Logic 0 Input Current (Ports 1, 2, 3) SDATA, SCLOCK | –75 | –25 | µA max |
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| –40 | –15 | µA typ | VIL = 450 mV |
| Logic 1 to Logic 0 Transition Current (Ports 2 and 3) | –660 | –250 | µA max | VIL = 2 V | ||
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| –400 | –140 | µA typ | VIL = 2 V |
| RESET | ±10 | ±10 | µA max | VIN = 0 V | ||
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| 10 | 5 | µA min | VIN = 5 V, 3 V Internal Pull Down |
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| 105 | 35 | µA max | VIN = 5 V, 3 V Internal Pull Down |
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Rev. B | Page 4 of 95
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| ADuC841/ADuC842/ADuC843 | ||||
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| Parameter | VDD = 5 V | VDD = 3 V | Unit |
| Test Conditions/Comments | ||
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| LOGIC INPUTS4 |
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| INPUT VOLTAGES |
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| All Inputs Except SCLOCK, SDATA, RESET, and |
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| XTAL1 |
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| VINL, Input Low Voltage | 0.8 | 0.4 | V max |
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| VINH, Input High Voltage | 2.0 | 2.0 | V min |
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| SDATA |
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| VINL, Input Low Voltage | 0.8 | 0.8 | V max |
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| VINH, Input High Voltage | 2.0 | 2.0 | V min |
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| SCLOCK and RESET ONLY4 |
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| (Schmitt-Triggered Inputs) |
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| VT+ | 1.3 | 0.95 | V min |
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| 3.0 | 0.25 | V max |
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| VT– | 0.8 | 0.4 | V min |
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| 1.4 | 1.1 | V max |
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| VT+ – VT– | 0.3 | 0.3 | V min |
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| 0.85 | 0.85 | V max |
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| CRYSTAL OSCILLATOR |
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| Logic Inputs, XTAL1 Only |
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| VINL, Input Low Voltage | 0.8 | 0.4 | V typ |
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| VINH, Input High Voltage | 3.5 | 2.5 | V typ |
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| XTAL1 Input Capacitance | 18 | 18 | pF typ |
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| XTAL2 Output Capacitance | 18 | 18 | pF typ |
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| MCU CLOCK RATE | 16.78 | 8.38 | MHz max |
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| 20 | 8.38 | MHz max |
| ADuC841 Only |
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| DIGITAL OUTPUTS |
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| Output High Voltage (VOH) | 2.4 |
| V min |
| VDD = 4.5 V to 5.5 V | ||
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| 4 |
| V typ |
| ISOURCE = 80 µA |
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| 2.4 | V min |
| VDD = 2.7 V to 3.3 V |
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| 2.6 | V typ |
| ISOURCE = 20 µA |
| Output Low Voltage (VOL) |
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| ALE, Ports 0 and 2 | 0.4 | 0.4 | V max |
| ISINK = 1.6 mA | ||
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| 0.2 | 0.2 | V typ |
| ISINK = 1.6 mA |
| Port 3 | 0.4 | 0.4 | V max |
| ISINK = 4 mA | ||
| SCLOCK/SDATA | 0.4 | 0.4 | V max |
| ISINK = 8 mA, I2C Enabled | ||
| Floating State Leakage Current4 | ±10 | ±10 | µA max |
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| ±1 | ±1 | µA typ |
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| STARTUP TIME |
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| At any core CLK | ||
| At Power-On | 500 | 500 | ms typ |
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| From Idle Mode | 100 | 100 | µs typ |
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| From Power-Down Mode |
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| 150 | 400 | µs typ |
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| Wake-up with | INT0 | Interrupt |
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| Wake-up with SPI/I2C Interrupt | 150 | 400 | µs typ |
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| Wake-up with External RESET | 150 | 400 | µs typ |
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| After External RESET in Normal Mode | 30 | 30 | ms typ |
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| After WDT Reset in Normal Mode | 3 | 3 | ms typ |
| Controlled via WDCON SFR | ||
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