VHDL实现194功能代码

Neverland ly

于 2022-12-21 12:35:04 发布

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文章标签： fpga开发

本文链接：https://blog.csdn.net/Y2816093416/article/details/128395578

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完整代码：

LIBRARY IEEE;                                                            

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;



ENTITY jicunqi IS

       PORT(

       CR,CP,SL,SR:IN STD_LOGIC;

       S0,S1:IN STD_LOGIC;

       D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

       Q0,Q1,Q2,Q3:out STD_LOGIC

       );

END jicunqi;



ARCHITECTURE behavior OF jicunqi IS

signal M1:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

       PROCESS(CR,CP)

       BEGIN

              IF CR='0'     THEN

                     M1<="0000";

              ELSIF CP'EVENT AND CP ='1'    THEN

                     IF S1='0'     AND S0='1' THEN    M1<=SR&M1(3 DOWNTO 1);

                     ELSIF S1='1' AND S0='0'     THEN M1<=M1(2 DOWNTO 0)&SL;

                     ELSIF S1='1' AND S0='1'     THEN M1<=D;

                     END IF;

              END IF;

       END PROCESS;

       Q3<=M1(0);Q2<=M1(1);Q1<=M1(2);Q0<=M1(3);

END BEHAVIOR;