`timescale 10ns/1ps
module CNT_tb;
reg clk,RST,EN;
wire[3:0]q;
initial
begin
clk=0;
forever #2.5 clk=~clk;
end
initial
begin
RST=0; EN=1;
#15 RST=1;
#10 RST=0;
#45 EN=0;
#10 EN=1;
#10 $stop;
end
CNT_tb CNT(.clk(clk),.RST(RST),.EN(EN),.q(q));
endmodule
module CNT(output reg [3:0]q,input clk,input RST,input EN);
always@(posedge clk,posedge RST)
begin
if(RST)q<=0;
else if(!EN)q<=q;
else q<=q+1;
end
endmodule
EDA学习笔记timescale 10ns/1ps
最新推荐文章于 2022-07-23 00:11:54 发布