Verilog 基本电路3-全加器

module full_add(Cout, Sum, Ain, Bin, Cin);
	input Ain, Bin, Cin;
	output Sum, Cout;
	wire Sum;
	wire Cout;
	assign Sum = Ain ^ Bin ^ Cin;
	assign Cout = (Ain & Bin) | (Bin & Cin) | (Ain & Cin);
endmodule

module adder_carry_para#(parameter N=4)
(
  input [N-1:0] a,
  input [N-1:0] b,
  output [N-1:0] sum,
  output cout // carry output
);
// constant declaration
localparam N1 = N - 1;
           // signal declaration
wire [N:0] sum_ext;
// body
assign sum_ext = {1'b0, a} + {1'b0, b};
assign sum = sum_ext[N1:0];
assign cout = sum_ext[N];

endmodule