Cache Policies

FROM:

http://ywuchn.spaces.live.com/blog/cns!2F33043850B92381!452.entry

 

Most modern CPUs have a MMU module which handles address translation. It means that the effective address used by the software may not be same with physical address where the data actually resides. Then the cache can be placed beyond or behind address translation mechanism. We know that item in cache is made up of tag, index, offset and data. Tag and index are used to locate an individual item. We can implement tag and index from either virtual or physical address. So we can get four combinations including VIVT (virtual-index, virtual tag), PIPT, PIVT and VIPT. Different implementations lead to different properties.

In physically indexed, physically tagged (PIPT) caches, the tag and index of the cache are both in physical memory, that is, after virtual address translation has been done. This process is nice and simple, but the disadvantage of PIPT caches is that a valid address translation must be in the TLB (translation lookaside buffer) of the CPU. If such a TLB entry needs to be fetched from memory before the address translation can be done, the advantage of caching the data is lost. Even if a TLB entry is present, the TLB lookup and the cache lookup must be done sequentially, making these caches slow.

In virtual-indexed, virtual-tagged (VIVT) cache, both the index and the tag are based on the virtual address. The main advantage of this method is that cache lookups are faster because the translation look-aside buffer (TLB) is not involved in matching cache lines for a virtual address. However, this caching method does require more frequent cache flushing because of cache aliasing, in which the same physical address can be mapped to multiple virtual addresses. Another disadvantage is that in OS which implement virtual memory and the TLB items are changed frequently, cache mechanism must pay more attention to it.

In a virtual-indexed, physical-tagged (VIPT) cache, the cache line index is derived from the virtual address. However, the tag is specified by using the physical address. The main advantage is that cache aliasing is not an issue because every physical address has a unique tag in the cache. However, a cache entry cannot be determined to be valid until the TLB has translated the virtual address to a physical address that matches the tag. Generally, the TLB lookup cost offsets the performance gain achieved by avoiding cache aliasing.

The VIPT cache gains its speed advantage over PIPT because the address translation and the cache lookup now can be done in parallel. The CPU doesn't know if the cache line is valid (the tags match), however, until the address translation has completed.

The disadvantages of VIVT are overcome because the tag is physical, thus the VIPT cache automatically detects aliasing when it sees that two tags are identical in the cache. Thus, a VIPT cache may be constructed in such a fashion that cache-line aliasing never occurs.

Physically indexed, virtually tagged (PIVT), is only a theoretical type and basically useless.  It seems that it was implemented in MIPS6000.

Note: the term flush is used for writing back and invalidating cache lines.