vhdl 15位m序列发生

library a40mx;

use a40mx.all;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity test is    port(qout:out std_logic;  clkin,clrin:in std_logic);

end test;

architecture structual of test is component dfcib    port(d:in std_logic; clk:in std_logic;  clr:in std_logic;  q:out std_logic);

end component;

component xnor2    port(a:in std_logic;          b:in std_logic;          y:out std_logic);

end component;

signal q1:std_logic;

signal q2:std_logic;

signal q3:std_logic;

signal q4:std_logic;

signal y1:std_logic;

begin qout<=q4;

u1:dfcib port map (y1,clkin,clrin,q1);

u2:dfcib port map (q1,clkin,clrin,q2);

u3:dfcib port map (q2,clkin,clrin,q3);

 u4:dfcib port map (q3,clkin,clrin,q4);

 u5:xnor2 port map (q3,q4,y1);

end structual;