ILI9881C 配BOE_TV101WXU-N90-49P0

本文链接：https://blog.csdn.net/baidu_37552881/article/details/141017826

ILI9881C 配BOE_TV101WXU-N90-49P0_V02 玻璃

(1) panel timming: 在这里插入图片描述
（2）原始初始化代码，需要跟进index 修改成RK数据包格式

REGISTER,FF,03,98,81,03

//GIP_1
REGISTER,01,01,00
REGISTER,02,01,00
REGISTER,03,01,53        //STVA
REGISTER,04,01,00        //STVB
REGISTER,05,01,00        //STVC
REGISTER,06,01,08        //STVA_Rise
REGISTER,07,01,00        //STVB_Rise
REGISTER,08,01,00        //STVC_Rise
REGISTER,09,01,00        //FTI1R(A)
REGISTER,0a,01,00        //FTI2R(B)
REGISTER,0b,01,00        //FTI3R(C)
REGISTER,0c,01,00        //FTI1F(A)
REGISTER,0d,01,00        //FTI2F(B)
REGISTER,0e,01,00        //FTI2F(C)
REGISTER,0f,01,26    //08        //CLW1(ALR) 45%
REGISTER,10,01,26    //08        //CLW2(ARR) 45%
REGISTER,11,01,00           
REGISTER,12,01,00        
REGISTER,13,01,00        //CLWX(ATF)
REGISTER,14,01,00
REGISTER,15,01,00        //GPMRi(ALR)
REGISTER,16,01,00        //GPMRii(ARR)
REGISTER,17,01,00        //GPMFi(ALF)
REGISTER,18,01,00        //GPMFii(AFF)
REGISTER,19,01,00
REGISTER,1a,01,00
REGISTER,1b,01,00   
REGISTER,1c,01,00
REGISTER,1d,01,00
REGISTER,1e,01,40        //CLKA 40︑笆は C0も笆は(X8把σCLKB)
REGISTER,1f,01,C0        //C0
REGISTER,20,01,06        //CLKA_Rise
REGISTER,21,01,01        //CLKA_Fall
REGISTER,22,01,07        //CLKB_Rise(keep toggle惠砞CLK A)
REGISTER,23,01,00        //CLKB_Fall
REGISTER,24,01,8A        //CLK keep toggle(AL) 8X┕オ
REGISTER,25,01,8A        //CLK keep toggle(AR) 8X┕オ
REGISTER,26,01,00
REGISTER,27,01,00
REGISTER,28,01,33    //3B       //CLK Phase
REGISTER,29,01,33       //CLK overlap
REGISTER,2a,01,00  
REGISTER,2b,01,00
REGISTER,2c,01,08       //GCH R
REGISTER,2d,01,08       //GCL R 
REGISTER,2e,01,0B       //GCH F        
REGISTER,2f,01,0B       //GCL F
REGISTER,30,01,00
REGISTER,31,01,00
REGISTER,32,01,42       //GCH/L ext2/1︽  5E 01:31   5E 00:42
REGISTER,33,01,00
REGISTER,34,01,00       //VDD1&2 non-overlap 04:2.62us
REGISTER,35,01,0A       //GCH/L 跋丁 00:VS玡 01:VS 10:阁VS 11:frameい       
REGISTER,36,01,00
REGISTER,37,01,08       //GCH/L
REGISTER,38,01,3C	//VDD1&2 toggle 1sec
REGISTER,39,01,00
REGISTER,3a,01,00 
REGISTER,3b,01,00
REGISTER,3c,01,00
REGISTER,3d,01,00
REGISTER,3e,01,00
REGISTER,3f,01,00
REGISTER,40,01,00
REGISTER,41,01,00
REGISTER,42,01,00
REGISTER,43,01,08       //GCH/L
REGISTER,44,01,00

//GIP_2
REGISTER,50,01,01
REGISTER,51,01,23
REGISTER,52,01,45
REGISTER,53,01,67
REGISTER,54,01,89
REGISTER,55,01,ab
REGISTER,56,01,01
REGISTER,57,01,23
REGISTER,58,01,45
REGISTER,59,01,67
REGISTER,5a,01,89
REGISTER,5b,01,ab
REGISTER,5c,01,cd
REGISTER,5d,01,ef

//GIP_3
REGISTER,5e,01,00
REGISTER,5f,01,01     //FW_CGOUT_L[1]    VDS
REGISTER,60,01,01     //FW_CGOUT_L[2]    VDS
REGISTER,61,01,06     //FW_CGOUT_L[3]    STV2
REGISTER,62,01,06     //FW_CGOUT_L[4]    STV2
REGISTER,63,01,06     //FW_CGOUT_L[5]    STV4
REGISTER,64,01,06     //FW_CGOUT_L[6]    STV4
REGISTER,65,01,00     //FW_CGOUT_L[7]    VSD
REGISTER,66,01,00     //FW_CGOUT_L[8]    VSD
REGISTER,67,01,17     //FW_CGOUT_L[9]    GCL
REGISTER,68,01,02     //FW_CGOUT_L[10]   
REGISTER,69,01,16     //FW_CGOUT_L[11]   GCH  
REGISTER,6a,01,16     //FW_CGOUT_L[12]   GCH
REGISTER,6b,01,02     //FW_CGOUT_L[13]   
REGISTER,6c,01,0D     //FW_CGOUT_L[14]   CLK8   
REGISTER,6d,01,0D     //FW_CGOUT_L[15]   CLK8
REGISTER,6e,01,0C     //FW_CGOUT_L[16]   CLK6    
REGISTER,6f,01,0C     //FW_CGOUT_L[17]   CLK6
REGISTER,70,01,0F     //FW_CGOUT_L[18]   CLK4
REGISTER,71,01,0F     //FW_CGOUT_L[19]   CLK4
REGISTER,72,01,0E     //FW_CGOUT_L[20]   CLK2
REGISTER,73,01,0E     //FW_CGOUT_L[21]   CLK2
REGISTER,74,01,02     //FW_CGOUT_L[22]   VGL
  
REGISTER,75,01,01     //BW_CGOUT_L[1]   
REGISTER,76,01,01     //BW_CGOUT_L[2]    
REGISTER,77,01,06     //BW_CGOUT_L[3]    
REGISTER,78,01,06     //BW_CGOUT_L[4]    
REGISTER,79,01,06     //BW_CGOUT_L[5]     
REGISTER,7a,01,06     //BW_CGOUT_L[6]     
REGISTER,7b,01,00     //BW_CGOUT_L[7]   
REGISTER,7c,01,00     //BW_CGOUT_L[8]    
REGISTER,7d,01,17     //BW_CGOUT_L[9]      
REGISTER,7e,01,02     //BW_CGOUT_L[10]
REGISTER,7f,01,16     //BW_CGOUT_L[11]    
REGISTER,80,01,16     //BW_CGOUT_L[12]   
REGISTER,81,01,02     //BW_CGOUT_L[13] 
REGISTER,82,01,0D     //BW_CGOUT_L[14]      
REGISTER,83,01,0D     //BW_CGOUT_L[15]   
REGISTER,84,01,0C     //BW_CGOUT_L[16]      
REGISTER,85,01,0C     //BW_CGOUT_L[17]
REGISTER,86,01,0F     //BW_CGOUT_L[18]
REGISTER,87,01,0F     //BW_CGOUT_L[19]
REGISTER,88,01,0E     //BW_CGOUT_L[20]   
REGISTER,89,01,0E     //BW_CGOUT_L[21]   
REGISTER,8A,01,02     //BW_CGOUT_L[22]   

//CMD_Page 4
REGISTER,FF,03,98,81,04

REGISTER,6E,01,2B           /VGH 15V
REGISTER,6F,01,35    //37           // reg vcl + pumping ratio VGH=3x VGL=-2.5x
REGISTER,3A,01,A4           //POWER SAVING
REGISTER,8D,01,1A           //VGL -11V
REGISTER,87,01,BA           //ESD
REGISTER,B2,01,D1
REGISTER,88,01,0B
REGISTER,38,01,01      
REGISTER,39,01,00
REGISTER,B5,01,07           //gamma bias
REGISTER,31,01,75
REGISTER,3B,01,98  			
			
//CMD_Page 1
REGISTER,FF,03,98,81,01
REGISTER,22,01,0A          //BGR, SS
REGISTER,31,01,00          //Column inversion
REGISTER,53,01,40          //VCOM1
REGISTER,55,01,40          //VCOM2 
REGISTER,50,01,95          //VREG1OUT 4.5V
REGISTER,51,01,90          //VREG2OUT -4.5V
REGISTER,60,01,22    //06          //SDT
REGISTER,62,01,20
//============Gamma START=============

//Pos Register
REGISTER,A0,01,00
REGISTER,A1,01,1B
REGISTER,A2,01,2A
REGISTER,A3,01,14
REGISTER,A4,01,17
REGISTER,A5,01,2B
REGISTER,A6,01,1F
REGISTER,A7,01,20
REGISTER,A8,01,93
REGISTER,A9,01,1E
REGISTER,AA,01,2A
REGISTER,AB,01,7E
REGISTER,AC,01,1B
REGISTER,AD,01,19
REGISTER,AE,01,4C
REGISTER,AF,01,22
REGISTER,B0,01,28
REGISTER,B1,01,4B
REGISTER,B2,01,59
REGISTER,B3,01,23



//Neg Register
REGISTER,C0,01,00
REGISTER,C1,01,1B
REGISTER,C2,01,2A
REGISTER,C3,01,14
REGISTER,C4,01,17
REGISTER,C5,01,2B
REGISTER,C6,01,1F
REGISTER,C7,01,20
REGISTER,C8,01,93
REGISTER,C9,01,1E
REGISTER,CA,01,2A
REGISTER,CB,01,7E
REGISTER,CC,01,1B
REGISTER,CD,01,19
REGISTER,CE,01,4C
REGISTER,CF,01,22
REGISTER,D0,01,28
REGISTER,D1,01,4B
REGISTER,D2,01,59
REGISTER,D3,01,23

//============ Gamma END===========			
			
//CMD_Page 0			
REGISTER,FF,03,98,81,00
REGISTER,11,01,00  
Delay,120
REGISTER,29,01,00
REGISTER,35,01,00

（3）修改配置在RK3566/3568上DTS：


&dsi0 {
	status = "okay";
	rockchip,lane-rate = <600>; //<1000>;

	panel: panel@0 {
		status = "okay";
		compatible = "simple-panel-dsi";
		reg = <0>;
		backlight = <&backlight2>;
		enable-gpios = <&gpio8 6 GPIO_ACTIVE_HIGH>;

		reset-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; // 1280x800 
		
		power-supply = <&vcc_lcd>;		
		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_EOT_PACKET)>;
		dsi,format = <MIPI_DSI_FMT_RGB888>;
		dsi,lanes = <4>;
		
		/*reset-delay-ms = <20>;
		init-delay-ms = <20>;
		enable-delay-ms = <20>;
		prepare-delay-ms = <20>;
		delay,prepare = <120>;
		delay,enable = <200>;*/
		
		prepare-delay-ms = <20>;
		reset-delay-ms = <30>;
		init-delay-ms = <30>;
		enable-delay-ms = <300>;		
				
		panel-init-sequence = [
		39 00 04 FF 98 81 03
								 
		15 00 02 01 00        //GIP_1
		15 00 02 02 00
		15 00 02 03 53        //STVA
		15 00 02 04 00        //STVB
		15 00 02 05 00        //STVC
		15 00 02 06 08        //STVA_Rise
		15 00 02 07 00        //STVB_Rise
		15 00 02 08 00        //STVC_Rise
		15 00 02 09 00        //FTI1R(A)
		15 00 02 0a 00        //FTI2R(B)
		15 00 02 0b 00        //FTI3R(C)
		15 00 02 0c 00        //FTI1F(A)
		15 00 02 0d 00        //FTI2F(B)
		15 00 02 0e 00        //FTI2F(C)
		15 00 02 0f 26          //08        //CLW1(ALR) 45%
		15 00 02 10 26          //08        //CLW2(ARR) 45%
		15 00 02 11 00           
		15 00 02 12 00        
		15 00 02 13 00        //CLWX(ATF)
		15 00 02 14 00
		15 00 02 15 00        //GPMRi(ALR)
		15 00 02 16 00        //GPMRii(ARR)
		15 00 02 17 00        //GPMFi(ALF)
		15 00 02 18 00        //GPMFii(AFF)
		15 00 02 19 00
		15 00 02 1a 00
		15 00 02 1b 00   
		15 00 02 1c 00
		15 00 02 1d 00
		15 00 02 1e 40        //CLKA 40自動反 C0手動反(X8參考CLKB)
		15 00 02 1f C0        //C0
		15 00 02 20 06        //CLKA_Rise
		15 00 02 21 01        //CLKA_Fall
		15 00 02 22 07        //CLKB_Rise(keep toggle需設CLK A後一格)
		15 00 02 23 00        //CLKB_Fall
		15 00 02 24 8A        //CLK keep toggle(AL) 8X往左看
		15 00 02 25 8A        //CLK keep toggle(AR) 8X往左看
		15 00 02 26 00
		15 00 02 27 00
		15 00 02 28 33       //3B       //CLK Phase
		15 00 02 29 33       //CLK overlap
		15 00 02 2a 00  
		15 00 02 2b 00
		15 00 02 2c 08       //GCH R
		15 00 02 2d 08       //GCL R 
		15 00 02 2e 0B       //GCH F        
		15 00 02 2f 0B       //GCL F
		15 00 02 30 00
		15 00 02 31 00
		15 00 02 32 42       //GCH/L ext2/1行為  5E 01:31   5E 00:42
		15 00 02 33 00
		15 00 02 34 00       //VDD1&2 non-overlap 04:2.62us
		15 00 02 35 0A       //GCH/L 區間 00:VS前 01:VS後 10:跨VS 11:frame中       
		15 00 02 36 00
		15 00 02 37 08       //GCH/L
		15 00 02 38 3C	    //VDD1&2 toggle 1sec
		15 00 02 39 00
		15 00 02 3a 00 
		15 00 02 3b 00
		15 00 02 3c 00
		15 00 02 3d 00
		15 00 02 3e 00
		15 00 02 3f 00
		15 00 02 40 00
		15 00 02 41 00
		15 00 02 42 00
		15 00 02 43 08       //GCH/L
		15 00 02 44 00


		15 00 02 50 01       //GIP_2
		15 00 02 51 23
		15 00 02 52 45
		15 00 02 53 67
		15 00 02 54 89
		15 00 02 55 ab
		15 00 02 56 01
		15 00 02 57 23
		15 00 02 58 45
		15 00 02 59 67
		15 00 02 5a 89
		15 00 02 5b ab
		15 00 02 5c cd
		15 00 02 5d ef

							   
		15 00 02 5e 00     //GIP_3
		15 00 02 5f 01     //FW_CGOUT_L[1]    VDS
		15 00 02 60 01     //FW_CGOUT_L[2]    VDS
		15 00 02 61 06     //FW_CGOUT_L[3]    STV2
		15 00 02 62 06     //FW_CGOUT_L[4]    STV2
		15 00 02 63 06     //FW_CGOUT_L[5]    STV4
		15 00 02 64 06     //FW_CGOUT_L[6]    STV4
		15 00 02 65 00     //FW_CGOUT_L[7]    VSD
		15 00 02 66 00     //FW_CGOUT_L[8]    VSD
		15 00 02 67 17     //FW_CGOUT_L[9]    GCL
		15 00 02 68 02     //FW_CGOUT_L[10]   
		15 00 02 69 16     //FW_CGOUT_L[11]   GCH  
		15 00 02 6a 16     //FW_CGOUT_L[12]   GCH
		15 00 02 6b 02     //FW_CGOUT_L[13]   
		15 00 02 6c 0D     //FW_CGOUT_L[14]   CLK8   
		15 00 02 6d 0D     //FW_CGOUT_L[15]   CLK8
		15 00 02 6e 0C     //FW_CGOUT_L[16]   CLK6    
		15 00 02 6f 0C     //FW_CGOUT_L[17]   CLK6
		15 00 02 70 0F     //FW_CGOUT_L[18]   CLK4
		15 00 02 71 0F     //FW_CGOUT_L[19]   CLK4
		15 00 02 72 0E     //FW_CGOUT_L[20]   CLK2
		15 00 02 73 0E     //FW_CGOUT_L[21]   CLK2
		15 00 02 74 02     //FW_CGOUT_L[22]   VGL
		  
		15 00 02 75 01     //BW_CGOUT_L[1]   
		15 00 02 76 01     //BW_CGOUT_L[2]    
		15 00 02 77 06     //BW_CGOUT_L[3]    
		15 00 02 78 06     //BW_CGOUT_L[4]    
		15 00 02 79 06     //BW_CGOUT_L[5]     
		15 00 02 7a 06     //BW_CGOUT_L[6]     
		15 00 02 7b 00     //BW_CGOUT_L[7]   
		15 00 02 7c 00     //BW_CGOUT_L[8]    
		15 00 02 7d 17     //BW_CGOUT_L[9]      
		15 00 02 7e 02     //BW_CGOUT_L[10]
		15 00 02 7f 16     //BW_CGOUT_L[11]    
		15 00 02 80 16     //BW_CGOUT_L[12]   
		15 00 02 81 02     //BW_CGOUT_L[13] 
		15 00 02 82 0D     //BW_CGOUT_L[14]      
		15 00 02 83 0D     //BW_CGOUT_L[15]   
		15 00 02 84 0C     //BW_CGOUT_L[16]      
		15 00 02 85 0C     //BW_CGOUT_L[17]
		15 00 02 86 0F     //BW_CGOUT_L[18]
		15 00 02 87 0F     //BW_CGOUT_L[19]
		15 00 02 88 0E     //BW_CGOUT_L[20]   
		15 00 02 89 0E     //BW_CGOUT_L[21]   
		15 00 02 8A 02     //BW_CGOUT_L[22]   

									  
		39 00 04 FF 98 81 04      //CMD_Page 4
		15 00 02 6E 2B           //VGH 15V
		15 00 02 6F 35           //37           // reg vcl + pumping ratio VGH=3x VGL=-2.5x
		15 00 02 3A A4           //POWER SAVING
		15 00 02 8D 1A           //VGL -11V
		15 00 02 87 BA           //ESD
		15 00 02 B2 D1
		15 00 02 88 0B
		15 00 02 38 01      
		15 00 02 39 00
		15 00 02 B5 07           //gamma bias
		15 00 02 31 75
		15 00 02 3B 98  			
					
									
		39 00 04 FF 98 81 01       //CMD_Page 1
		15 00 02 22 0A             //BGR, SS
		15 00 02 31 00             //Column inversion
		//15 00 02 53 40          //VCOM1
		//15 00 02 55 40          //VCOM2 
		15 00 02 50 95          //VREG1OUT 4.5V
		15 00 02 51 90          //VREG2OUT -4.5V
		15 00 02 60 22          //06          //SDT
		15 00 02 62 20          //============Gamma START=============
									 
								   
		15 00 02 A0 00          //Pos Register
		15 00 02 A1 1B
		15 00 02 A2 2A
		15 00 02 A3 14
		15 00 02 A4 17
		15 00 02 A5 2B
		15 00 02 A6 1F
		15 00 02 A7 20
		15 00 02 A8 93
		15 00 02 A9 1E
		15 00 02 AA 2A
		15 00 02 AB 7E
		15 00 02 AC 1B
		15 00 02 AD 19
		15 00 02 AE 4C
		15 00 02 AF 22
		15 00 02 B0 28
		15 00 02 B1 4B
		15 00 02 B2 59
		15 00 02 B3 23

								   
		15 00 02 C0 00          //Neg Register
		15 00 02 C1 1B
		15 00 02 C2 2A
		15 00 02 C3 14
		15 00 02 C4 17
		15 00 02 C5 2B
		15 00 02 C6 1F
		15 00 02 C7 20
		15 00 02 C8 93
		15 00 02 C9 1E
		15 00 02 CA 2A
		15 00 02 CB 7E
		15 00 02 CC 1B
		15 00 02 CD 19
		15 00 02 CE 4C
		15 00 02 CF 22
		15 00 02 D0 28
		15 00 02 D1 4B
		15 00 02 D2 59
		15 00 02 D3 23           //============ Gamma END===========	
								
		39 00 04 FF 98 81 00      //CMD_Page 0	
		15 00 02 11 00
		15 78 02 00 00
		15 00 02 29 00
		15 05 02 00 00

		];
		panel-exit-sequence = [
			 05 05 01 28
             05 78 01 10
		];
		

		display_timings: display-timings {
			native-mode = <&timing0>;
			compatible = "rockchip,display-timings";
			timing0: timing0 {
				clock-frequency = <68000000>;
				hactive = <800>;
				vactive = <1280>;
				hback-porch = <32>;
				hfront-porch = <32>;
				vback-porch = <32>;
				vfront-porch = <22>;
				hsync-len = <4>;
				vsync-len = <4>;
				
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <0>;
				pixelclk-active = <0>;
			};
		};
	};
};