mips-gcc options

3.17.26 MIPS Options

-EB

Generate big-endian code. 

-EL

Generate little-endian code. This is the default for `mips*el-*-*'configurations. 

-march=arch

Generate code that runs on arch, which can be the name of ageneric MIPS ISA, or the name of a particular processor. The ISA names are:`mips1', `mips2', `mips3', `mips4',`mips32', `mips32r2', `mips64' and `mips64r2'. The processor names are:`4kc', `4km', `4kp', `4ksc',`4kec', `4kem', `4kep', `4ksd',`5kc', `5kf',`20kc',`24kc', `24kf2_1', `24kf1_1',`24kec', `24kef2_1', `24kef1_1',`34kc', `34kf2_1', `34kf1_1', `34kn',`74kc', `74kf2_1', `74kf1_1', `74kf3_2',`1004kc', `1004kf2_1', `1004kf1_1',`loongson2e', `loongson2f', `loongson3a',`m4k',`octeon', `octeon+', `octeon2',`orion',`r2000', `r3000', `r3900', `r4000', `r4400',`r4600', `r4650', `r6000', `r8000',`rm7000', `rm9000',`r10000', `r12000', `r14000', `r16000',`sb1',`sr71000',`vr4100', `vr4111', `vr4120', `vr4130', `vr4300',`vr5000', `vr5400', `vr5500',`xlr' and `xlp'. The special value `from-abi' selects themost compatible architecture for the selected ABI (that is,`mips1' for 32-bit ABIs and `mips3' for 64-bit ABIs).

The native Linux/GNU toolchain also supports the value `native',which selects the best architecture option for the host processor. -march=native has no effect if GCC does not recognizethe processor.

In processor names, a final `000' can be abbreviated as `k'(for example, -march=r2k). Prefixes are optional, and`vr' may be written `r'.

Names of the form `nf2_1' refer to processors withFPUs clocked at half the rate of the core, names of the form`nf1_1' refer to processors with FPUs clocked at the samerate as the core, and names of the form `nf3_2' refer toprocessors with FPUs clocked a ratio of 3:2 with respect to the core. For compatibility reasons, `nf' is accepted as a synonymfor `nf2_1' while `nx' and `bfx' areaccepted as synonyms for `nf1_1'.

GCC defines two macros based on the value of this option. The firstis `_MIPS_ARCH', which gives the name of target architecture, asa string. The second has the form `_MIPS_ARCH_foo',where foo is the capitalized value of `_MIPS_ARCH'. For example, -march=r2000 sets `_MIPS_ARCH'to `"r2000"' and defines the macro `_MIPS_ARCH_R2000'.

Note that the `_MIPS_ARCH' macro uses the processor names givenabove. In other words, it has the full prefix and does notabbreviate `000' as `k'. In the case of `from-abi',the macro names the resolved architecture (either `"mips1"' or`"mips3"'). It names the default architecture when no-march option is given. 

-mtune=arch

Optimize for arch. Among other things, this option controlsthe way instructions are scheduled, and the perceived cost of arithmeticoperations. The list of arch values is the same as for-march.

When this option is not used, GCC optimizes for the processorspecified by -march. By using -march and-mtunetogether, it is possible to generate code thatruns on a family of processors, but optimize the code for oneparticular member of that family.

-mtune defines the macros `_MIPS_TUNE' and`_MIPS_TUNE_foo', which work in the same way as the-march ones described above. 

-mips1

Equivalent to -march=mips1. 

-mips2

Equivalent to -march=mips2. 

-mips3

Equivalent to -march=mips3. 

-mips4

Equivalent to -march=mips4. 

-mips32

Equivalent to -march=mips32. 

-mips32r2

Equivalent to -march=mips32r2. 

-mips64

Equivalent to -march=mips64. 

-mips64r2

Equivalent to -march=mips64r2. 

-mips16

-mno-mips16

Generate (do not generate) MIPS16 code. If GCC is targeting aMIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE.

MIPS16 code generation can also be controlled on a per-function basisby means of mips16 and nomips16attributes. See Function Attributes, for more information. 

-mflip-mips16

Generate MIPS16 code on alternating functions. This option is providedfor regression testing of mixed MIPS16/non-MIPS16 code generation, and isnot intended for ordinary use in compiling user code. 

-minterlink-mips16

-mno-interlink-mips16

Require (do not require) that non-MIPS16 code be link-compatible withMIPS16 code.

For example, non-MIPS16 code cannot jump directly to MIPS16 code;it must either use a call or an indirect jump.-minterlink-mips16therefore disables direct jumps unless GCC knows that the target of thejump is not MIPS16. 

-mabi=32

-mabi=o64

-mabi=n32

-mabi=64

-mabi=eabi

Generate code for the given ABI.

Note that the EABI has a 32-bit and a 64-bit variant. GCC normallygenerates 64-bit code when you select a 64-bit architecture, but youcan use -mgp32 to get 32-bit code instead.

For information about the O64 ABI, seehttp://gcc.gnu.org/projects/mipso64-abi.html.

GCC supports a variant of the o32 ABI in which floating-point registersare 64 rather than 32 bits wide. You can select this combination with-mabi=32 -mfp64. This ABI relies on the mthc1and mfhc1 instructions and is therefore only supported forMIPS32R2 processors.

The register assignments for arguments and return values remain thesame, but each scalar value is passed in a single 64-bit registerrather than a pair of 32-bit registers. For example, scalarfloating-point values are returned in `$f0' only, not a`$f0'/`$f1' pair. The set of call-saved registers alsoremains the same, but all 64 bits are saved. 

-mabicalls

-mno-abicalls

Generate (do not generate) code that is suitable for SVR4-styledynamic objects. -mabicalls is the default for SVR4-basedsystems. 

-mshared

-mno-shared

Generate (do not generate) code that is fully position-independent,and that can therefore be linked into shared libraries. This optiononly affects -mabicalls.

All -mabicalls code has traditionally been position-independent,regardless of options like -fPIC and -fpic. However,as an extension, the GNU toolchain allows executables to use absoluteaccesses for locally-binding symbols. It can also use shorter GPinitialization sequences and generate direct calls to locally-definedfunctions. This mode is selected by -mno-shared.

-mno-shared depends on binutils 2.16 or higher and generatesobjects that can only be linked by the GNU linker. However, the optiondoes not affect the ABI of the final executable; it only affects the ABIof relocatable objects. Using -mno-shared generally makesexecutables both smaller and quicker.

-mshared is the default. 

-mplt

-mno-plt

Assume (do not assume) that the static and dynamic linkerssupport PLTs and copy relocations. This option only affects-mno-shared -mabicalls. For the n64 ABI, this optionhas no effect without -msym32.

You can make -mplt the default by configuringGCC with --with-mips-plt. The default is-mno-plt otherwise. 

-mxgot

-mno-xgot

Lift (do not lift) the usual restrictions on the size of the globaloffset table.

GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOTis smaller than about 64k. Anything larger causes the linkerto report an error such as:

          relocation truncated to fit: R_MIPS_GOT16 foobar
     

If this happens, you should recompile your code with -mxgot. This works with very large GOTs, although the code is alsoless efficient, since it takes three instructions to fetch thevalue of a global symbol.

Note that some linkers can create multiple GOTs. If you have such alinker, you should only need to use -mxgotwhen a single objectfile accesses more than 64k's worth of GOT entries. Very few do.

These options have no effect unless GCC is generating positionindependent code. 

-mgp32

Assume that general-purpose registers are 32 bits wide. 

-mgp64

Assume that general-purpose registers are 64 bits wide. 

-mfp32

Assume that floating-point registers are 32 bits wide. 

-mfp64

Assume that floating-point registers are 64 bits wide. 

-mhard-float

Use floating-point coprocessor instructions. 

-msoft-float

Do not use floating-point coprocessor instructions. Implementfloating-point calculations using library calls instead. 

-mno-float

Equivalent to -msoft-float, but additionally asserts that theprogram being compiled does not perform any floating-point operations. This option is presently supported only by some bare-metal MIPSconfigurations, where it may select a special set of librariesthat lack all floating-point support (including, for example, thefloating-point printf formats). If code compiled with -mno-float accidentally containsfloating-point operations, it is likely to suffer a link-timeor run-time failure. 

-msingle-float

Assume that the floating-point coprocessor only supports single-precisionoperations. 

-mdouble-float

Assume that the floating-point coprocessor supports double-precisionoperations. This is the default. 

-mllsc

-mno-llsc

Use (do not use) `ll', `sc', and `sync' instructions toimplement atomic memory built-in functions. When neither option isspecified, GCC uses the instructions if the target architecturesupports them.

-mllsc is useful if the runtime environment can emulate theinstructions and -mno-llsc can be useful when compiling fornonstandard ISAs. You can make either option the default byconfiguring GCC with --with-llsc and --without-llscrespectively. --with-llsc is the default for someconfigurations; see the installation documentation for details. 

-mdsp

-mno-dsp

Use (do not use) revision 1 of the MIPS DSP ASE. See MIPS DSP Built-in Functions. This option defines thepreprocessor macro `__mips_dsp'. It also defines`__mips_dsp_rev' to 1. 

-mdspr2

-mno-dspr2

Use (do not use) revision 2 of the MIPS DSP ASE. See MIPS DSP Built-in Functions. This option defines thepreprocessor macros `__mips_dsp' and `__mips_dspr2'. It also defines `__mips_dsp_rev' to 2. 

-msmartmips

-mno-smartmips

Use (do not use) the MIPS SmartMIPS ASE. 

-mpaired-single

-mno-paired-single

Use (do not use) paired-single floating-point instructions. See MIPS Paired-Single Support. This option requireshardware floating-point support to be enabled. 

-mdmx

-mno-mdmx

Use (do not use) MIPS Digital Media Extension instructions. This option can only be used when generating 64-bit code and requireshardware floating-point support to be enabled. 

-mips3d

-mno-mips3d

Use (do not use) the MIPS-3D ASE. See MIPS-3D Built-in Functions. The option -mips3d implies -mpaired-single. 

-mmt

-mno-mt

Use (do not use) MT Multithreading instructions. 

-mmcu

-mno-mcu

Use (do not use) the MIPS MCU ASE instructions. 

-mlong64

Force long types to be 64 bits wide. See -mlong32 foran explanation of the default and the way that the pointer size isdetermined.

-mlong32

Force long, int, and pointer types to be 32 bits wide.

The default size of ints, longs and pointers depends onthe ABI. All the supported ABIs use 32-bit ints. The n64 ABIuses 64-bit longs, as does the 64-bit EABI; the others use32-bit longs. Pointers are the same size as longs,or the same size as integer registers, whichever is smaller. 

-msym32

-mno-sym32

Assume (do not assume) that all symbols have 32-bit values, regardlessof the selected ABI. This option is useful in combination with-mabi=64 and -mno-abicalls because it allows GCCto generate shorter and faster references to symbolic addresses. 

-G num

Put definitions of externally-visible data in a small data sectionif that data is no bigger than num bytes. GCC can then generatemore efficient accesses to the data; see -mgpopt for details.

The default -G option depends on the configuration. 

-mlocal-sdata

-mno-local-sdata

Extend (do not extend) the -G behavior to local data too,such as to static variables in C. -mlocal-sdata is thedefault for all configurations.

If the linker complains that an application is using too much small data,you might want to try rebuilding the less performance-critical parts with-mno-local-sdata. You might also want to build largelibraries with -mno-local-sdata, so that the libraries leavemore room for the main program. 

-mextern-sdata

-mno-extern-sdata

Assume (do not assume) that externally-defined data is ina small data section if the size of that data is within the -G limit. -mextern-sdata is the default for all configurations.

If you compile a module Mod with -mextern-sdata -Gnum -mgpopt, and Mod references a variable Varthat is no bigger than num bytes, you must make sure that Varis placed in a small data section. If Var is defined by anothermodule, you must either compile that module with a high-enough-G setting or attach a section attribute to Var'sdefinition. If Var is common, you must link the applicationwith a high-enough -G setting.

The easiest way of satisfying these restrictions is to compileand link every module with the same -G option. However,you may wish to build a library that supports several differentsmall data limits. You can do this by compiling the library withthe highest supported -G setting and additionally using-mno-extern-sdata to stop the library from making assumptionsabout externally-defined data. 

-mgpopt

-mno-gpopt

Use (do not use) GP-relative accesses for symbols that are known to bein a small data section; see -G, -mlocal-sdata and-mextern-sdata. -mgpopt is the default for allconfigurations.

-mno-gpopt is useful for cases where the $gp registermight not hold the value of _gp. For example, if the code ispart of a library that might be used in a boot monitor, programs thatcall boot monitor routines pass an unknown value in $gp. (In such situations, the boot monitor itself is usually compiledwith -G0.)

-mno-gpopt implies -mno-local-sdata and-mno-extern-sdata. 

-membedded-data

-mno-embedded-data

Allocate variables to the read-only data section first if possible, thennext in the small data section if possible, otherwise in data. This givesslightly slower code than the default, but reduces the amount of RAM requiredwhen executing, and thus may be preferred for some embedded systems. 

-muninit-const-in-rodata

-mno-uninit-const-in-rodata

Put uninitialized const variables in the read-only data section. This option is only meaningful in conjunction with -membedded-data. 

-mcode-readable=setting

Specify whether GCC may generate code that reads from executable sections. There are three possible settings:

-mcode-readable=yes

Instructions may freely access executable sections. This is thedefault setting. 

-mcode-readable=pcrel

MIPS16 PC-relative load instructions can access executable sections,but other instructions must not do so. This option is useful on 4KScand 4KSd processors when the code TLBs have the Read Inhibit bit set. It is also useful on processors that can be configured to have a dualinstruction/data SRAM interface and that, like the M4K, automaticallyredirect PC-relative loads to the instruction RAM. 

-mcode-readable=no

Instructions must not access executable sections. This option can beuseful on targets that are configured to have a dual instruction/dataSRAM interface but that (unlike the M4K) do not automatically redirectPC-relative loads to the instruction RAM.

 

-msplit-addresses

-mno-split-addresses

Enable (disable) use of the %hi() and %lo() assemblerrelocation operators. This option has been superseded by-mexplicit-relocsbut is retained for backwards compatibility. 

-mexplicit-relocs

-mno-explicit-relocs

Use (do not use) assembler relocation operators when dealing with symbolicaddresses. The alternative, selected by -mno-explicit-relocs,is to use assembler macros instead.

-mexplicit-relocs is the default if GCC was configuredto use an assembler that supports relocation operators. 

-mcheck-zero-division

-mno-check-zero-division

Trap (do not trap) on integer division by zero.

The default is -mcheck-zero-division. 

-mdivide-traps

-mdivide-breaks

MIPS systems check for division by zero by generating either aconditional trap or a break instruction. Using traps results insmaller code, but is only supported on MIPS II and later. Also, someversions of the Linux kernel have a bug that prevents trap fromgenerating the proper signal (SIGFPE). Use -mdivide-traps toallow conditional traps on architectures that support them and-mdivide-breaks to force the use of breaks.

The default is usually -mdivide-traps, but this can beoverridden at configure time using --with-divide=breaks. Divide-by-zero checks can be completely disabled using-mno-check-zero-division. 

-mmemcpy

-mno-memcpy

Force (do not force) the use of memcpy() for non-trivial blockmoves. The default is -mno-memcpy, which allows GCC to inlinemost constant-sized copies. 

-mlong-calls

-mno-long-calls

Disable (do not disable) use of the jal instruction. Callingfunctions using jal is more efficient but requires the callerand callee to be in the same 256 megabyte segment.

This option has no effect on abicalls code. The default is-mno-long-calls. 

-mmad

-mno-mad

Enable (disable) use of the mad, madu and mulinstructions, as provided by the R4650 ISA. 

-mfused-madd

-mno-fused-madd

Enable (disable) use of the floating-point multiply-accumulateinstructions, when they are available. The default is-mfused-madd.

When multiply-accumulate instructions are used, the intermediateproduct is calculated to infinite precision and is not subject tothe FCSR Flush to Zero bit. This may be undesirable in somecircumstances. 

-nocpp

Tell the MIPS assembler to not run its preprocessor over userassembler files (with a `.s' suffix) when assembling them. 

-mfix-24k

-mno-fix-24k

Work around the 24K E48 (lost data on stores during refill) errata. The workarounds are implemented by the assembler rather than by GCC. 

-mfix-r4000

-mno-fix-r4000

Work around certain R4000 CPU errata:

• A double-word or a variable shift may give an incorrect result if executedimmediately after starting an integer division.
• A double-word or a variable shift may give an incorrect result if executedwhile an integer multiplication is in progress.
• An integer division may give an incorrect result if started in a delay slotof a taken branch or a jump.

 

-mfix-r4400

-mno-fix-r4400

Work around certain R4400 CPU errata:

• A double-word or a variable shift may give an incorrect result if executedimmediately after starting an integer division.

 

-mfix-r10000

-mno-fix-r10000

Work around certain R10000 errata:

• ll/sc sequences may not behave atomically on revisionsprior to 3.0. They may deadlock on revisions 2.6 and earlier.

This option can only be used if the target architecture supportsbranch-likely instructions. -mfix-r10000 is the default when-march=r10000 is used; -mno-fix-r10000 is the defaultotherwise. 

-mfix-vr4120

-mno-fix-vr4120

Work around certain VR4120 errata:

• dmultu does not always produce the correct result.
• div and ddiv do not always produce the correct result if oneof the operands is negative.

The workarounds for the division errata rely on special functions inlibgcc.a. At present, these functions are only provided bythemips64vr*-elf configurations.

Other VR4120 errata require a NOP to be inserted between certain pairs ofinstructions. These errata are handled by the assembler, not by GCC itself. 

-mfix-vr4130

Work around the VR4130 mflo/mfhi errata. Theworkarounds are implemented by the assembler rather than by GCC,although GCC avoids using mflo and mfhi if theVR4130 macc, macchi, dmacc and dmacchiinstructions are available instead. 

-mfix-sb1

-mno-fix-sb1

Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2“F1” and “F2” floating-point errata.) 

-mr10k-cache-barrier=setting

Specify whether GCC should insert cache barriers to avoid theside-effects of speculation on R10K processors.

In common with many processors, the R10K tries to predict the outcomeof a conditional branch and speculatively executes instructions fromthe “taken” branch. It later aborts these instructions if thepredicted outcome is wrong. However, on the R10K, even abortedinstructions can have side effects.

This problem only affects kernel stores and, depending on the system,kernel loads. As an example, a speculatively-executed store may loadthe target memory into cache and mark the cache line as dirty, even ifthe store itself is later aborted. If a DMA operation writes to thesame area of memory before the “dirty” line is flushed, the cacheddata overwrites the DMA-ed data. See the R10K processor manualfor a full description, including other potential problems.

One workaround is to insert cache barrier instructions before every memoryaccess that might be speculatively executed and that might have sideeffects even if aborted. -mr10k-cache-barrier=settingcontrols GCC's implementation of this workaround. It assumes thataborted accesses to any byte in the following regions does not haveside effects:

1. the memory occupied by the current function's stack frame;
2. the memory occupied by an incoming stack argument;
3. the memory occupied by an object with a link-time-constant address.

It is the kernel's responsibility to ensure that speculativeaccesses to these regions are indeed safe.

If the input program contains a function declaration such as:

          void foo (void);
     

then the implementation of foo must allow j foo andjal foo to be executed speculatively. GCC honors thisrestriction for functions it compiles itself. It expects non-GCCfunctions (such as hand-written assembly code) to do the same.

The option has three forms:

-mr10k-cache-barrier=load-store

Insert a cache barrier before a load or store that might bespeculatively executed and that might have side effects evenif aborted. 

-mr10k-cache-barrier=store

Insert a cache barrier before a store that might be speculativelyexecuted and that might have side effects even if aborted. 

-mr10k-cache-barrier=none

Disable the insertion of cache barriers. This is the default setting.

 

-mflush-func=func

-mno-flush-func

Specifies the function to call to flush the I and D caches, or to notcall any such function. If called, the function must take the samearguments as the common _flush_func(), that is, the address of thememory range for which the cache is being flushed, the size of thememory range, and the number 3 (to flush both caches). The defaultdepends on the target GCC was configured for, but commonly is either`_flush_func' or `__cpu_flush'. 

mbranch-cost=num

Set the cost of branches to roughly num “simple” instructions. This cost is only a heuristic and is not guaranteed to produceconsistent results across releases. A zero cost redundantly selectsthe default, which is based on the -mtune setting. 

-mbranch-likely

-mno-branch-likely

Enable or disable use of Branch Likely instructions, regardless of thedefault for the selected architecture. By default, Branch Likelyinstructions may be generated if they are supported by the selectedarchitecture. An exception is for the MIPS32 and MIPS64 architecturesand processors that implement those architectures; for those, BranchLikely instructions are not be generated by default because the MIPS32and MIPS64 architectures specifically deprecate their use. 

-mfp-exceptions

-mno-fp-exceptions

Specifies whether FP exceptions are enabled. This affects howFP instructions are scheduled for some processors. The default is that FP exceptions areenabled.

For instance, on the SB-1, if FP exceptions are disabled, and we are emitting64-bit code, then we can use both FP pipes. Otherwise, we can only use oneFP pipe. 

-mvr4130-align

-mno-vr4130-align

The VR4130 pipeline is two-way superscalar, but can only issue twoinstructions together if the first one is 8-byte aligned. When thisoption is enabled, GCC aligns pairs of instructions that itthinks should execute in parallel.

This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level -O3. 

-msynci

-mno-synci

Enable (disable) generation of synci instructions onarchitectures that support it. The synci instructions (ifenabled) are generated when __builtin___clear_cache() iscompiled.

This option defaults to -mno-synci, but the default can beoverridden by configuring with --with-synci.

When compiling code for single processor systems, it is generally safeto use synci. However, on many multi-core (SMP) systems, itdoes not invalidate the instruction caches on all cores and may leadto undefined behavior. 

-mrelax-pic-calls

-mno-relax-pic-calls

Try to turn PIC calls that are normally dispatched via register$25 into direct calls. This is only possible if the linker canresolve the destination at link-time and if the destination is withinrange for a direct call.

-mrelax-pic-calls is the default if GCC was configured to usean assembler and a linker that support the .relocassemblydirective and -mexplicit-relocs is in effect. With-mno-explicit-relocs, this optimization can be performed by theassembler and the linker alone without help from the compiler. 

-mmcount-ra-address

-mno-mcount-ra-address

Emit (do not emit) code that allows _mcount to modify thecalling function's return address. When enabled, this option extendsthe usual _mcount interface with a new ra-addressparameter, which has type intptr_t * and is passed in register$12. _mcount can then modify the return address bydoing both of the following:

• Returning the new address in register $31.
• Storing the new address in *ra-address,if ra-address is nonnull.

The default is -mno-mcount-ra-address.