Understanding the linux kernel-ch4-Interrupt and exception

IRQs and Interrupts Programmable Interrupt Controller which performs the following actions: 1. Monitors the IRQ lines, checking for raised signals.     If two or more IRQ lines are raised, selects the one having the lower pin number 2. If a raised signal occurs on an IRQ line: a. Converts the raised signal received into a corresponding vector. b. Stores the vector in an Interrupt Controller I/O port,    thus allowing the CPU to read it via the data bus. c.  Sends a raised signal to the processor INTR pinthat is, issues an interrupt. d.  Waits until the CPU acknowledges the interrupt signal    by writing into one of the Programmable Interrupt Controllers (PIC) I/O ports;    when this occurs, clears the INTR line. 3. Goes back to step 1. the IF flag of the eflags register is clear,  each maskable interrupt issued by the PIC is temporarily ignored by the CPU cli and sti assembly language instructions, respectively, clear and set IF flag PIC: Programmable interrupt controller 8259A                                     The Advanced Programmable Interrupt Controller (APIC)
	a new component designated as the I/O Advanced Programmable Interrupt Controller (I/O APIC)
	advanced version of the old 8259A Programmable Interrupt Controller
	local APIC for CUPs		Pentium III
	Many of the current uniprocessor systems include an I/O APIC chip,
	which may be configured in two distinct ways:
	·         As a standard 8259A-style external PIC connected to the CPU.
		The local APIC is disabled and the two LINT 0 and LINT 1 local IRQ lines are configured,
		respectively, as the INTR and NMI pins.
	·         As a standard external I/O APIC. The local APIC is enabled,
		and all external interrupts are received through the I/O APIC
Exceptions
	The 80x86 microprocessors issue roughly 20 different exceptions .
	The kernel must provide a dedicated exception handler for each exception type
	The following list gives the vector, the name, the type,
	and a brief description of the exceptions found in 80x86 processors
	0 - "Divide error" (fault)
	Raised when a program issues an integer division by 0.
	1- "Debug" (trap or fault)
	Raised when the TF flag of eflags is set
	2 - Not used
	Reserved for nonmaskable interrupts (those that use the NMI pin).
	3 - "Breakpoint" (trap)
	Caused by an int3 (breakpoint) instruction
	4 - "Overflow" (trap)
	An into (check for overflow) instruction has been executed while the OF (overflow) flag of eflags is set
	5 - "Bounds check" (fault)
	A bound (check on address bound) instruction is executed
	with the operand outside of the valid address bounds.
	6 - "Invalid opcode" (fault)
	The CPU execution unit has detected an invalid opcode
	(the part of the machine instruction that determines the operation performed)
	7 - "Device not available" (fault)
	An ESCAPE, MMX, or SSE/SSE2 instruction has been executed with the TS flag of cr0 set
	8 - "Double fault" (abort)
	Normally, when the CPU detects an exception while trying to call the handler for a prior exception,
	the two exceptions can be handled serially. In a few cases,
	however, the processor cannot handle them serially, so it raises this exception.
	9 - "Coprocessor segment overrun" (abort)
	Problems with the external mathematical coprocessor (applies only to old 80386 microprocessors)
	10 - "Invalid TSS" (fault)
	The CPU has attempted a context switch to a process having an invalid Task State Segment.
	11 - "Segment not present" (fault)
	A reference was made to a segment not present in memory
	(one in which the Segment-Present flag of the Segment Descriptor was cleared)
	12 - "Stack segment fault" (fault)
	The instruction attempted to exceed the stack segment limit,
	or the segment identified by ss is not present in memory
	13 - "General protection" (fault)
	One of the protection rules in the protected mode of the 80x86 has been violated
	14 - "Page Fault" (fault)
	The addressed page is not present in memory, the corresponding Page Table entry is null,
	or a violation of the paging protection mechanism has occurred
	15 - Reserved by Intel
	16 - "Floating-point error" (fault)
	The floating-point unit integrated into the CPU chip has signaled an error condition,
	such as numeric overflow or division by 0
	17 - "Alignment check" (fault)
	The address of an operand is not correctly aligned
	(for instance, the address of a long integer is not a multiple of 4)
	18 - "Machine check" (abort)
	A machine-check mechanism has detected a CPU or bus error.
	19 - "SIMD floating point exception" (fault)
	The SSE or SSE2 unit integrated in the CPU chip
	has signaled an error condition on a floating-point operation
	The values from 20 to 31 are reserved by Intel for future development
	each exception is handled by a specific exception handler
	which usually sends a Unix signal to the process that caused the exception
Interrupt Descriptor Table
	Interrupt Descriptor Table (IDT ) associates each interrupt or exception vector
	with the address of the corresponding interrupt or exception handler.
	The IDT must be properly initialized before the kernel enables interrupts.
	Each entry corresponds to an interrupt or an exception vector and consists of an 8-byte descriptor.
	Thus, a maximum of 256 x 8 = 2048 bytes are required to store the IDT
	The idtr CPU register allows the IDT to be located anywhere in memory
	lidt
	IDT may include three types of descriptors,that is:
	Task gate
	Includes the TSS selector of the process that must replace the current one when an interrupt signal occurs
	Interrupt gate
	Includes the Segment Selector and the offset inside the segment of an interrupt or exception handler.
	While transferring control to the proper segment, the processor clears the IF flag,
	thus disabling further maskable interrupts
	Trap gate
	Similar to an interrupt gate, except that while transferring control to the proper segment,
	the processor does not modify the IF flag
	Linux uses interrupt gates to handle interrupts and trap gates to handle exceptions
Hardware Handling of Interrupts and Exceptions
	the control unit checks whether an interrupt or an exception occurred
	while the control unit executed the previous instruction.
	If one occurred, the control unit does the following:
	1. Determines the vector i (0  i  255) associated with the interrupt or the exception.
	2. Reads the i th entry of the IDT referred by the idtr register
	3. Gets the base address of the GDT from the gdtr register and looks in the GDT
	to read the Segment Descriptor identified by the selector in the IDT entry.
	This descriptor specifies the base address of the segment
	that includes the interrupt or exception handler
	4. Makes sure the interrupt was issued by an authorized source
	compares Current Privilege Level (CPL) of CS to
	Descriptor Privilege Level (DPL ) of the Segment Descriptor included in the GDT
	compares the CPL with the DPL of the gate descriptor included in the IDT
	5. Checks whether a change of privilege level is taking place that is, if CPL
	is different from the selected Segment Descriptor's DPL. If so,
	the control unit must start using the stack that is associated with the new privilege level.
	It does this by performing the following steps:
	a. Reads the tr register to access the TSS segment of the running process.
	b. Loads the ss and esp registers with the proper values for the stack segment and stack pointer
	associated with the new privilege level. These values are found in the TSS
	c. In the new stack, it saves the previous values of ss and esp, which define t
	he logical address of the stack associated with the old privilege level.
	6. If a fault has occurred, it loads cs and eip with the logical address of the instruction
	that caused the exception so that it can be executed again
	7. Saves the contents of eflags , cs, and eip in the stack.
	8. If the exception carries a hardware error code, it saves it on the stack
	9. Loads cs and eip, respectively, with the Segment Selector and the Offset fields of the Gate Descriptor
	stored in the i th entry of the IDT. These values define the logical address
	of the first instruction of the interrupt or exception handler
	After the interrupt or exception is processed,relinquish control to the interrupted process
	by issuing the iret instruction, which forces the control unit to:
	1. Load the cs, eip, and eflags registers with the values saved on the stack.
	If a hardware error code has been pushed in the stack on top of the eip contents,
	it must be popped before executing iret.
	2. Check whether the CPL of the handler is equal to the value contained in the two
	least significant bits of cs. If so, iret concludes execution; otherwise, go to the next step
	3. Load the ss and esp registers from the stack and
	return to the stack associated with the old privilege level.
	4. Examine the contents of the ds, es, fs, and gs segment registers;
	if any of them contains a selector that refers to a Segment Descriptor whose DPL value
	is lower than CPL, clear the corresponding segment register.