atlas7_gpio_probe
/drivers/pinctrl/sirf/pinctrl-atlas7.c中atlas7_gpio_probe的定义如下:
6003 static int atlas7_gpio_probe(struct platform_device *pdev)
6004 {
6005 printk(KERN_ERR "tom atlas7_gpio_probe\r\n");
6006 struct device_node *np = pdev->dev.of_node;
6007 struct atlas7_gpio_chip *a7gc;
6008 struct gpio_chip *chip;
6009 u32 nbank;
6010 int ret, idx;
6011
6012 ret = of_property_read_u32(np, "gpio-banks", &nbank);
6013 if (ret) {
6014 dev_err(&pdev->dev,
6015 "Could not find GPIO bank info,ret=%d!\n",
6016 ret);
6017 return ret;
6018 }
6019
6020 /* retrieve gpio descriptor data */
6021 a7gc = devm_kzalloc(&pdev->dev, sizeof(*a7gc) +
6022 sizeof(struct atlas7_gpio_bank) * nbank, GFP_KERNEL);
6023 if (!a7gc)
6024 return -ENOMEM;
6025
6026 /* Get Gpio clk */
6027 a7gc->clk = of_clk_get(np, 0);
6028 if (!IS_ERR(a7gc->clk)) {
6029 ret = clk_prepare_enable(a7gc->clk);
6030 if (ret) {
6031 dev_err(&pdev->dev,
6032 "Could not enable clock!\n");
6033 return ret;
6034 }
6035 }
6036
6037 /* Get Gpio Registers */
6038 a7gc->reg = of_iomap(np, 0);
6039
6040 printk(KERN_ERR "tom a7gc->reg=%x %x\r\n",(int*)a7gc->reg,*((int*)a7gc->reg));
6041 if (!a7gc->reg) {
6042 dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
6043 return -ENOMEM;
6044 }
6045
6046 a7gc->nbank = nbank;
6047 spin_lock_init(&a7gc->lock);
6048
6049
6050 /* Setup GPIO Chip */
6051 chip = &a7gc->chip;
6052 chip->request = atlas7_gpio_request;
6053 chip->free = atlas7_gpio_free;
6054 chip->direction_input = atlas7_gpio_direction_input;
6055 chip->get = atlas7_gpio_get_value;
6056 chip->direction_output = atlas7_gpio_direction_output;
6057 chip->set = atlas7_gpio_set_value;
6058 chip->base = -1;
6059 /* Each chip can support 32 pins at one bank */
6060 chip->ngpio = NGPIO_OF_BANK * nbank;
6061 chip->label = kstrdup(np->name, GFP_KERNEL);
6062 chip->of_node = np;
6063 chip->of_gpio_n_cells = 2;
6064 chip->dev = &pdev->dev;
6065
6066 printk(KERN_ERR "tom nbank=%x chip->label=%s chip->ngpio=%x\r\n",nbank,chip->label,chip->ngpio);
6067
6068 /* Add gpio chip to system */
6069 ret = gpiochip_add(chip);
6070 if (ret) {
6071 dev_err(&pdev->dev,
6072 "%s: error in probe function with status %d\n",
6073 np->name, ret);
6074 goto failed;
6075 }
6076
6077 /* Add gpio chip to irq subsystem */
6078 ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip,
6079 0, handle_level_irq, IRQ_TYPE_NONE);
6080 if (ret) {
6081 dev_err(&pdev->dev,
6082 "could not connect irqchip to gpiochip\n");
6083 goto failed;
6084 }
6085
6086 for (idx = 0; idx < nbank; idx++) {
6087 struct gpio_pin_range *pin_range;
6088 struct atlas7_gpio_bank *bank;
6089
6090 bank = &a7gc->banks[idx];
6091 /* Set ctrl registers' base of this bank */
6092 bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
6093
6094 /* Get interrupt number from DTS */
6095 ret = of_irq_get(np, idx);
6096 if (ret == -EPROBE_DEFER) {
6097 dev_err(&pdev->dev,
6098 "Unable to find IRQ number. ret=%d\n", ret);
6099 goto failed;
6100 }
6101 bank->irq = ret;
6102
6103 gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip,
6104 bank->irq, atlas7_gpio_handle_irq);
6105
6106 /* Records gpio_pin_range to a7gc */
6107 list_for_each_entry(pin_range, &chip->pin_ranges, node) {
6108 struct pinctrl_gpio_range *range;
6109
6110 range = &pin_range->range;
6111 if (range->id == NGPIO_OF_BANK * idx) {
6112 bank->gpio_offset = range->id;
6113 bank->ngpio = range->npins;
6114 bank->gpio_pins = range->pins;
6115 bank->pctldev = pin_range->pctldev;
6116 break;
6117 }
6118 }
6119
6120 BUG_ON(!bank->pctldev);
6121 }
6122
6123 platform_set_drvdata(pdev, a7gc);
6124
6125 dev_info(&pdev->dev, "add to system.\n");
6126 return 0;
6127 failed:
6128 return ret;
6129 }
gpiochip_add
223 int gpiochip_add(struct gpio_chip *chip)
224 {
225 unsigned long flags;
226 int status = 0;
227 unsigned id;
228 int base = chip->base;
229
230 if ((!gpio_is_valid(base) || !gpio_is_valid(base + chip->ngpio - 1))
231 && base >= 0) {
232 status = -EINVAL;
233 goto fail;
234 }
235
236 spin_lock_irqsave(&gpio_lock, flags);
237
238 if (base < 0) {
239 base = gpiochip_find_base(chip->ngpio);
240 if (base < 0) {
241 status = base;
242 goto unlock;
243 }
244 chip->base = base;
245 }
246 if(chip->ngpio==0x80)
247 {
248 printk(KERN_ERR "tom chip->base=%d\r\n",chip->base);
249 }
250
251 status = gpiochip_add_to_list(chip);
252
253 if (status == 0) {
254 chip->desc = &gpio_desc[chip->base];
255
256 for (id = 0; id < chip->ngpio; id++) {
257 struct gpio_desc *desc = &chip->desc[id];
258 desc->chip = chip;
259
260 /* REVISIT: most hardware initializes GPIOs as
261 * inputs (often with pullups enabled) so power
262 * usage is minimized. Linux code should set the
263 * gpio direction first thing; but until it does,
264 * and in case chip->get_direction is not set,
265 * we may expose the wrong direction in sysfs.
266 */
267 desc->flags = !chip->direction_input
268 ? (1 << FLAG_IS_OUT)
269 : 0;
270 }
271 }
272
273 spin_unlock_irqrestore(&gpio_lock, flags);
274
275 if (status)
276 goto fail;
277
278 #ifdef CONFIG_PINCTRL
279 INIT_LIST_HEAD(&chip->pin_ranges);
280 #endif
281
282 of_gpiochip_add(chip);
283 acpi_gpiochip_add(chip);
284
285 status = gpiochip_export(chip);
286 if (status) {
287 acpi_gpiochip_remove(chip);
288 of_gpiochip_remove(chip);
289 goto fail;
290 }
291
292 pr_debug("%s: registered GPIOs %d to %d on device: %s\n", __func__,
293 chip->base, chip->base + chip->ngpio - 1,
294 chip->label ? : "generic");
295
296 return 0;
297
298 unlock:
299 spin_unlock_irqrestore(&gpio_lock, flags);
300 fail:
301 /* failures here can mean systems won't boot... */
302 pr_err("%s: GPIOs %d..%d (%s) failed to register\n", __func__,
303 chip->base, chip->base + chip->ngpio - 1,
304 chip->label ? : "generic");
305 return status;
306 }
of_gpiochip_add
ddd
686
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