uboot关闭看门狗和中断---嵌入式回归第八篇

上一节中根据uboot架构分析我们第一步设置系统为SVC模式，这一小节根据架构设计步骤来关闭看门狗和屏蔽中断！（架构中的第二步和第三步）

相信做嵌入式这行的对看门狗都不陌生！

1. 看门狗的作用：在嵌入式领域，有些系统需要长期运行在无人看守的环境。在运行过程中，难免不出现系统死机的情况，这时就需要系统自身带有一种自动重启的功能。watchdog一般就是一个硬件模块，其作用就是在系统死机时帮助系统实现自动重启。

2. 看门狗的工作方式：watchdog在硬件上实现了计时功能，启动计时后，用户软件必须在计时结束前重新开始计时，俗称“喂狗”，如果到超时的时候还没有重新开始计时，那么它就认为系统是死机了，就自动重启系统。

这里贴上6410 Watchdog ARM芯片手册上看门狗部分的英文原版！

34  WATCHDOG TIMER 
This chapter describes the functions and usage of Watchdog Timer in S3C6410X RISC microprocessor.  
 
34.1 OVERVIEW  
The S3C6410X RISC microprocessor watchdog timer is used to resume the controller operation whenever it is 
disturbed by malfunctions such as noise and system errors. The watchdog timer generates the reset signal.          
It can be used as a normal 16-bit interval timer to request interrupt service.  
Advantage in using WDT instead of PWM timer is that WDT generates the reset signal.  
 
34.2 FEATURES   
The Watchdog Timer includes the following features:  
• 
Normal interval timer mode with interrupt request. 
• 
Internal reset signal is activated when the timer count value reaches 0 (time-out).  
• 
Level-triggered Interrupt mechanism. 

34.3 FUNCTIONAL DESCRIPTION   
34.3.1 WATCHDOG TIMER OPERATION  
Figure 34-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its 
source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the 
resulting frequency is divided again.  

下面的一张图可以分为三个部分：

1. 时钟源PCLK ，分频器将时钟源分频出来的时钟就是Watchdog所用的时钟！

2. 计数逻辑模块，减1操作，设置一个时间， 会一直减减，所以一定时间要定时重新设置新值

3.  减到0时会产生一个信号 Reset Signal Generator--->RESET

一般uboot程序比较简单，所以一开始都是把watchdog关闭

The prescaler value and the frequency division factor are specified in the watchdog timer control (WTCON) 
register. Valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64, 
or 128. 
Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock 
cycle: 
            t_watchdog  = 1/( PCLK / (Prescaler value + 1) / Division_factor ) 
 
34.3.2 WTDAT & WTCNT  
Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically 
reloaded into the timer counter (WTCNT). For this reason, an initial value must be written to the watchdog timer 
count (WTCNT) register, before the watchdog timer starts.  
 
34.3.3 CONSIDERATION OF DEBUGGING ENVIRONMENT  
When the S3C6410 is in debug mode using Embedded ICE, the watchdog timer must not operate.  
The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal 
(DBGACK signal). Once the DBGACK signal is asserted, the reset output of the watchdog timer is not activated as 
the watchdog timer is expired. 

34.4 SPECIAL FUNCTION REGISTER 
34.4.1 MEMORY MAP  
  

34.5 INDIVIDUAL REGISTER DESCRIPTION 
34.5.1 WATCHDOG TIMER CONTROL (WTCON) REGISTER  
The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different 
sources, enable/disable interrupts, and enable/disable the watchdog timer output.  
The Watchdog timer is used to resume the S3C6410 restart on mal-function after its power on. At this time, 
disable the interrupt generation and enable the Watchdog timer output for reset signal.  
If controller restart is not desired and if the user wants to use the normal timer only, which is provided by the 
Watchdog timer, enable the interrupt generation and disable the Watchdog timer output for reset signal.  

从下面的表格可以看出：WTCON可以控制watchdog的开关，看下面的表格设置第0位为0就disable了看门狗

1. 设置那个寄存器， 寄存器地址
2. 设置寄存器哪一位可以关闭看门狗

3. 然后用代码实现

Note: Initial state of ‘Reset enable/disable’ is 1(reset enable). If user do not disable this bit, S3C6410 will be 
rebooted in about 5.63sec (In the case of PCLK is 12MHz). So at boot loader, this bit should be disabled before 
under control of Operating System, or Firmware. 

这后面的可以先了解一下，这里暂时用不到！
34.5.2 WATCHDOG TIMER DATA (WTDAT) REGISTER  
The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically 
loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value of WTCNT) 
will drive the first time-out. Then, the value of WTDAT will be automatically reloaded into WTCNT.  

34.5.3 WATCHDOG TIMER COUNT (WTCNT) REGISTER   
The WTCNT register contains the current count values for the watchdog timer during normal operation.  
NOTE:  
The content of the WTDAT register cannot be automatically loaded into the timer count register when the 
watchdog timer is enabled initially, so the WTCNT register must be set to an initial value before enabling 
it. 

接着上一课， 这里贴上关闭Watchdog的汇编代码（OK6410）

<span style="font-size:18px;">reset:
		bl set_svc
		bl disable_watchdog
		
set_svc:
		mrs r0, cpsr
		bic r0, r0, #0x1f   @后5位清零
		orr r0, r0, #0xd3   @相应位置1 10011
		msr cpsr, r0 @写入GPSR寄存器
		mov pc, lr 

#define pWTCON 0x7e004000 @watchdog CON寄存器地址
disable_watchdog:
		ldr r0, =pWTCON @将地址装载到通用寄存器
		mov r1, #0x0 @将0传到r1寄存器中
		str r1, [r0] @将值传到到寄存器地址所在的内存中
		mov pc, lr</span>

下面来关闭中断部分：（还是看datasheet）

6410采用的是中断向量的方式，采用硬件自动跳转！

关闭中断分为两个环节：

1.  CPSR寄存器I 位控制中断， 还有F位控制快速中断， 这里其实在设置SVC模式时就附带做了！这里可以在前面的博文中找到CPSR寄存器手册截图！（看看可以前后连接起来）

2. 还需要设置中断屏蔽寄存器

同上面一样，先找到那个寄存器，然后寄存器要设置什么值，从下面手册上的截图表格最后一行可以看到Interupt Enable Register 就是我们要找的

从datasheet中找到这个寄存器：

这里可以看到6410的中断分为两组，VIC0和VIC1， 下面来看看这两个寄存器的描述！中断使能寄存器

从上面的表格看到，这里这个寄存器只能使能中断，要屏蔽中断要使用VICINTENCLEAR寄存器

下面再来看看VICINTENCLEAR寄存器：

写0是no effect, 看上面的截图可以看出要向两个寄存器中写入全1

这里贴上代码，还是在之前的博文上start.S基础上加上这部分的代码！

reset:
		bl set_svc
		bl disable_watchdog
		bl disable_interrupt
		
set_svc:
		mrs r0, cpsr
		bic r0, r0, #0x1f   @后5位清零
		orr r0, r0, #0xd3   @相应位置1 10011
		msr cpsr, r0 @写入GPSR寄存器
		mov pc, lr 

#define pWTCON 0x7e004000 @watchdog CON寄存器地址
disable_watchdog:
		ldr r0, =pWTCON @将地址装载到通用寄存器
		mov r1, #0x0 @将0传到r1寄存器中
		str r1, [r0] @将值传到到寄存器地址所在的内存中
		mov pc, lr
		
disable_interrupt:
	mvn r1,#0x0 @写入全1 取反然后填入到r1寄存器中
	ldr r0,=0x71200014 @用r0保存地址
	str r1,[r0] @然后将r1中的值写入到ro地址中去

	ldr r0,=0x71300014
	str r1,[r0]
	mov pc, lr