串口传输输入输出不一致_计算机科学组织| 输入和输出传输模式

串口传输输入输出不一致

输入输出传输方式 (Input output transfer mode)

There are three kinds of transfer mode present to transfer the data from input out devices to other components of the computer system.

存在三种传输模式 ，用于将数据从输入输出设备传输到计算机系统的其他组件。

1. Programmed IO

   编程的IO

2. Interrupt initiated I/O

   中断启动的I / O

3. Direct Memory access

   直接内存访问

1)编程的I / O (1) Programmed I/O)

In this mode, input-output devices are directly connected with the system BUS that means no interface is used between the CPU and Input-output devices. Therefore the CPU performed will be degraded. In this mode CPU time is directly depending on the speed of the input-output devices that means until completion of an IO operation processor is there is waiting for the state.

在此模式下，输入输出设备直接与系统BUS连接，这意味着CPU与输入输出设备之间不使用任何接口。 因此，执行的CPU将降级。 在这种模式下，CPU时间直接取决于输入输出设备的速度，这意味着直到IO操作处理器完成才等待该状态。

When the 1 KBPS device is connected to the CPU in the programmed IO mode to transfer the data byte by byte. Once byte transfer takes 1 millisecond, therefore, processor time will be wasted.

当以编程的IO模式将1 KBPS设备连接到CPU以逐字节传输数据时。 因此，一旦字节传输需要1毫秒，则将浪费处理器时间。

2)中断启动的I / O (2) Interrupt Initiated I/O)

In this mode, high-speed interface is used between the CPU and IO devices. Therefore processor utilization is efficient. In this mode, the CPU time is depending on the latency of the interface rather than the speed of the input-output devices.

在此模式下，CPU和IO设备之间使用高速接口。 因此，处理器利用率很高。 在这种模式下，CPU时间取决于接口的等待时间，而不取决于输入输出设备的速度。

In this mode, the interrupt controller is used as the high-speed interface logic to control the IO devices operation. Interrupt controller is a programmable interface so in the single mode configuration 8 IO devices are possible and in the cascading mode configuration maximum 64 IO devices are connected to the CPU by using the interrupt controller interface.

在此模式下，中断控制器用作高速接口逻辑，以控制IO设备的操作。 中断控制器是可编程接口，因此在单模式配置中可以使用8个IO设备，而在级联模式配置中，通过使用中断控制器接口，最多可以将64个IO设备连接到CPU。

3)DMA(直接内存访问) (3) DMA (Direct Memory Access))

In this mode bulk amount of data is transferred from the IO to main memory without the involvement of the CPU. When the user program capacity is greater than the main memory capacity then there is a need for increasing the address space.

在这种模式下，大量数据从IO传输到主存储器，而无需CPU的参与。 当用户程序容量大于主存储器容量时，则需要增加地址空间。

Virtual memory concept is used to increase the address space that means using the secondary storage component to store the user program. Secondary storage components are connected to DMA modules. Therefore to execute the user program there is a need to transfer the bulk amount of data from the input-output devices (secondary memory) to main memory through DMA. CPU initiates the DMA module along with the IO address memory address, control signals and count value later CPU is busy with another task.

虚拟内存概念用于增加地址空间，这意味着使用辅助存储组件来存储用户程序。 辅助存储组件连接到DMA模块。 因此，为了执行用户程序，需要通过DMA将大量数据从输入输出设备(辅助存储器)传输到主存储器。 CPU随IO地址存储器地址，控制信号和计数值一起启动DMA模块，之后CPU忙于其他任务。

Direct memory access logic interrupts the request and enables the corresponding port for the respective operation.

直接存储器访问逻辑中断请求并启用相应端口以进行相应操作。

Based on the speed of the disk it prepares the required data. When the data is available in the buffer then DMA enables the hold signal to gain the control of the bus and waiting for the HLDA signals. After receiving the acknowledgment DMA transfers the bulk amount of data to main memory without the involvement of the CPU until the count becomes zero. After the DMA operation, it re-establish the bus connection to the CPU.

根据磁盘的速度，它准备所需的数据。 当缓冲区中的数据可用时，DMA将使保持信号获得对总线的控制权并等待HLDA信号。 收到确认后，DMA将大量数据传输到主存储器，而无需CPU的参与，直到计数变为零为止。 DMA操作之后，它将重新建立与CPU的总线连接。

In the DMA operation CPU is present in two states:

在DMA操作中，CPU处于两种状态：

• Busy state

  忙碌状态

• Blocked state

  封锁状态

CPU is in a busy state until preparing the data therefore busy time is depending on the preparation time of the data. Preparation time is depending on the speed of the disk.

在准备数据之前，CPU处于繁忙状态，因此繁忙时间取决于数据的准备时间。 准备时间取决于磁盘的速度。

CPU is blocked until transferring the data so block time is depending on the transfer time. Transfer time is depending on the Main memory latency.

在传输数据之前，CPU一直处于阻塞状态，因此阻塞时间取决于传输时间。 传输时间取决于主存延迟。

DMA is operated in mainly three modes,

DMA主要以三种模式运行，

1. Burst mode

   突发模式

   In the burst mode of DMA after receiving the HLDA signal bulk amount of data is transferred to main memory.

   在DMA的突发模式下，收到HLDA信号后，大量数据将传输到主存储器。

2. Cycle stealing mode

   循环盗窃模式

   In the cycle stealing mode of DMA before receiving the HLDA signal it forcefully suspends the CPU operation and gains the control of the bus. To transfer a few bytes of the data.

   在DMA的周期窃取模式下，在接收HLDA信号之前，它会强制中止CPU操作并获得总线的控制权。 传输几个字节的数据。

3. Block mode

   阻止模式

   In the locked mode of DMA after receiving HLDA signal data is transferred to main memory blocked buses.

   在DMA的锁定模式下，接收到HLDA信号后，数据将传输到主存储器阻塞的总线。

翻译自: https://www.includehelp.com/cso/input-and-output-transfer-mode.aspx

串口传输输入输出不一致