探秘FPGA内部结构

Max Maxfield
A lot of my friends are highly experienced design engineers, but they come from ASIC or microcontroller backgrounds, so they often have only a vague idea as to what a field-programmable gate array (FPGA) is and what it does. When pressed, they might say something like "You can configure an FPGA to do different things," but they really have no clue as to what's inside an FPGA or how one might be used in a design.









For example, one of our All Programmable Planet bloggers -- Duane Benson -- is an absolute hero with regard to microcontrollers, which he uses in his robot projects, but he doesn’t know anything about programmable devices. The great thing is that Duane has volunteered to learn about FPGAs and to blog about his experiences. (See: Discovering FPGAs: What's This All About?)

I'm going to be complementing Duane's work by explaining the fundamental concepts underpinning programmable devices. In this inaugural Ask Max column, we consider the underlying architecture of one of the original FPGAs -- just what was inside one of these little rascals?

Introducing early programmable FPGA fabric
In the context of an integrated circuit, it's common to hear the term fabric, which is used to refer to the underlying structure of the device. (As a point of interest, the word "fabric" comes from the Middle English fabryke, meaning "something constructed.") Let's start with the core fabric inside an FPGA...

For the purposes of this column, let's assume we're considering one of the earliest FPGA devices. If we were to peer inside the package, we would see its silicon chip (the technical term is the die). The programmable fabric is presented in the form of an array of programmable logic blocks as shown in the image below. If we zoom in with a metaphorical magnifying glass, we see that this fabric comprises "islands" of logic (the programmable logic blocks) basking in a "sea" of programmable interconnect.

A representation of fundamental generic FPGA programmable fabric.

Why yes, I did create this image especially for this blog, and I am rather proud of it -- thank you so much for noticing! If we zoom in further, we see that each of the programmable blocks contains a number of digital functions. In this example we see a 3-input lookup table (LUT), a multiplexer, and a flip-flop, but it's important to realize that the number and types of these functions varies from family to family.

The flip-flop can be configured (programmed) to act as a register or a latch, the multiplexer can be configured to select an input to the block or the output from the LUT, and the LUT can be configured to represent whatever logical function is required. (We will return to consider how this configuration is performed in a future Ask Max.)

The device will also include primary input/output (I/O) pins and pads (not shown in the illustration above). By means of its configuration cells, the interconnect can be programmed such that the primary inputs to the device are connected to the inputs of one or more programmable logic blocks. Also, the outputs from any logic block can be used to drive the inputs to any other logic block and/or the primary outputs from the device.

The very first FPGA was very similar to the architecture discussed in this column. Introduced by Xilinx in 1985, the XC2064 (which was created at the 2µm technology node) contained an 8x8 = 64 array of logic blocks, each containing a 4-input LUT along with some other simple functions.

In future Ask Max blogs I'm going to look at more sophisticated FPGA architectures, how we capture FPGA designs, how we program FPGA devices, what we can use FPGAs for, and all sorts of other things (not least the fact that the FPGA moniker no longer reflects the capabilities and functionality of today's incredibly sophisticated programmable devices). You can use the search box (search for "Ask Max") to find other articles in this series. Also, if you have any questions of your own, you can post them on the All Programmable Planet message boards or you can email me directly at Ask Max.


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