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RSS订阅原创 english note
Since the signal A is asynchronous, a cycle slip here is identical in effect to the signal arriving just after the sampling clock.
2012-11-27 17:59:33
192
原创 csh debug
To show code before execcsh -v script.cshcsh -x script.cshcsh -vx script.cshset echo ...unset echoset verbose..unset verbose
2012-11-02 08:54:04
768
原创 csh
1. get segment of path/fileset path = /export/home/dennis/awb.vecho $path:r/export/home/dennis/awbecho $path:h/export/home/dennis/echo $path:t awb.vecho $path:e.vset path =
2012-10-31 17:13:53
325
原创 sed
1. find and printsed -n ‘/dennis/p' file2. delete line 3 to lastsed '3,$d' file3. substitutesed 's/dennis/Dennis/g' file4. find and substitute with item_dennissed 's/[0-9][0-9]$/&_denn
2012-10-31 00:05:25
137
原创 vi
1. find a word dennis://2. swape from dennis_ic to ic_dennis1:$s/\(dennis\)_\(ic\)/\2_\1/g3. find 55222./5\{2}2\{3\}\./4.
2012-10-30 22:26:04
161
原创 Oct 12, 2012
1. SystemVerilog introduces several 2-state data types to improve simulator performance and reduce memory usage.2. As you employ more static variables, the code manipulate them may grow into a f
2012-10-17 18:41:09
220
原创 svn commands
Following are some useful svn commands:1. svn st [-u -v]: List statuses of local files2. svn diff file.v -r rev1:rev2: Compare file.v of revision rev1 and rev2
2012-10-10 09:18:57
179
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