LDREX and STREX

最近看linux关于atomic的实现的代码(asm/atomic.h)发现大量使用了LDREX和STREX(ARM体系结构)，现将这两个指令的用法总结如下。

详细用法 http://www.keil.com/support/man/docs/armasm/armasm_cihbghef.htm

 

Syntax：

LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
LDREXD{cond} Rt, Rt2, [Rn]
STREXD{cond} Rd, Rt, Rt2, [Rn]

 

LDREX：

LDREX loads data from memory.

If the physical address has the Shared TLB attribute, LDREX tags the physical address as exclusive access for the current processor, and clears any exclusive access tag for this processor for any other physical address.

Otherwise, it tags the fact that the executing processor has an outstanding tagged physical address.

 

STREX：

STREX performs a conditional store to memory. The conditions are as follows:

If the physical address does not have the Shared TLB attribute, and the executing processor has an outstanding tagged physical address, the store takes place, the tag is cleared, and the value 0 is returned in Rd.

If the physical address does not have the Shared TLB attribute, and the executing processor does not have an outstanding tagged physical address, the store does not take place, and the value 1 is returned in Rd.

If the physical address has the Shared TLB attribute, and the physical address is tagged as exclusive access for the executing processor, the store takes place, the tag is cleared, and the value 0 is returned in Rd.

If the physical address has the Shared TLB attribute, and the physical address is not tagged as exclusive access for the executing processor, the store does not take place, and the value 1 is returned in Rd.

 

Usage：

Use LDREX and STREX to implement interprocess communication in multiple-processor and shared-memory systems.

For reasons of performance, keep the number of instructions between corresponding LDREX and STREX instruction to a minimum.

 

Note：

The address used in a STREX instruction must be the same as the address in the most recently executed LDREX instruction. The result of executing a STREX instruction to a different address is unpredictable.

 

Architectures：

ARM LDREX and STREX are available in ARMv6 and above.

ARM LDREXB, LDREXH, LDREXD, STREXB, STREXD, and STREXH are available in ARMv6K and above.

All these 32-bit Thumb instructions are available in ARMv6T2 and above, except that LDREXD and STREXD are not available in the ARMv7-M profile.

There are no 16-bit versions of these instructions.

 

Examples

 

[c-sharp] view plain copy print ?

1. MOV r1, #0x1                ; load the ‘lock taken’ value  
2.   
3. LDREX r0, [LockAddr]        ; load the lock value  
4. CMP r0, #0                  ; is the lock free?  
5. STREXEQ r0, r1, [LockAddr]  ; try and claim the lock  
6. CMPEQ r0, #0                ; did this succeed?  
7. BNE try                     ; no – try again  
8. ....                        ; yes – we have the lock  

MOV r1, #0x1 ; load the ‘lock taken’ value try LDREX r0, [LockAddr] ; load the lock value CMP r0, #0 ; is the lock free? STREXEQ r0, r1, [LockAddr] ; try and claim the lock CMPEQ r0, #0 ; did this succeed? BNE try ; no – try again .... ; yes – we have the lock

 

再看一个linux源代码的例子：

[c-sharp] view plain copy print ?

1. static inline void atomic_set(atomic_t *v, int i)  
2. {  
3.     unsigned long tmp;  
4.   
5.     __asm__ __volatile__("@ atomic_set/n"  
6. "1: ldrex   %0, [%1]/n"  
7. "   strex   %0, %2, [%1]/n"  
8. "   teq %0, #0/n"  
9. "   bne 1b"  
10.     : "=&r" (tmp)  
11.     : "r" (&v->counter), "r" (i)  
12.     : "cc");  
13. }  

static inline void atomic_set(atomic_t *v, int i) { unsigned long tmp; __asm__ __volatile__("@ atomic_set/n" "1: ldrex %0, [%1]/n" " strex %0, %2, [%1]/n" " teq %0, #0/n" " bne 1b" : "=&r" (tmp) : "r" (&v->counter), "r" (i) : "cc"); }

 

输入为v(原子变量)，i(要设置的值)，均存放在动态分配的寄存器中。tmp用来指示操作是否成功。