现在的嵌入式实时系统规模越来越大,很多在linux中使用的特性,例如虚拟内存管理,动态加载等功能也加入进来,进一步增加了RTOS开发的难度.在应用开发中,和cache相关的同步问题有两个,一个是flush操作,另一个是invalidate操作,有时候为了确认问题是否和cache同步有关,需要关闭dcache来验证.这里介绍一种经过验证过的通过页表项关闭DCACHE的实践。
Cortex-A7中启用cache的依赖条件:
在启用cache前,需要设置ACTLR.SMP=1,它表示“Enables coherent requests to the processor", 即使是在单核Cortex-A7上也是如此,详细的解释看arm官方回复:
Even in a single core Cortex-A7 processor the ACTLR.SMP bit must be set. The caches are disabled when ACTLR.SMP is set to 0 regardless of the value of the cache enable bit (SCTLR.C).
It must ensure the ACTLR.SMP bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed. The only time this bit is set to 0 is during a processor power-down sequence.