硬體流程圖
我用de2-150的內部晶片和ADV7123數位轉類比色彩轉化器連接上VGA裝置
軟體流程圖我使用自己寫的除2除頻器，把FPGA內建的50MHz變成25MHz的時鐘,再來自己再寫HSYNC平行信號和VSYNC垂直信號模組,再來用RGB888信號,自己設定想要的顏色，然後設定外部按鈕一按下，螢幕就會換顏色
ＶＧＡ接口只需要注意這五個訊號即可
這五個洞 分別由ADV7123輸入進去
25.2MHz的vga時鐘
0:黑畫面
1:可以顯示圖像
1: 打開 40 IRE 電流源
0:關閉40 IRE電流源
IRE（Institute of Radio Engineers）電視信號品質度量單位，測量視頻信號的亮度級別。IRE值通常在0到100之間，0表示黑色，100表示最大亮度白色。
ADV7123需要用的腳位只有這些 其他忽略即可
螢幕VGA運作原理如圖
VSYNC和HSYNC的原理如圖詳細
行時序的週期基本單位:
一個像素時鐘週期
Pixel clock =25.175MHz=525*800*60
一週期大約40ns
幀時序基本單位:
一個行時序週期
確保適當的同步和排列，以防止圖像扭曲或失真。
包含邊框或其他保留像素，以增強圖像的外觀。
實際顯示的圖像像素
.
如圖示VGA480*640的簡易理解
如圖是信號模組的軟體流程圖
HSYNC跑完800個像素週期
VSYNC就上升高電平
HSYNC跑完525個週期
VSYNC就下降低電平
顏色顯示模組是24位元
143 <= cnt_h < 783
35 <= cnt_v < 515
在這範圍之內
pix_data_req 要等於 1
其餘為0
assign pix_x = (pix_data_req == 1'b1)?
(cnt_h - (H_SYNC + H_BACK + H_LEFT - 1'b1)) : 10'h3ff;
assign pix_y = (pix_data_req == 1'b1)?
(cnt_v - (V_SYNC + V_BACK + V_TOP)) : 10'h3ff;
assign pix_x = (pix_data_req == 1'b1)?
(cnt_h - (H_SYNC + H_BACK + H_LEFT - 1'b1)) : 10'h3ff;
assign pix_y = (pix_data_req == 1'b1)?
(cnt_v - (V_SYNC + V_BACK + V_TOP)) : 10'h3ff;
pix_data_req == 1’b0的時候
Pix_x 跟Pix_y都等於1023
ADV7123採用RGB888
因為像素資料會延遲一個clk才輸出到pix_data
所以沒有rgb_valid 的程式碼沒有-1’b1
但也因為這樣在(pix_x=0 ,pix_y=0)的像素是丟失的
assign rgb_valid = (((cnt_h >= H_SYNC + H_BACK + H_LEFT) && (cnt_h < H_SYNC + H_BACK + H_LEFT + H_VALID))
&&( (cnt_v >= V_SYNC + V_BACK + V_TOP) && (cnt_v < V_SYNC + V_BACK + V_TOP + V_VALID) )
)
? 1'b1 : 1'b0;
assign pix_data_req = (
((cnt_h >= H_SYNC + H_BACK + H_LEFT - 1'b1) && (cnt_h < H_SYNC + H_BACK + H_LEFT + H_VALID - 1'b1))
&&((cnt_v >= V_SYNC + V_BACK + V_TOP) && (cnt_v < V_SYNC + V_BACK + V_TOP + V_VALID))
)
? 1'b1 : 1'b0;
assign rgb = (rgb_valid == 1'b1) ? pix_data : 24'd0 ;
assign VGA_R = rgb[23:16];
assign VGA_G = rgb[15:8];
assign VGA_B = rgb[7:0];
wire TL;
wire TR;
wire BL;
wire BR;
assign TL = (( pix_x >= 0) && (pix_x < H_VALID/2) && ((pix_y >= 0) && (pix_y < V_VALID/2)));
assign TR = (( pix_x >= H_VALID/2) && (pix_x < H_VALID) && ((pix_y >= 0) && (pix_y < V_VALID/2)) );
assign BL = (( pix_x >= 0) && (pix_x < H_VALID/2) && ((pix_y >= V_VALID/2) && (pix_y < V_VALID)) );
assign BR = (( pix_x >= H_VALID/2) && (pix_x < H_VALID) && ((pix_y >= V_VALID/2) && (pix_y < V_VALID)) );
按下按鈕就+1
`timescale 1ns/1ns
module
VGA
(
input sys_clk,
input sys_rst_n,
input color_change,
output vga_clk,
output VGA_BLANK_N,
output VGA_SYNC_N,
output hsync,
output vsync,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B
);
wire [9:0] pix_x;
wire [9:0] pix_y;
reg [1:0] cnt;
parameter div_num = 2;
parameter H_SYNC = 10'd96 ;
parameter H_BACK = 10'd40 ;
parameter H_LEFT = 10'd8 ;
parameter H_VALID = 10'd640 ;
parameter H_RIGHT = 10'd8 ;
parameter H_FRONT = 10'd8 ;
parameter H_TOTAL = 10'd800 ;
parameter V_SYNC = 10'd2 ;
parameter V_BACK = 10'd25 ;
parameter V_TOP = 10'd8 ;
parameter V_VALID = 10'd480 ;
parameter V_BOTTOM = 10'd8 ;
parameter V_FRONT = 10'd2 ;
parameter V_TOTAL = 10'd525 ;
parameter White = 24'hFFFFFF;
parameter Silver = 24'hC0C0C0;
parameter Turquoise1 = 24'h00F5FF;
parameter Moccasin = 24'hFFE4B5;
parameter NavyBlue = 24'h000080;
parameter Green1 = 24'h00FF00;
parameter Chartreuse1 = 24'h7FFF00;
parameter DarkGreen = 24'h006400;
parameter Yellow1 = 24'hFFFF00;
parameter IndianRed1 = 24'hFF6A6A;
parameter Brown1 = 24'hFF4040;
parameter Purple = 24'hA020F0;
parameter Orange1 = 24'hFFA500;
parameter PeachPuff1 = 24'hFFDAB9;
parameter Red1 = 24'hFF0000;
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
begin
cnt <= 2'd0;
end
else
begin
if(cnt <= div_num - 1'b1)
begin
cnt <= cnt + 2'd1;
end
else
begin
cnt <= 2'd1;
end
end
end
assign vga_clk = (cnt == 2'b1 ) ? 1'b1 : 1'b0;
reg [23:0] pix_data;
wire [23:0] rgb;
wire rgb_valid;
wire pix_data_req;
//reg define
reg [9:0] cnt_h;
reg [9:0] cnt_v;
always@(posedge vga_clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
begin
cnt_h <= 10'd0;
end
else
begin
if(cnt_h == H_TOTAL - 1'd1)
begin
cnt_h <= 10'd0;
end
else
begin
cnt_h <= cnt_h + 1'd1;
end
end
end
assign hsync = (cnt_h <= H_SYNC - 1'd1) ? 1'b0 : 1'b1 ;
wire cnt_v_zero;
assign cnt_v_zero = ((cnt_v == V_TOTAL - 1'd1) && (cnt_h == H_TOTAL-1'd1) );
always@(posedge vga_clk or negedge sys_rst_n or posedge cnt_v_zero)
begin
if(!sys_rst_n || cnt_v_zero)
begin
cnt_v <= 10'd0 ;
end
else
begin
if(cnt_h == H_TOTAL - 1'd1)
cnt_v <= cnt_v + 1'd1 ;
else
cnt_v <= cnt_v ;
end
end
assign vsync = (cnt_v <= V_SYNC - 1'd1) ? 1'b0 : 1'b1 ;
assign pix_data_req = (
((cnt_h >= H_SYNC + H_BACK + H_LEFT - 1'b1) && (cnt_h < H_SYNC + H_BACK + H_LEFT + H_VALID - 1'b1))
&&((cnt_v >= V_SYNC + V_BACK + V_TOP) && (cnt_v < V_SYNC + V_BACK + V_TOP + V_VALID))
)
? 1'b1 : 1'b0;
assign pix_x = (pix_data_req == 1'b1)
? (cnt_h - (H_SYNC + H_BACK + H_LEFT - 1'b1)) : 10'h3ff;
assign pix_y = (pix_data_req == 1'b1)
? (cnt_v - (V_SYNC + V_BACK + V_TOP)) : 10'h3ff;
wire TL;
wire TR;
wire BL;
wire BR;
assign TL = (( pix_x >= 0) && (pix_x < H_VALID/2) && ((pix_y >= 0) && (pix_y < V_VALID/2)));
assign TR = (( pix_x >= H_VALID/2) && (pix_x < H_VALID) && ((pix_y >= 0) && (pix_y < V_VALID/2)) );
assign BL = (( pix_x >= 0) && (pix_x < H_VALID/2) && ((pix_y >= V_VALID/2) && (pix_y < V_VALID)) );
assign BR = (( pix_x >= H_VALID/2) && (pix_x < H_VALID) && ((pix_y >= V_VALID/2) && (pix_y < V_VALID)) );
reg color_change_d0;
reg color_change_d1;
wire CG_TG;
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
begin
color_change_d0 <= 1'b0;
color_change_d1 <= 1'b0;
end
else
begin
color_change_d0 <= color_change;
color_change_d1 <= color_change_d0;
end
end
assign CG_TG = color_change_d0 && !color_change_d1;
reg [3:0] CG_cnt;
wire CG_10;
assign CG_10 = (CG_cnt == 4'd4) ? 1'b1 : 1'b0;
always@(posedge sys_clk or negedge sys_rst_n or posedge CG_10)
begin
if(!sys_rst_n || CG_10)
begin
CG_cnt <= 4'd0;
end
else
begin
if(CG_TG)
begin
CG_cnt <= CG_cnt + 4'd1;
end
else
begin
CG_cnt <= CG_cnt;
end
end
end
reg [23:0] TL_cor;
reg [23:0] TR_cor;
reg [23:0] BL_cor;
reg [23:0] BR_cor;
always @(posedge vga_clk or negedge sys_rst_n)
begin
if (!sys_rst_n)
begin
TL_cor <= 24'd0;
TR_cor <= 24'd0;
BL_cor <= 24'd0;
BR_cor <= 24'd0;
end
else
begin
case (CG_cnt)
4'd1:
begin
TL_cor <= White;
TR_cor <= Silver;
BL_cor <= Turquoise1;
BR_cor <= Moccasin;
end
4'd2:
begin
TL_cor <= NavyBlue;
TR_cor <= Green1;
BL_cor <= Chartreuse1;
BR_cor <= DarkGreen;
end
4'd3:
begin
TL_cor <= Yellow1;
TR_cor <= IndianRed1;
BL_cor <= Turquoise1;
BR_cor <= Brown1;
end
4'd4:
begin
TL_cor <= Purple;
TR_cor <= Orange1;
BL_cor <= PeachPuff1;
BR_cor <= Red1;
end
default:
begin
TL_cor <= TL_cor;
TR_cor <= TR_cor;
BL_cor <= BL_cor;
BR_cor <= BR_cor;
end
endcase
end
end
/*
reg state;
always@(posedge vga_clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
pix_data <= 16'd0;
else
begin
case(state)
White_pix: pix_data <= White;
Silver_pix: pix_data <= Silver;
Turquoise1_pix: pix_data <= Turquoise1;
Moccasin_pix :pix_data <= Moccasin;
default:
begin
pix_data <= pix_data;
end
endcase
end
end
*/
always@(posedge vga_clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
pix_data <= 24'd0;
else
begin
if(TL)
begin
pix_data <= TL_cor;
end
else
begin
if(TR)
begin
pix_data <= TR_cor;
end
else
begin
if(BL)
begin
pix_data <= BL_cor;
end
else
begin
if(TR)
begin
pix_data <= BR_cor;
end
else
begin
pix_data <= Red1;
end
end
end
end
end
end
assign rgb_valid = (
((cnt_h >= H_SYNC + H_BACK + H_LEFT) && (cnt_h < H_SYNC + H_BACK + H_LEFT + H_VALID))
&&( (cnt_v >= V_SYNC + V_BACK + V_TOP) && (cnt_v < V_SYNC + V_BACK + V_TOP + V_VALID) )
)
? 1'b1 : 1'b0;
assign rgb = (rgb_valid == 1'b1) ? pix_data : 24'd0 ;
assign VGA_BLANK_N = rgb_valid;
assign VGA_R = rgb[23:16];
assign VGA_G = rgb[15:8];
assign VGA_B = rgb[7:0];
endmodule
`timescale 1ns / 1ps
module tb();
reg sys_clk;
reg sys_rst_n;
reg color_change;
wire vga_clk;
wire VGA_BLANK_N;
wire VGA_SYNC_N;
wire hsync;
wire vsync;
wire [7:0] VGA_R;
wire [7:0] VGA_G;
wire [7:0] VGA_B;
always #20 sys_clk = !sys_clk;
initial
begin
sys_clk = 1'b1;
sys_rst_n = 1'b1;
color_change = 1'b0;
#40;
sys_rst_n = 1'b0;
#50;
sys_rst_n = 1'b1;
#20;
color_change = 1'b1;
#50;
color_change = 1'b0;
end
VGA g0
(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.color_change(color_change),
.vga_clk(vga_clk),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N),
.hsync(hsync),
.vsync(vsync),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
endmodule以上包括tb和v檔
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