一、环境准备
- 下载官方uboot版本uboot-202301
下载地址https://ftp.denx.de/pub/u-boot/u-boot-2023.01.tar.bz2
- 交叉工具编译安装版本。安装后查看版本 arm-none-linux-gnueabihf-gcc -v，如下图
- 安装openssl-1.1.1n，编译源码的过程中提示需安装，先前安装过低一点的版本也会报错，之后安装该版本后未再报错，安装方法请到网上搜索。
- 设备树编译工具安装
本次编译所用编译工具版本如下，
二、硬件设备
- 所使用的硬件设备为北京讯为的iTop4412精英版，1G内存pop封装核心板。网上有很多iTop4412 uboot的移植资料，但由于pop版本和scp版本还是有所区别的，可能本次移植并不一定兼容scp的板子。
三、参考资料
本文参考uboot-2017的移植，在大佬对uboot-2017移植的基础上对uboot-202301进行移植。参考及学习的博客、文章如下：
https://www.jianshu.com/p/5df61e55e96a
https://www.tiandeng.xyz/posts/iTop4412-u-boot-%E7%A7%BB%E6%A4%8D/#3-添加板级配置文件
https://blog.csdn.net/lgc1990/article/details/109160426
https://chasinglulu.github.io/2019/08/29/%E5%9F%BA%E4%BA%8EExynos4412%E5%BC%80%E5%8F%91%E6%9D%BF%E7%9A%84uboot-2019-07%E7%A7%BB%E6%A4%8D/
https://www.cnblogs.com/pengdonglin137/p/5080645.html
https://github.com/kuangfei2019/ITOP4412-POP-1G-uboot-2017
四、开始移植
本博客对照samsung的origen的移植文件进行修改，硬件外设对照iTop4412 精英版1G pop核心板开发板的设置。以下是对uboot-202301版本的移植过程。
1.拷贝board/samsung/origen 目录的文件，目录名改为ex4412,目录下需修改的文件名如下：
$ tree board/samsung/ex4412
board/samsung/ex4412
├── ex4412.c
├── Kconfig
├── MAINTAINERS
├── Makefile
└── tools
└── mkex4412spl.c
2.拷贝include/configs/origen.h，修改命名为ex4412.h
cp include/configs/origen.h include/configs/ex4412.h
3.拷贝arch/arm/dts/exynos4412-odroid.dts，修改文件名称为exynos4412-ex4412.dts
cp arch/arm/dts/exynos4412-odroid.dts arch/arm/dts/exynos4412-ex4412.dts
4.拷贝arch/arm/mach-exynos/exynos4_setup.h，重命名为ex4412_setup.h
cp arch/arm/mach-exynos/exynos4_setup.h arch/arm/mach-exynos/ex4412_setup.h
5.拷贝以下文件并重命名
cp configs/origen_defconfig configs/ex4412_defconfig
6.新增文件
touch arch/arm/mach-exynos/board.c
其中board.c实现板子初始化点灯动作。
7.修改文件board/samsung/ex4412下的文件
- ex4412.c
--- board/samsung/origen/origen.c 2023-01-10 00:07:33.000000000 +0800
+++ board/samsung/ex4412/ex4412.c 2023-04-28 17:27:21.000000000 +0800
@@ -12,6 +12,9 @@
#include <asm/arch/pinmux.h>
#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
int exynos_init(void)
{
return 0;- Kconfig
--- board/samsung/origen/Kconfig 2023-01-10 00:07:33.000000000 +0800
+++ board/samsung/ex4412/Kconfig 2023-04-15 10:38:39.000000000 +0800
@@ -1,12 +1,12 @@
-if TARGET_ORIGEN
+if TARGET_EX4412
config SYS_BOARD
- default "origen"
+ default "ex4412"
config SYS_VENDOR
default "samsung"
config SYS_CONFIG_NAME
- default "origen"
+ default "ex4412"
endif- Makefile
--- board/samsung/origen/Makefile 2023-01-10 00:07:33.000000000 +0800
+++ board/samsung/ex4412/Makefile 2023-04-26 16:43:42.000000000 +0800
@@ -6,7 +6,7 @@
# necessary to create built-in.o
obj- := __dummy__.o
-hostprogs-y := tools/mkorigenspl
+hostprogs-y := tools/mkex4412spl
always := $(hostprogs-y)
# omit -O2 option to suppress
@@ -14,7 +14,7 @@
#
# TODO:
# Fix the root cause in tools/mkorigenspl.c and delete the following work-around
-$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
+$(obj)/tools/mkex4412spl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
else
-obj-y += origen.o
+obj-y += ex4412.o
endif- MAINTAINERS
--- board/samsung/origen/MAINTAINERS 2023-01-10 00:07:33.000000000 +0800
+++ board/samsung/ex4412/MAINTAINERS 2023-04-15 11:37:44.000000000 +0800
@@ -1,6 +1,6 @@
-ORIGEN BOARD
+EX4412 BOARD
M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
-F: board/samsung/origen/
-F: include/configs/origen.h
-F: configs/origen_defconfig
+F: board/samsung/ex4412/
+F: include/configs/ex4412.h
+F: configs/ex4412_defconfig8.在arch/arm/include/asm/mach-types.h文件末尾处新增machine-type 。文件中存在MACH_TYPE_EXYNOS4412，貌似也可以使用该ID,使用时需与ex4412.h里的引用一致，实际测试中，不论新增还是使用已有的，编译不受影响，存在即有其道理，只是暂时未知。
9.修改include/configs/ex4412.h
--- include/configs/origen.h 2023-01-10 00:07:33.000000000 +0800
+++ include/configs/ex4412.h 2023-05-11 10:51:17.000000000 +0800
@@ -5,24 +5,46 @@
* Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.
*/
-#ifndef __CONFIG_ORIGEN_H
-#define __CONFIG_ORIGEN_H
+#ifndef __CONFIG_EX4412_H
+#define __CONFIG_EX4412_H
#include <configs/exynos4-common.h>
+#define CONFIG_EXYNOS4412 1
+#define CONFIG_EX4412 1
+/* #define CONFIG_SYS_L2CACHE_OFF 1 */
+#define CONFIG_SPL_TEXT_BASE 0x02023400
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+#define COPY_BL2_FNPTR_ADDR 0x02020030
+#define CONFIG_DEFAULT_CONSOLE “console=ttySAC2,115200n8\0”
+
+#define CONFIG_DEBUG_UART_BASE 0x13820000
+#define CONFIG_DEBUG_UART_CLOCK 100000000
+#define CONFIG_SPL_SERIAL_SUPPORT 1
+#define CONFIG_SPL_GPIO_SUPPORT 1
+
+#define CONFIG_CLK_1000_200_200
+/* #define CONFIG_SPL_BUILD run wrong*/
+
+/* #define CONFIG_SYS_DRAM_TEST 1 */
/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
+
/* Power Down Modes */
#define S5P_CHECK_SLEEP 0x00000BAD
#define S5P_CHECK_DIDLE 0xBAD00000
#define S5P_CHECK_LPA 0xABAD0000
/* MMC SPL */
-#define COPY_BL2_FNPTR_ADDR 0x02020030
-
+#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x40007000\0" \
"rdaddr=0x48000000\0" \
@@ -40,8 +62,10 @@
/* MIU (Memory Interleaving Unit) */
#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
-
#define RESERVE_BLOCK_SIZE (512)
-#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
+#define BL1_SIZE (8 << 10) /*16 K reserved for BL1*/
+#define BL2_SIZE (16 << 10) /* 512 KB */
+
+/* #define SPI_FLASH_UBOOT_POS (SEC_FW_SIZE + BL1_SIZE) */
#endif /* __CONFIG_H */10.修改arch/arm/dts/exynos4412-ex4412.dts
--- arch/arm/dts/exynos4412-odroid.dts 2023-04-17 00:02:21.000000000 +0800
+++ arch/arm/dts/exynos4412-ex4412.dts 2023-04-29 22:14:35.000000000 +0800
@@ -10,17 +10,25 @@
#include "exynos4412.dtsi"
/ {
- model = "Odroid based on Exynos4412";
- compatible = "samsung,odroid", "samsung,exynos4412";
+ model = "EX4412 based on Exynos4412";
+ compatible = "samsung,ex4412", "samsung,exynos4412";
aliases {
- serial0 = "/serial@13800000";
- console = "/serial@13810000";
+ serial2 = "/serial@13820000";
+ console = "/serial@13820000";
mmc0 = &mshc_0;
mmc2 = &sdhci2;
};
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
- serial@13810000 {
+ serial@13820000 {
status = "okay";
};
@@ -242,7 +250,7 @@
};
&mshc_0 {
- samsung,bus-width = <8>;
+ samsung,bus-width = <4>;
samsung,timing = <2 1 0>;
samsung,removable = <0>;
fifoth_val = <0x203f0040>;11.修改arch/arm/mach-exynos/Kconfig
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -77,6 +77,12 @@ config TARGET_ORIGEN
select EXYNOS4210
select SUPPORT_SPL
+config TARGET_EX4412
+ bool "Exynos4412 Ex4412 board"
+ select EXYNOS4412
+ select SUPPORT_SPL
+
+
config TARGET_TRATS2
bool "Exynos4412 Trat2 board"
@@ -232,6 +238,7 @@ source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
source "board/samsung/universal_c210/Kconfig"
source "board/samsung/origen/Kconfig"
+source "board/samsung/ex4412/Kconfig"
source "board/samsung/trats2/Kconfig"
source "board/samsung/odroid/Kconfig"
source "board/samsung/arndale/Kconfig"12.修改arch/arm/mach-exynos/Makefile
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -3,6 +3,7 @@
# Copyright (C) 2009 Samsung Electronics
# Minkyu Kang <mk7.kang@samsung.com>
+obj-y += board.o
obj-y += soc.o
obj-$(CONFIG_CPU_V7A) += clock.o pinmux.o power.o system.o
obj-$(CONFIG_ARM64) += mmu-arm64.o
@@ -12,7 +13,9 @@ obj-$(CONFIG_EXYNOS5420) += sec_boot.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
-obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
+ifneq ($(filter y,$(CONFIG_EXYNOS4210)$(CONFIG_EX4412)),)
+obj-y += dmc_init_exynos4.o clock_init_exynos4.o
+endif
obj-y += spl_boot.o tzpc.o
obj-y += lowlevel_init.o
endif五、适配板子硬件的配置修改
前面已经对origen的配置做了拷贝，部分需针对iTop4412 1G pop精英版的板子做修改
1.对ex4412_defconfig的内容进行增减、修改
CONFIG_ARM=y
# CONFIG_SKIP_LOWLEVEL_INIT=y
#CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ARCH_EXYNOS4=y
CONFIG_EX4412=y
CONFIG_TARGET_EX4412=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_S5P=y
CONFIG_DEBUG_UART_BASE=0x13820000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4200
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-ex4412"
CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SYS_PROMPT="EX4412 # "
CONFIG_TEXT_BASE=0x43E00000
CONFIG_SD_BOOT=y
CONFIG_IDENT_STRING=" for EX4412"
CONFIG_SYS_MEM_TOP_HIDE=0x100000
CONFIG_SYS_LOAD_ADDR=0x43e00000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2040000
CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTCOMMAND="if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};run importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run uenvcmd;fi;if run loadbootscript; then run bootscript; fi; fi;load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x3800
CONFIG_SYS_PBSIZE=1024
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Samsung"
CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
CONFIG_USB_GADGET_PRODUCT_NUM=0x6601
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DWC2_OTG_PHY=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y2.修改arch/arm/mach-exynos/clock_init_exynos4.c，初始化时钟
diff --git a/arch/arm/mach-exynos/clock_init_exynos4.c b/arch/arm/mach-exynos/clock_init_exynos4.c
index 584e4ba..bf85a3b 100644
--- a/arch/arm/mach-exynos/clock_init_exynos4.c
+++ b/arch/arm/mach-exynos/clock_init_exynos4.c
@@ -30,65 +30,559 @@
#include <asm/arch/clk.h>
#include <asm/arch/clock.h>
#include "common_setup.h"
-#include "exynos4_setup.h"
+#ifdef CONFIG_EX4412
+#include "ex4412_setup.h"
+#else
+#include "exynos4_setup.h"
+#endif
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
+/**
+ * freq (ARMCLK) = 1400 MHz at 1.3 V
+ * freq (ACLK_COREM0) = 350 MHz at 1.3V
+ * freq (ACLK_COREM1) = 188 MHz at 1.3 V
+ * freq (PERIPHCLK) = 1400 MHz at 1.3 V
+ * freq (ATCLK) = 214 MHz at 1.3 V
+ * freq (PCLK_DBG) = 107 MHz at 1.3 V
+ * freq (SCLK_DMC) = 400 MHz at 1.0 V
+ * freq (ACLK_DMCD) = 200 MHz at 1.0 V
+ * freq (ACLK_DMCP) = 100 MHz at 1.0 V
+ * freq (ACLK_ACP) = 200 MHz at 1.0 V
+ * freq (PCLK_ACP) = 100 MHz at 1.0 V
+ * freq (SCLK_C2C) = 400 MHz at 1.0 V
+ * freq (ACLK_C2C) = 200 MHz at 1.0 V
+ * freq (ACLK_GDL) = 200 MHz at 1.0 V
+ * freq (ACLK_GPL) = 100 MHz at 1.0 V
+ * freq (ACLK_GDR) = 200 MHz at 1.0 V
+ * freq (ACLK_GPR) = 100 MHz at 1.0 V
+ * freq (ACLK_400_MCUISP) = 400 MHz at 1.0 V
+ * freq (ACLK_200) = 160 MHz at 1.0 V
+ * freq (ACLK_100) = 100 MHz at 1.0 V
+ * freq (ACLK_160) = 160 MHz at 1.0 V
+ * freq (ACLK_133) = 133 MHz at 1.0 V
+ * freq (SCLK_ONENAND) = 160 MHz at 1.0 V
+ */
void system_clock_init(void)
{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
-
- writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
-
- sdelay(0x10000);
-
- writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
- writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
- writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
- writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
- writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
- writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
- writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
- writel(CLK_SRC_CAM_VAL, &clk->src_cam);
- writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
- writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
- writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
-
- sdelay(0x10000);
-
- writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
- writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
- writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
- writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
- writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
- writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
- writel(CLK_DIV_TOP_VAL, &clk->div_top);
- writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
- writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
- writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
- writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
- writel(CLK_DIV_CAM_VAL, &clk->div_cam);
- writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
- writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
- writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
-
- /* Set PLL locktime */
- writel(PLL_LOCKTIME, &clk->apll_lock);
- writel(PLL_LOCKTIME, &clk->mpll_lock);
- writel(PLL_LOCKTIME, &clk->epll_lock);
- writel(PLL_LOCKTIME, &clk->vpll_lock);
-
- writel(APLL_CON1_VAL, &clk->apll_con1);
- writel(APLL_CON0_VAL, &clk->apll_con0);
- writel(MPLL_CON1_VAL, &clk->mpll_con1);
- writel(MPLL_CON0_VAL, &clk->mpll_con0);
- writel(EPLL_CON1_VAL, &clk->epll_con1);
- writel(EPLL_CON0_VAL, &clk->epll_con0);
- writel(VPLL_CON1_VAL, &clk->vpll_con1);
- writel(VPLL_CON0_VAL, &clk->vpll_con0);
-
- sdelay(0x30000);
+ unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
+ struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
+ samsung_get_base_clock();
+
+/************************************************************
+ * Step 1:
+ *
+ * Set PDIV, MDIV, and SDIV values (Refer to (A, M, E, V)
+ * Change other PLL control values
+ ************************************************************/
+
+ /**
+ * Set dividers for MOUTcore = 1000 MHz
+ *
+ * DOUTcore = MOUTcore / (CORE_RATIO +1) = 1000 MHz (0)
+ * ACLK_COREM0 = ARMCLK / (COREM0_RATIO +1) = 250 MHz (3)
+ * ACLK_COREM1 = ARMCLK / (COREM1_RATIO +1) = 125 MHz (7)
+ * PERIPHCLK = DOUTcore / (PERIPH_RATIO + 1) = 1000 MHz (0)
+ * ATCLK = MOUTcore / (ATB_RATIO + 1) = 200 MHz (4)
+ * PCLK_DBG = ATCLK / (PCLK_DBG_RATIO + 1) = 100 MHz (1)
+ * SCLKapll = MOUTapll / (APLL_RATIO + 1) = 500 MHz (1)
+ * ARMCLK = DOUTcore / (CORE2_RATIO + 1) = 1000 MHz (0)
+ */
+
+ /** CLK_DIV_CPU0 */
+ clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
+ PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
+ APLL_RATIO(7) | CORE2_RATIO(7);
+ set = CORE_RATIO(0) | COREM0_RATIO(3) | COREM1_RATIO(7) |
+ PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
+ APLL_RATIO(1) | CORE2_RATIO(0);
+
+ clrsetbits_le32(&clk->div_cpu0, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
+ continue;
+
+ /**
+ * Set dividers for MOUThpm = 1000 MHz (MOUTapll)
+ *
+ * DOUTcopy = MOUThpm / (COPY_RATIO + 1) = 200 MHz (4)
+ * SCLK_HPM = DOUTcopy / (HPM_RATIO + 1) = 200 MHz (0)
+ * ACLK_CORES = ARMCLK / (CORES_RATIO + 1) = 1000 MHz (0)
+ */
+
+ /** CLK_DIV_CPU1 */
+ clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
+ set = COPY_RATIO(4) | HPM_RATIO(0) | CORES_RATIO(0);
+
+ clrsetbits_le32(&clk->div_cpu1, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
+ continue;
+
+ /**
+ * Set dividers for -->
+ * MOUTdmc = 800 MHz
+ * MOUTdphy = 800 MHz
+ *
+ * ACLK_ACP = MOUTdmc / (ACP_RATIO + 1) = 200 MHz (3)
+ * PCLK_ACP = ACLK_ACP / (ACP_PCLK_RATIO + 1) = 100 MHz (1)
+ * SCLK_DPHY = MOUTdphy / (DPHY_RATIO + 1) = 400 MHz (1)
+ * SCLK_DMC = MOUTdmc / (DMC_RATIO + 1) = 400 MHz (1)
+ * ACLK_DMCD = SCLK_DMC / (DMCD_RATIO + 1) = 200 MHz (1)
+ * ACLK_DMCP = ACLK_DMCD / (DMCP_RATIO + 1) = 100 MHz (1)
+ */
+
+ /** CLK_DIV_DMC0 */
+ clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
+ DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
+ set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
+ DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
+
+ clrsetbits_le32(&clk->div_dmc0, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
+ continue;
+
+ /**
+ * For:
+ * MOUTg2d = 800 MHz
+ * MOUTc2c = 800 Mhz
+ * MOUTpwi = 24 MHz
+ *
+ * SCLK_G2D_ACP = MOUTg2d / (G2D_ACP_RATIO + 1) = 200 MHz (3)
+ * SCLK_C2C = MOUTc2c / (C2C_RATIO + 1) = 400 MHz (1)
+ * SCLK_PWI = MOUTpwi / (PWI_RATIO + 1) = 24 MHz (0)
+ * ACLK_C2C = SCLK_C2C / (C2C_ACLK_RATIO + 1) = 200 MHz (1)
+ * DVSEM_RATIO : It decides frequency for PWM frame time slot in DVS emulation mode.
+ * DPM_RATIO : It decides frequency of DPM channel clock.
+ */
+
+ /** CLK_DIV_DMC1 */
+ clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
+ C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
+ set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(0) |
+ C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
+
+ clrsetbits_le32(&clk->div_dmc1, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
+ continue;
+
+ /**
+ * MOUTmpll = 800 MHz
+ * MOUTvpll = 54 MHz
+ *
+ * ACLK_200 = MOUTACLK_200 / (ACLK_200_RATIO + 1) = 200 MHz (3)
+ * ACLK_100 = MOUTACLK_100 / (ACLK_100_RATIO + 1) = 100 MHz (7)
+ * ACLK_160 = MOUTACLK_160 / (ACLK_160_RATIO + 1) = 160 MHz (4)
+ * ACLK_133 = MOUTACLK_133 / (ACLK_133_RATIO + 1) = 133 MHz (5)
+ * ONENAND = MOUTONENAND_1 / (ONENAND_RATIO + 1) = 160 MHz (0)
+ * ACLK_266_GPS = MOUTACLK_266_GPS / (ACLK_266_GPS_RATIO + 1) = 266 MHz (2)
+ * ACLK_400_MCUISP = MOUTACLK_400_MCUISP / (ACLK_400_MCUISP_RATIO + 1) = 400 MHz (1)
+ */
+
+ /** CLK_DIV_TOP */
+ clr = ACLK_200_RATIO(7) | ACLK_100_RATIO(15) | ACLK_160_RATIO(7) |
+ ACLK_133_RATIO(7) | ONENAND_RATIO(7) | ACLK_266_GPS_RATIO(7) | ACLK_400_MCUISP_RATIO(7);
+ set = ACLK_200_RATIO(3) | ACLK_100_RATIO(7) | ACLK_160_RATIO(4) |
+ ACLK_133_RATIO(5) | ONENAND_RATIO(0) | ACLK_266_GPS_RATIO(2) | ACLK_400_MCUISP_RATIO(1);
+
+ clrsetbits_le32(&clk->div_top, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_top) & DIV_STAT_TOP_CHANGING)
+ continue;
+
+ /**
+ * ACLK_GDL = MOUTGDL / (GDL_RATIO + 1) = 200 MHz (3)
+ * ACLK_GPL = MOUTGPL / (GPL_RATIO + 1) = 100 MHz (1)
+ */
+
+ /** CLK_DIV_LEFTBUS */
+ clr = GDL_RATIO(7) | GPL_RATIO(7);
+ set = GDL_RATIO(3) | GPL_RATIO(1);
+
+ clrsetbits_le32(&clk->div_leftbus, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_leftbus) & DIV_STAT_LEFTBUS_CHANGING)
+ continue;
+
+ /**
+ * ACLK_GDR = MOUTGDR / (GDR_RATIO + 1) = 200 MHz (3)
+ * ACLK_GPR = MOUTGPR / (GPR_RATIO + 1) = 100 MHz (1)
+ */
+
+ /** CLK_DIV_RIGHTBUS */
+ clr = GPR_RATIO(7) | GDR_RATIO(7);
+ set = GPR_RATIO(3) | GDR_RATIO(1);
+
+ clrsetbits_le32(&clk->div_rightbus, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_rightbus) & DIV_STAT_RIGHTBUS_CHANGING)
+ continue;
+
+ /**
+ * MOUTUART[1-4] = 800 Mhz (MPLL)
+ *
+ * SCLK_UART0 = MOUTUART0 / (UART0_RATIO + 1) = 100 MHz (7)
+ * SCLK_UART1 = MOUTUART1 / (UART1_RATIO + 1) = 100 MHz (7)
+ * SCLK_UART2 = MOUTUART2 / (UART2_RATIO + 1) = 100 MHz (7)
+ * SCLK_UART3 = MOUTUART3 / (UART3_RATIO + 1) = 100 MHz (7)
+ * SCLK_UART4 = MOUTUART4 / (UART4_RATIO + 1) = 100 MHz (7)
+ */
+ /** CLK_DIV_PERIL0 */
+ clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
+ UART3_RATIO(15) | UART4_RATIO(15);
+ set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
+ UART3_RATIO(7) | UART4_RATIO(7);
+
+ clrsetbits_le32(&clk->div_peril0, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
+ continue;
+ /**
+ * For MOUTMMC0-3 = 800 MHz (MPLL)
+ *
+ * SCLK_MIPIHSI = MOUTMIPIHSI / (MIPIHSI_RATIO + 1) = 200 MHz (3)
+ */
+ /* CLK_DIV_FSYS0 */
+ clr = MIPIHSI_RATIO(15);
+ set = MIPIHSI_RATIO(3);
+
+ clrsetbits_le32(&clk->div_fsys0, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_fsys0) & DIV_STAT_FSYS0_CHANGING)
+ continue;
+
+ /**
+ * For MOUTMMC0-3 = 800 MHz (MPLL)
+ *
+ * DOUTMMC0 = MOUTMMC0 / (MMC0_RATIO + 1) = 100 MHz (7)
+ * SCLK_MMC0 = DOUTMMC0 / (MMC0_PRE_RATIO + 1) = 50 MHz (1)
+ * DOUTMMC1 = MOUTMMC1 / (MMC1_RATIO + 1) = 100 MHz (7)
+ * SCLK_MMC1 = DOUTMMC1 / (MMC1_PRE_RATIO + 1) = 50 MHz (1)
+ */
+ /* CLK_DIV_FSYS1 */
+ clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
+ MMC1_PRE_RATIO(255);
+
+ set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
+ MMC1_PRE_RATIO(1);
+
+ clrsetbits_le32(&clk->div_fsys1, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
+ continue;
+
+ /**
+ * For MOUTmmc0-3 = 800 MHz (MPLL)
+ *
+ * DOUTmmc3 = MOUTmmc3 / (MMC2_RATIO + 1) = 100 MHz (7)
+ * sclk_mmc3 = DOUTmmc3 / (MMC2_PRE_RATIO + 1) = 50 MHz (1)
+ * DOUTmmc2 = MOUTmmc2 / (MMC3_RATIO + 1) = 100 MHz (7)
+ * sclk_mmc2 = DOUTmmc2 / (MMC3_PRE_RATIO + 1) = 50 MHz (1)
+ */
+ /* CLK_DIV_FSYS2 */
+ clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
+ MMC3_PRE_RATIO(255);
+ set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
+ MMC3_PRE_RATIO(1);
+
+ clrsetbits_le32(&clk->div_fsys2, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
+ continue;
+
+ /**
+ * For MOUTmmc4 = 800 MHz (MPLL)
+ *
+ * DOUTmmc4 = MOUTmmc4 / (MMC4_RATIO + 1) = 100 MHz (7)
+ * sclk_mmc4 = DOUTmmc4 / (MMC4_PRE_RATIO + 1) = 50 MHz (1)
+ */
+ /* CLK_DIV_FSYS3 */
+ clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
+ set = MMC4_RATIO(7) | MMC4_PRE_RATIO(1);
+
+ clrsetbits_le32(&clk->div_fsys3, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
+ continue;
+
+/************************************************************
+ * Step 2:
+ *
+ * Set K, AFC, MRR, MFR values if necessary
+ * (Refer to (A, M, E, V)PLL_CON1 SFRs)
+ * Turn on a PLL (Refer to (A, M, E, V) PLL_CON0 SFRs)
+ ************************************************************/
+
+ /* Set APLL to 1000MHz */
+ /** APLL_CON1 */
+ clr = AFC(31) | LOCK_CON_DLY(31) | LOCK_CON_IN(3) |
+ LOCK_CON_OUT(3) |FEED_EN(1)| AFC_ENB(1) |
+ DCC_ENB(1) | BYPASS(1) |RESV0(1) | RESV1(1);
+ set = AFC(0) | LOCK_CON_DLY(8) | LOCK_CON_IN(3) |
+ LOCK_CON_OUT(0) |FEED_EN(0)| AFC_ENB(0) |
+ DCC_ENB(1) | BYPASS(0) |RESV0(0) | RESV1(0);
+
+ clrsetbits_le32(&clk->apll_con1, clr, set);
+
+ /** APLL_CON0 */
+ clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | PLL_ENABLE(1);
+ set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(0) | PLL_ENABLE(1);
+
+ clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
+
+ /* Wait for PLL to be locked */
+ while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
+ continue;
+
+ /* Set MPLL to 800MHz */
+ /** MPLL_CON1 */
+ clr = AFC(31) | LOCK_CON_DLY(31) | LOCK_CON_IN(3) |
+ LOCK_CON_OUT(3) |FEED_EN(1)| AFC_ENB(1) |
+ DCC_ENB(1) | BYPASS(1) |RESV0(1) | RESV1(1);
+ set = AFC(0) | LOCK_CON_DLY(8) | LOCK_CON_IN(3) |
+ LOCK_CON_OUT(0) |FEED_EN(0)| AFC_ENB(0) |
+ DCC_ENB(1) | BYPASS(0) |RESV0(0) | RESV1(0);
+
+ clrsetbits_le32(&clk->mpll_con1, clr, set);
+
+ /** MPLL_CON0 */
+ clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | PLL_ENABLE(1);
+ set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
+
+ clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
+
+ /* Wait for PLL to be locked */
+ while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
+ continue;
+
+ /* Set EPLL to 192MHz */
+ /** EPLL_CON2 */
+ clr = ICP_BOOST(7) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
+ SSCG_EN(1) | EV_AFC_ENB(1) | EV_DCC_ENB(1) | EXTAFC(1);
+ set = ICP_BOOST(0) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
+ SSCG_EN(0) | EV_AFC_ENB(0) | EV_DCC_ENB(1) | EXTAFC(0);
+
+ clrsetbits_le32(&clk->epll_con2, clr, set);
+
+ /** EPLL_CON1 */
+ /* there is null */
+
+ /** EPLL_CON0 */
+ clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | PLL_ENABLE(1);
+ set = SDIV(2) | PDIV(2) | MDIV(64) | FSEL(0) | PLL_ENABLE(1);
+
+ clrsetbits_le32(&clk->epll_con0, clr_pll_con0, set);
+
+ /* Wait for PLL to be locked */
+ while (!(readl(&clk->epll_con0) & PLL_LOCKED_BIT))
+ continue;
+
+ /* Set VPLL to 54MHz */
+ /** VPLL_CON2 */
+ clr = ICP_BOOST(7) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
+ SSCG_EN(1) | EV_AFC_ENB(1) | EV_DCC_ENB(1) | EXTAFC(1);
+ set = ICP_BOOST(0) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
+ SSCG_EN(0) | EV_AFC_ENB(0) | EV_DCC_ENB(1) | EXTAFC(0);
+
+ clrsetbits_le32(&clk->vpll_con2, clr, set);
+
+ /** VPLL_CON1 */
+ /* there is null */
+
+ /** VPLL_CON0 */
+ clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | PLL_ENABLE(1);
+ set = SDIV(3) | PDIV(3) | MDIV(54) | FSEL(0) | PLL_ENABLE(1);
+
+ clrsetbits_le32(&clk->vpll_con0, clr_pll_con0, set);
+
+ /* Wait for PLL to be locked */
+ while (!(readl(&clk->vpll_con0) & PLL_LOCKED_BIT))
+ continue;
+
+/************************************************************
+ *Step 3:
+ *
+ * Wait until the PLL is locked
+ ************************************************************/
+ clr = PLL_LOCKTIME(65535);
+
+ /** APLL LOCKTIME 1000MHz */
+ set = PLL_LOCKTIME(PDIV(3) * 270);
+ clrsetbits_le32(&clk->apll_lock, clr, set);
+
+ /** MPLL LOCKTIME 800MHz */
+ set = PLL_LOCKTIME(PDIV(3) * 270);
+ clrsetbits_le32(&clk->mpll_lock, clr, set);
+
+ /** EPLL LOCKTIME 192MHz */
+ set = PLL_LOCKTIME(PDIV(2) * 270);
+ clrsetbits_le32(&clk->epll_lock, clr, set);
+
+ /** VPLL LOCKTIME 54MHz */
+ set = PLL_LOCKTIME(PDIV(3) * 270);
+ clrsetbits_le32(&clk->vpll_lock, clr, set);
+
+/************************************************************
+ * Step 4:
+ *
+ * Select the PLL output clock instead of input reference clock,
+ * after PLL output clock is stabilized.
+ * (Refer to CLK_SRC_CPU SFR for APLL and MPLL,
+ * CLK_SRC_TOP0 for EPLL and VPLL)
+ * Once a PLL is turned on, do not turn it off.
+ ************************************************************/
+
+ /**
+ * before set system clocks,we switch system clocks src to FINpll
+ *
+ * Bit values: 0 ; 1
+ * MUX_APLL_SEL: FIN_PLL ; MOUTAPLLFOUT
+ * MUX_CORE_SEL: MOUTAPLL ; SCLKMPLL
+ * MUX_HPM_SEL: MOUTAPLL ; SCLKMPLL
+ * MUX_MPLL_USER_SEL_C: FINPLL ; FOUTMPLL
+ */
+ /** CLK_SRC_CPU */
+ clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
+ MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
+ set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
+ MUX_MPLL_USER_SEL_C(1);
+
+ clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
+
+ /* Wait for mux change */
+ while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
+ continue;
+
+ /**
+ * Set CMU_DMC default clocks src to APLL
+ *
+ * Bit values: 0 ; 1
+ * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
+ * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
+ * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
+ * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
+ */
+ /** CLK_SRC_DMC */
+ clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
+ MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
+ MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
+ MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
+ set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
+ MUX_MPLL_SEL(1) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(0) |
+ MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
+
+ clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
+
+ /* Wait for mux change */
+ while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
+ continue;
+
+ /**
+ * Set CMU_TOP default clocks src to APLL
+ *
+ * Bit values: 0 ; 1
+ * MUX_ONENAND_1_SEL MOUTONENAND ; SCLKVPLL
+ * MUX_EPLL_SEL FINPLL ; FOUTEPLL
+ * MUX_VPLL_SEL FINPLL ; FOUTEPLL
+ * MUX_ACLK_200_SEL SCLKMPLL ; SCLKAPLL
+ * MUX_ACLK_100_SEL SCLKMPLL ; SCLKAPLL
+ * MUX_ACLK_160_SEL SCLKMPLL ; SCLKAPLL
+ * MUX_ACLK_133_SEL SCLKMPLL ; SCLKAPLL
+ * MUX_ONENAND_SEL ACLK_133 ; ACLK_160
+ */
+
+ /* CLK_SRC_TOP0 */
+ clr = MUX_ONENAND_1_SEL(1) | MUX_EPLL_SEL(1) | MUX_VPLL_SEL(1) |
+ MUX_ACLK_200_SEL(1) | MUX_ACLK_100_SEL(1) | MUX_ACLK_160_SEL(1) |
+ MUX_ACLK_133_SEL(1) | MUX_ONENAND_SEL(1);
+ set = MUX_ONENAND_1_SEL(0) | MUX_EPLL_SEL(1) | MUX_VPLL_SEL(1) |
+ MUX_ACLK_200_SEL(0) | MUX_ACLK_100_SEL(0) | MUX_ACLK_160_SEL(0) |
+ MUX_ACLK_133_SEL(0) | MUX_ONENAND_SEL(1);
+
+ clrsetbits_le32(&clk->src_top0, clr, set);
+
+ /* Wait for mux change */
+ while (readl(&clk->mux_stat_top0) & MUX_STAT_TOP0_CHANGING)
+ continue;
+
+ /**
+ * Bit values: 0 ; 1
+ * MUX_ACLK_266_GPS_SEL SCLKMPLL_USER_T ; SCLKAPLL
+ * MUX_ACLK_400_MCUISP_SEL SCLKMPLL_USER_T ; SCLKAPLL
+ * MUX_MPLL_USER_SEL_T FINPLL ; SCLKMPLLL
+ * MUX_ACLK_266_GPS_SUB_SEL FINPLL ; DIVOUT_ACLK_266_GPS
+ * MUX_ACLK_200_SUB_SEL FINPLL ; DIVOUT_ACLK_200
+ * MUX_ACLK_400_MCUISP_SUB_SEL FINPLL
+ */
+
+ /* CLK_SRC_TOP1 */
+ clr = MUX_ACLK_266_GPS_SEL(1) | MUX_ACLK_400_MCUISP_SEL(1) |
+ MUX_MPLL_USER_SEL_T(1) | MUX_ACLK_266_GPS_SUB_SEL(1) |
+ MUX_ACLK_200_SUB_SEL(1) | MUX_ACLK_400_MCUISP_SUB_SEL(1);
+ set = MUX_ACLK_266_GPS_SEL(0) | MUX_ACLK_400_MCUISP_SEL(0) |
+ MUX_MPLL_USER_SEL_T(1) | MUX_ACLK_266_GPS_SUB_SEL(1) |
+ MUX_ACLK_200_SUB_SEL(1) | MUX_ACLK_400_MCUISP_SUB_SEL(1);
+
+ clrsetbits_le32(&clk->src_top1, clr, set);
+
+ /* Wait for mux change */
+ while (readl(&clk->mux_stat_top1) & MUX_STAT_TOP1_CHANGING)
+ continue;
+
+ /* CLK_SRC_LEFTBUS */
+ clr = MUX_GDL_SEL(1) | MUX_MPLL_USER_SEL_L(1);
+ set = MUX_GDL_SEL(0) | MUX_MPLL_USER_SEL_L(1);
+
+ clrsetbits_le32(&clk->src_leftbus, clr, set);
+
+ /* Wait for mux change */
+ while (readl(&clk->mux_stat_leftbus) & MUX_STAT_LEFTBUS_CHANGING)
+ continue;
+
+ /* CLK_SRC_RIGHTBUS */
+ clr = MUX_GDR_SEL(1) | MUX_MPLL_USER_SEL_R(1);
+ set = MUX_GDR_SEL(0) | MUX_MPLL_USER_SEL_R(1);
+
+ clrsetbits_le32(&clk->src_rightbus, clr, set);
+
+ /* Wait for mux change */
+ while (readl(&clk->mux_stat_rightbus) & MUX_STAT_RIGHTBUS_CHANGING)
+ continue;
+
+ /** CLK_SRC_PERIL0 */
+ clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
+ UART3_SEL(15) | UART4_SEL(15);
+ set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) |
+ UART3_SEL(6) | UART4_SEL(6);
+
+ clrsetbits_le32(&clk->src_peril0, clr, set);
+
+ /** CLK_SRC_FSYS */
+ clr = MMC1_SEL(15) | MMC2_SEL(15) | MMC3_SEL(15) |
+ MMC4_SEL(15) | MIPIHSI_SEL(1);
+ set = MMC1_SEL(6) | MMC2_SEL(6) | MMC3_SEL(6) |
+ MMC4_SEL(6) | MIPIHSI_SEL(0);
+
+ clrsetbits_le32(&clk->src_fsys, clr, set);
}
3.修改ex4412_setup.h
参照arch/arm/mach-exynos/exynos4_setup.h修改部分内容，由于对该部分不是很了解，在移植过程中遇到未能正确配置而导致写入内存的数据无法正确读取的情况。以下做记录，后续再查找相关文档分析学习。
diff --git a/arch/arm/mach-exynos/ex4412_setup.h b/arch/arm/mach-exynos/ex4412_setup.h
new file mode 100644
index 0000000..65a205a
--- /dev/null
+++ b/arch/arm/mach-exynos/ex4412_setup.h
@@ -0,0 +1,608 @@
+#ifndef _EX4412_SETUP_H
+#define _EX4412_SETUP_H
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200
+#endif
+#ifdef CONFIG_CLK_1000_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_400_200
+#define DRAM_CLK_400
+#endif
+
+/* this state is changing for register */
+#define MUX_STAT_CHANGING 0x100
+#define DIV_STAT_CHANGING 0x1
+
+/* A/M/EV PLL_CON0 */
+#define SDIV(x) ((x) & 0x7)
+#define PDIV(x) (((x) & 0x3f) << 8)
+#define MDIV(x) (((x) & 0x3ff) << 16)
+#define FSEL(x) (((x) & 0x1) << 27)
+#define PLL_LOCKED_BIT (0x1 << 29)
+#define PLL_ENABLE(x) (((x) & 0x1) << 31)
+
+/* A/M PLL_CON1 */
+#define AFC(x) ((x) & 0x1f)
+#define LOCK_CON_DLY(x) (((x) & 0x1f) << 8)
+#define LOCK_CON_IN(x) (((x) & 0x3) << 12)
+#define LOCK_CON_OUT(x) (((x) & 0x3) << 14)
+#define FEED_EN(x) (((x) & 0x1) << 16)
+#define AFC_ENB(x) (((x) & 0x1) << 20)
+#define DCC_ENB(x) (((x) & 0x1) << 21)
+#define BYPASS(x) (((x) & 0x1) << 22)
+#define RESV0(x) (((x) & 0x1) << 23)
+#define RESV1(x) (((x) & 0x1) << 24)
+
+/* E/V PLL_CON1 */
+#define K(x) ((x) & 0xffff)
+#define MFR(x) (((x) & 0xff) << 16)
+#define MRR(x) (((x) & 0x1f) << 24)
+#define SEL_PF(x) (((x) & 0x3) << 29)
+
+/* E/V PLL_CON2 */
+#define ICP_BOOST(x) ((x) & 0x3)
+#define EV_FSEL(x) (((x) & 0x1) << 2)
+#define FVCO_EN(x) (((x) & 0x1) << 3)
+#define EV_BYPASS(x) (((x) & 0x1) << 4)
+#define SSCG_EN(x) (((x) & 0x1) << 5)
+#define EV_AFC_ENB(x) (((x) & 0x1) << 6)
+#define EV_DCC_ENB(x) (((x) & 0x1) << 7)
+#define EXTAFC(x) (((x) & 0x1f) << 8)
+
+/* CLK_SRC_CPU */
+#define MUX_APLL_SEL(x) ((x) & 0x1)
+#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
+#define MUX_HPM_SEL(x) (((x) & 0x1) << 20)
+#define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24)
+
+/* CLK_MUX_STAT_CPU */
+#define APLL_SEL(x) ((x) & 0x7)
+#define CORE_SEL(x) (((x) & 0x7) << 16)
+#define HPM_SEL(x) (((x) & 0x7) << 20)
+#define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24)
+#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \
+ CORE_SEL(MUX_STAT_CHANGING) | \
+ HPM_SEL(MUX_STAT_CHANGING) | \
+ MPLL_USER_SEL_C(MUX_STAT_CHANGING))
+
+/* A/M/E/V PLL_LOCK */
+#define PLL_LOCKTIME(x) ((x) & 0xffff)
+
+/* CLK_DIV_CPU0 */
+#define CORE_RATIO(x) ((x) & 0x7)
+#define COREM0_RATIO(x) (((x) & 0x7) << 4)
+#define COREM1_RATIO(x) (((x) & 0x7) << 8)
+#define PERIPH_RATIO(x) (((x) & 0x7) << 12)
+#define ATB_RATIO(x) (((x) & 0x7) << 16)
+#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20)
+#define APLL_RATIO(x) (((x) & 0x7) << 24)
+#define CORE2_RATIO(x) (((x) & 0x7) << 28)
+
+/* CLK_DIV_CPU1 */
+#define COPY_RATIO(x) ((x) & 0x7)
+#define HPM_RATIO(x) (((x) & 0x7) << 4)
+#define CORES_RATIO(x) (((x) & 0x7) << 8)
+
+/* CLK_DIV_STAT_CPU0 */
+#define DIV_CORE(x) ((x) & 0x1)
+#define DIV_COREM0(x) (((x) & 0x1) << 4)
+#define DIV_COREM1(x) (((x) & 0x1) << 8)
+#define DIV_PERIPH(x) (((x) & 0x1) << 12)
+#define DIV_ATB(x) (((x) & 0x1) << 16)
+#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20)
+#define DIV_APLL(x) (((x) & 0x1) << 24)
+#define DIV_CORE2(x) (((x) & 0x1) << 28)
+
+#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \
+ DIV_COREM0(DIV_STAT_CHANGING) | \
+ DIV_COREM1(DIV_STAT_CHANGING) | \
+ DIV_PERIPH(DIV_STAT_CHANGING) | \
+ DIV_ATB(DIV_STAT_CHANGING) | \
+ DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
+ DIV_APLL(DIV_STAT_CHANGING) | \
+ DIV_CORE2(DIV_STAT_CHANGING))
+
+/* CLK_DIV_STAT_CPU1 */
+#define DIV_COPY(x) ((x) & 0x1)
+#define DIV_HPM(x) (((x) & 0x1) << 4)
+#define DIV_CORES(x) (((x) & 0x1) << 8)
+
+#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \
+ DIV_HPM(DIV_STAT_CHANGING) | \
+ DIV_CORES(DIV_STAT_CHANGING))
+
+/* CLK_SRC_DMC */
+#define MUX_C2C_SEL(x) ((x) & 0x1)
+#define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4)
+#define MUX_DPHY_SEL(x) (((x) & 0x1) << 8)
+#define MUX_MPLL_SEL(x) (((x) & 0x1) << 12)
+#define MUX_PWI_SEL(x) (((x) & 0xf) << 16)
+#define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20)
+#define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24)
+#define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28)
+
+/* CLK_MUX_STAT_DMC */
+#define C2C_SEL(x) ((x) & 0x7)
+#define DMC_BUS_SEL(x) (((x) & 0x7) << 4)
+#define DPHY_SEL(x) (((x) & 0x7) << 8)
+#define MPLL_SEL(x) (((x) & 0x7) << 12)
+#define G2D_ACP0_SEL(x) (((x) & 0x7) << 20)
+#define G2D_ACP1_SEL(x) (((x) & 0x7) << 24)
+#define G2D_ACP_SEL(x) (((x) & 0x7) << 28)
+
+#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \
+ DMC_BUS_SEL(MUX_STAT_CHANGING) | \
+ DPHY_SEL(MUX_STAT_CHANGING) | \
+ MPLL_SEL(MUX_STAT_CHANGING) |\
+ G2D_ACP0_SEL(MUX_STAT_CHANGING) | \
+ G2D_ACP1_SEL(MUX_STAT_CHANGING) | \
+ G2D_ACP_SEL(MUX_STAT_CHANGING))
+
+/* CLK_DIV_DMC0 */
+#define ACP_RATIO(x) ((x) & 0x7)
+#define ACP_PCLK_RATIO(x) (((x) & 0x7) << 4)
+#define DPHY_RATIO(x) (((x) & 0x7) << 8)
+#define DMC_RATIO(x) (((x) & 0x7) << 12)
+#define DMCD_RATIO(x) (((x) & 0x7) << 16)
+#define DMCP_RATIO(x) (((x) & 0x7) << 20)
+
+/* CLK_DIV_DMC1 */
+#define G2D_ACP_RATIO(x) ((x) & 0xf)
+#define C2C_RATIO(x) (((x) & 0x7) << 4)
+#define PWI_RATIO(x) (((x) & 0xf) << 8)
+#define C2C_ACLK_RATIO(x) (((x) & 0x7) << 12)
+#define DVSEM_RATIO(x) (((x) & 0x7f) << 16)
+#define DPM_RATIO(x) (((x) & 0x7f) << 24)
+
+/* CLK_DIV_STAT_DMC0 */
+#define DIV_ACP(x) ((x) & 0x1)
+#define DIV_ACP_PCLK(x) (((x) & 0x1) << 4)
+#define DIV_DPHY(x) (((x) & 0x1) << 8)
+#define DIV_DMC(x) (((x) & 0x1) << 12)
+#define DIV_DMCD(x) (((x) & 0x1) << 16)
+#define DIV_DMCP(x) (((x) & 0x1) << 20)
+
+#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \
+ DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
+ DIV_DPHY(DIV_STAT_CHANGING) | \
+ DIV_DMC(DIV_STAT_CHANGING) | \
+ DIV_DMCD(DIV_STAT_CHANGING) | \
+ DIV_DMCP(DIV_STAT_CHANGING))
+
+/* CLK_DIV_STAT_DMC1 */
+#define DIV_G2D_ACP(x) ((x) & 0x1)
+#define DIV_C2C(x) (((x) & 0x1) << 4)
+#define DIV_PWI(x) (((x) & 0x1) << 8)
+#define DIV_C2C_ACLK(x) (((x) & 0x1) << 12)
+#define DIV_DVSEM(x) (((x) & 0x1) << 16)
+#define DIV_DPM(x) (((x) & 0x1) << 24)
+
+#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \
+ DIV_C2C(DIV_STAT_CHANGING) | \
+ DIV_PWI(DIV_STAT_CHANGING) | \
+ DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
+ DIV_DVSEM(DIV_STAT_CHANGING) | \
+ DIV_DPM(DIV_STAT_CHANGING))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ONENAND_1_SEL(x) ((x) & 0x1)
+#define MUX_EPLL_SEL(x) (((x) & 0x1) << 4)
+#define MUX_VPLL_SEL(x) (((x) & 0x1) << 8)
+#define MUX_ACLK_200_SEL(x) (((x) & 0x1) << 12)
+#define MUX_ACLK_100_SEL(x) (((x) & 0x1) << 16)
+#define MUX_ACLK_160_SEL(x) (((x) & 0x1) << 20)
+#define MUX_ACLK_133_SEL(x) (((x) & 0x1) << 24)
+#define MUX_ONENAND_SEL(x) (((x) & 0x1) << 28)
+
+/* CLK_MUX_STAT_TOP */
+#define ONENAND_1_SEL(x) ((x) & 0x3)
+#define EPLL_SEL(x) (((x) & 0x3) << 4)
+#define VPLL_SEL(x) (((x) & 0x3) << 8)
+#define ACLK_200_SEL(x) (((x) & 0x3) << 12)
+#define ACLK_100_SEL(x) (((x) & 0x3) << 16)
+#define ACLK_160_SEL(x) (((x) & 0x3) << 20)
+#define ACLK_133_SEL(x) (((x) & 0x3) << 24)
+#define ONENAND_SEL(x) (((x) & 0x3) << 28)
+
+#define MUX_STAT_TOP0_CHANGING (ONENAND_1_SEL(MUX_STAT_CHANGING) | \
+ EPLL_SEL(MUX_STAT_CHANGING) | \
+ EPLL_SEL(MUX_STAT_CHANGING) | \
+ VPLL_SEL(MUX_STAT_CHANGING) | \
+ ACLK_200_SEL(MUX_STAT_CHANGING) | \
+ ACLK_100_SEL(MUX_STAT_CHANGING) | \
+ ACLK_160_SEL(MUX_STAT_CHANGING) | \
+ ACLK_133_SEL(MUX_STAT_CHANGING) | \
+ ONENAND_SEL(MUX_STAT_CHANGING))
+
+/* CLK_SRC_TOP1 */
+#define MUX_ACLK_266_GPS_SEL(x) (((x) & 0x1) << 4)
+#define MUX_ACLK_400_MCUISP_SEL(x) (((x) & 0x1) << 8)
+#define MUX_MPLL_USER_SEL_T(x) (((x) & 0x1) << 12)
+#define MUX_ACLK_266_GPS_SUB_SEL(x) (((x) & 0x1) << 16)
+#define MUX_ACLK_200_SUB_SEL(x) (((x) & 0x1) << 20)
+#define MUX_ACLK_400_MCUISP_SUB_SEL(x) (((x) & 0x1) << 24)
+
+/* CLK_MUX_STAT_TOP1 */
+#define ACLK_266_GPS_SEL(x) (((x) & 0x3) << 4)
+#define ACLK_400_MCUISP_SEL(x) (((x) & 0x3) << 8)
+#define MPLL_USER_SEL_T(x) (((x) & 0x3) << 12)
+#define ACLK_266_GPS_SUB_SEL(x) (((x) & 0x3) << 16)
+#define ACLK_200_SUB_SEL(x) (((x) & 0x3) << 20)
+#define ACLK_400_MCUISP_SUB_SEL(x) (((x) & 0x3) << 24)
+
+#define MUX_STAT_TOP1_CHANGING (MUX_ACLK_266_GPS_SEL(MUX_STAT_CHANGING) | \
+ ACLK_400_MCUISP_SEL(MUX_STAT_CHANGING) | \
+ MPLL_USER_SEL_T(MUX_STAT_CHANGING) | \
+ ACLK_266_GPS_SUB_SEL(MUX_STAT_CHANGING) | \
+ ACLK_200_SUB_SEL(MUX_STAT_CHANGING) | \
+ ACLK_400_MCUISP_SUB_SEL(MUX_STAT_CHANGING))
+
+/* CLK_DIV_TOP */
+#define ACLK_200_RATIO(x) ((x) & 0x7)
+#define ACLK_100_RATIO(x) (((x) & 0xf) << 4)
+#define ACLK_160_RATIO(x) (((x) & 0x7) << 8)
+#define ACLK_133_RATIO(x) (((x) & 0x7) << 12)
+#define ONENAND_RATIO(x) (((x) & 0x7) << 16)
+#define ACLK_266_GPS_RATIO(x) (((x) & 0x7) << 20)
+#define ACLK_400_MCUISP_RATIO(x) (((x) & 0x7) << 24)
+
+#define DIV_STAT_TOP_CHANGING (ACLK_400_MCUISP_RATIO(DIV_STAT_CHANGING) | \
+ ACLK_266_GPS_RATIO(DIV_STAT_CHANGING) | \
+ ONENAND_RATIO(DIV_STAT_CHANGING) | \
+ ACLK_133_RATIO(DIV_STAT_CHANGING) | \
+ ACLK_160_RATIO(DIV_STAT_CHANGING) | \
+ ACLK_100_RATIO(DIV_STAT_CHANGING) | \
+ ACLK_200_RATIO(DIV_STAT_CHANGING))
+
+/* CLK_SRC_LEFTBUS */
+#define MUX_GDL_SEL(x) ((x) & 0x1)
+#define MUX_MPLL_USER_SEL_L(x) (((x) & 0x1) << 4)
+
+/* CLK_MUX_STAT_LEFTBUS */
+#define GDL_SEL(x) ((x) & 0x7)
+#define MPLL_USER_SEL_L(x) (((x) & 0x7) << 4)
+
+#define MUX_STAT_LEFTBUS_CHANGING (GDL_SEL(MUX_STAT_CHANGING) | \
+ MPLL_USER_SEL_L(MUX_STAT_CHANGING))
+
+/* CLK_DIV_LEFTBUS */
+#define GDL_RATIO(x) ((x) & 0x7)
+#define GPL_RATIO(x) (((x) & 0x7) << 4)
+
+/* CLK_DIV_STAT_LEFTBUS */
+#define DIV_GDL(x) ((x) & 0x1)
+#define DIV_GPL(x) (((x) & 0x1) << 4)
+
+#define DIV_STAT_LEFTBUS_CHANGING (DIV_GDL(DIV_STAT_CHANGING) | \
+ DIV_GPL(DIV_STAT_CHANGING))
+
+/* CLK_SRC_RIGHTBUS */
+#define MUX_GDR_SEL(x) ((x) & 0x1)
+#define MUX_MPLL_USER_SEL_R(x) (((x) & 0x1) << 4)
+
+/* CLK_MUX_STAT_RIGHTBUS */
+#define GDR_SEL(x) ((x) & 0x7)
+#define MPLL_USER_SEL_R(x) (((x) & 0x7) << 4)
+
+#define MUX_STAT_RIGHTBUS_CHANGING (GDR_SEL(MUX_STAT_CHANGING) | \
+ MPLL_USER_SEL_R(MUX_STAT_CHANGING))
+
+/* CLK_DIV_RIGHTBUS */
+#define GPR_RATIO(x) ((x) & 0x7)
+#define GDR_RATIO(x) (((x) & 0x7) << 4)
+
+/* CLK_DIV_STAT_RIGHTBUS */
+#define DIV_GDR(x) ((x) & 0x1)
+#define DIV_GPR(x) ((x) & 0x1)
+
+#define DIV_STAT_RIGHTBUS_CHANGING (DIV_GDR(DIV_STAT_CHANGING) | \
+ DIV_GPR(DIV_STAT_CHANGING))
+
+/* CLK_SRC_PERIL0 */
+#define UART0_SEL(x) ((x) & 0xf)
+#define UART1_SEL(x) (((x) & 0xf) << 4)
+#define UART2_SEL(x) (((x) & 0xf) << 8)
+#define UART3_SEL(x) (((x) & 0xf) << 12)
+#define UART4_SEL(x) (((x) & 0xf) << 16)
+
+/* CLK_DIV_PERIL0 */
+#define UART0_RATIO(x) ((x) & 0xf)
+#define UART1_RATIO(x) (((x) & 0xf) << 4)
+#define UART2_RATIO(x) (((x) & 0xf) << 8)
+#define UART3_RATIO(x) (((x) & 0xf) << 12)
+#define UART4_RATIO(x) (((x) & 0xf) << 16)
+
+/* CLK_DIV_STAT_PERIL0 */
+#define DIV_UART0(x) ((x) & 0x1)
+#define DIV_UART1(x) (((x) & 0x1) << 4)
+#define DIV_UART2(x) (((x) & 0x1) << 8)
+#define DIV_UART3(x) (((x) & 0x1) << 12)
+#define DIV_UART4(x) (((x) & 0x1) << 16)
+
+#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
+ DIV_UART3(DIV_STAT_CHANGING) | \
+ DIV_UART2(DIV_STAT_CHANGING) | \
+ DIV_UART1(DIV_STAT_CHANGING) | \
+ DIV_UART0(DIV_STAT_CHANGING))
+
+/* CLK_SRC_FSYS */
+#define MMC1_SEL(x) (((x) & 0xf) << 4)
+#define MMC2_SEL(x) (((x) & 0xf) << 8)
+#define MMC3_SEL(x) (((x) & 0xf) << 12)
+#define MMC4_SEL(x) (((x) & 0xf) << 16)
+#define MIPIHSI_SEL(x) (((x) & 0x1) << 24)
+
+/* CLK_DIV_FSYS0 */
+#define MIPIHSI_RATIO(x) (((x) & 0xf) << 20)
+
+/* CLK_DIV_STAT_FSYS0 */
+#define DIV_MIPIHSI(x) (((x) & 0x1) << 20)
+
+#define DIV_STAT_FSYS0_CHANGING (DIV_MIPIHSI(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS1 */
+#define MMC0_RATIO(x) ((x) & 0xf)
+#define MMC0_PRE_RATIO(x) (((x) & 0xff) << 8)
+#define MMC1_RATIO(x) (((x) & 0xf) << 16)
+#define MMC1_PRE_RATIO(x) (((x) & 0xff) << 24)
+
+/* CLK_DIV_STAT_FSYS1 */
+#define DIV_MMC0(x) ((x) & 1)
+#define DIV_MMC0_PRE(x) (((x) & 1) << 8)
+#define DIV_MMC1(x) (((x) & 1) << 16)
+#define DIV_MMC1_PRE(x) (((x) & 1) << 24)
+
+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
+ DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
+ DIV_MMC1(DIV_STAT_CHANGING) | \
+ DIV_MMC1_PRE(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO(x) ((x) & 0xf)
+#define MMC2_PRE_RATIO(x) (((x) & 0xff) << 8)
+#define MMC3_RATIO(x) (((x) & 0xf) << 16)
+#define MMC3_PRE_RATIO(x) (((x) & 0xff) << 24)
+
+/* CLK_DIV_STAT_FSYS2 */
+#define DIV_MMC2(x) ((x) & 0x1)
+#define DIV_MMC2_PRE(x) (((x) & 0x1) << 8)
+#define DIV_MMC3(x) (((x) & 0x1) << 16)
+#define DIV_MMC3_PRE(x) (((x) & 0x1) << 24)
+
+#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \
+ DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
+ DIV_MMC3(DIV_STAT_CHANGING) | \
+ DIV_MMC3_PRE(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS3 */
+#define MMC4_RATIO(x) ((x) & 0x7)
+#define MMC4_PRE_RATIO(x) (((x) & 0xff) << 8)
+
+/* CLK_DIV_STAT_FSYS3 */
+#define DIV_MMC4(x) ((x) & 0x1)
+#define DIV_MMC4_PRE(x) (((x) & 0x1) << 8)
+
+#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \
+ DIV_MMC4_PRE(DIV_STAT_CHANGING))
+
+/* DMC */
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200
+#endif
+#ifdef CONFIG_CLK_1000_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_400_200
+#define DRAM_CLK_400
+#endif
+
+/* Bus Configuration Register Address */
+#define ASYNC_CONFIG 0x10010350
+
+#define DIRECT_CMD_NOP 0x07000000
+#define DIRECT_CMD_ZQ 0x0a000000
+#define DIRECT_CMD_CHIP1_SHIFT (1 << 20)
+#define MEM_TIMINGS_MSR_COUNT 4
+#define CTRL_START (1 << 0)
+#define CTRL_DLL_ON (1 << 1)
+#define AREF_EN (1 << 5)
+#define DRV_TYPE (1 << 6)
+
+struct mem_timings {
+ unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
+ unsigned timingref;
+ unsigned timingrow;
+ unsigned timingdata;
+ unsigned timingpower;
+ unsigned zqcontrol;
+ unsigned control0;
+ unsigned control1;
+ unsigned control2;
+ unsigned concontrol;
+ unsigned prechconfig;
+ unsigned memcontrol;
+ unsigned memconfig0;
+ unsigned memconfig1;
+ unsigned dll_resync;
+ unsigned dll_on;
+};
+
+/* MIU */
+/* MIU Config Register Offsets*/
+#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
+#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
+#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
+#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
+#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
+
+#if (defined CONFIG_ORIGEN) || (defined CONFIG_EX4412)
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
+#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
+#endif
+
+#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000
+#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff
+#define INTERLEAVE_ADDR_MAP_EN 0x00000001
+
+#ifdef CONFIG_MIU_1BIT_INTERLEAVED
+/* Interleave_bit0: 0xC*/
+#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c
+#endif
+#ifdef CONFIG_MIU_2BIT_INTERLEAVED
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
+#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c
+#endif
+#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000
+#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff
+#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000
+#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff
+/* Enable SME0 and SME1*/
+#define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006
+
+#define FORCE_DLL_RESYNC 3
+#define DLL_CONTROL_ON 1
+
+#define DIRECT_CMD1 0x00020000
+#define DIRECT_CMD2 0x00030000
+#define DIRECT_CMD3 0x00010002
+#define DIRECT_CMD4 0x00000328
+
+#define CTRL_ZQ_MODE_NOTERM (0x1 << 0)
+#define CTRL_ZQ_START (0x1 << 1)
+#define CTRL_ZQ_DIV (0 << 4)
+#define CTRL_ZQ_MODE_DDS (0x7 << 8)
+#define CTRL_ZQ_MODE_TERM (0x2 << 11)
+#define CTRL_ZQ_FORCE_IMPN (0x5 << 14)
+#define CTRL_ZQ_FORCE_IMPP (0x6 << 17)
+#define CTRL_DCC (0xE38 << 20)
+/*
+#define ZQ_CONTROL_VAL (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
+ | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
+ | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
+ | CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
+*/
+#define ZQ_CONTROL_VAL 0xe3855403
+
+#define ASYNC (0 << 0)
+#define CLK_RATIO (1 << 1)
+#define DIV_PIPE (1 << 3)
+#define AWR_ON (1 << 4)
+#define AREF_DISABLE (0 << 5)
+#define DRV_TYPE_DISABLE (0 << 6)
+#define CHIP0_NOT_EMPTY (0 << 8)
+#define CHIP1_NOT_EMPTY (0 << 9)
+#define DQ_SWAP_DISABLE (0 << 10)
+#define QOS_FAST_DISABLE (0 << 11)
+#define RD_FETCH (0x3 << 12)
+#define TIMEOUT_LEVEL0 (0xFFF << 16)
+#define CONCONTROL_VAL (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
+ | AREF_DISABLE | DRV_TYPE_DISABLE\
+ | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
+ | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
+ | RD_FETCH | TIMEOUT_LEVEL0)
+
+#define CLK_STOP_DISABLE (0 << 1)
+#define DPWRDN_DISABLE (0 << 2)
+#define DPWRDN_TYPE (0 << 3)
+#define TP_DISABLE (0 << 4)
+#define DSREF_DIABLE (0 << 5)
+#define ADD_LAT_PALL (1 << 6)
+#define MEM_TYPE_DDR3 (0x6 << 8)
+#define MEM_WIDTH_32 (0x2 << 12)
+#define NUM_CHIP_2 (0 << 16)
+#define BL_8 (0x3 << 20)
+/*
+#define MEMCONTROL_VAL (CLK_STOP_DISABLE | DPWRDN_DISABLE\
+ | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
+ | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
+ | NUM_CHIP_2 | BL_8)
+*/
+#define MEMCONTROL_VAL 0x00202500
+
+#define CHIP_BANK_8 (0x3 << 0)
+#define CHIP_ROW_14 (0x3 << 4)
+#define CHIP_COL_10 (0x3 << 8)
+#define CHIP_MAP_INTERLEAVED (1 << 12)
+#define CHIP_MASK (0xC0 << 16)
+#ifdef CONFIG_MIU_LINEAR
+#define CHIP0_BASE (0x40 << 24)
+#define CHIP1_BASE (0x60 << 24)
+#else
+#define CHIP0_BASE (0x40 << 24)
+#define CHIP1_BASE (0x80 << 24)
+#endif
+/*
+#define MEMCONFIG0_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
+ | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
+*/
+#define MEMCONFIG1_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
+ | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
+
+#define MEMCONFIG0_VAL 0x40c01323
+
+#define TP_CNT (0xff << 24)
+#define PRECHCONFIG TP_CNT
+
+#define CTRL_OFF (0 << 0)
+#define CTRL_DLL_OFF (0 << 1)
+#define CTRL_HALF (0 << 2)
+#define CTRL_DFDQS (1 << 3)
+#define DQS_DELAY (0 << 4)
+#define CTRL_START_POINT (0x10 << 8)
+#define CTRL_INC (0x10 << 16)
+#define CTRL_FORCE (0x71 << 24)
+#define CONTROL0_VAL (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
+ | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
+ | CTRL_INC | CTRL_FORCE)
+
+#define CTRL_SHIFTC (0x6 << 0)
+#define CTRL_REF (8 << 4)
+#define CTRL_SHGATE (1 << 29)
+#define TERM_READ_EN (1 << 30)
+#define TERM_WRITE_EN (1 << 31)
+#define CONTROL1_VAL (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
+ | TERM_READ_EN | TERM_WRITE_EN)
+
+#define CONTROL2_VAL 0x00000000
+
+#ifdef CONFIG_EX4412
+#define TIMINGREF_VAL 0x000000BB
+#define TIMINGROW_VAL 0x4046654f
+#define TIMINGDATA_VAL 0x46400506
+#define TIMINGPOWER_VAL 0x52000A3C
+#else
+#define TIMINGREF_VAL 0x000000BC
+#ifdef DRAM_CLK_330
+#define TIMINGROW_VAL 0x3545548d
+#define TIMINGDATA_VAL 0x45430506
+#define TIMINGPOWER_VAL 0x4439033c
+#endif
+#ifdef DRAM_CLK_400
+#define TIMINGROW_VAL 0x45430506
+#define TIMINGDATA_VAL 0x56500506
+#define TIMINGPOWER_VAL 0x5444033d
+#endif
+#endif
+
+#ifdef CONFIG_BOARD_TYPES
+extern void sdelay(unsigned long);
+#endif
+
+
+#endif4.修改初始化内存的dmc_init_exynos4.c文件
--- a/arch/arm/mach-exynos/dmc_init_exynos4.c
+++ b/arch/arm/mach-exynos/dmc_init_exynos4.c
@@ -25,8 +25,10 @@
#include <config.h>
#include <asm/arch/dmc.h>
+#include <debug_uart.h>
#include "common_setup.h"
-#include "exynos4_setup.h"
+/*#include "exynos4_setup.h" */
+#include "ex4412_setup.h"
struct mem_timings mem = {
.direct_cmd_msr = {
@@ -48,6 +50,46 @@ struct mem_timings mem = {
.dll_resync = FORCE_DLL_RESYNC,
.dll_on = DLL_CONTROL_ON,
};
+
+
+#ifdef CONFIG_EX4412
+/*简易测试tiny4412内存情况,如果读出的值正常，即初步判断内存初始化正常*/
+void tiny4412_mem_test(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ unsigned int i;
+
+ printascii("Simple Memory test start...\r\n");
+ printascii("write 0x12345678 ...\r\n");
+ for (i = 0x40000000;
+ i < 0x80000000; i+=0x10000000)
+ {
+ writel(0x12345678, i);
+ printascii("addr:0x");
+ printhex8(i);
+ printascii("--data:");
+ printascii("0x");
+ printhex8(readl(i));
+ printascii("\r\n");
+ }
+ printascii("write 0x89abcdef ...\r\n");
+ for (i = 0x4FFFFFFC;
+ i <= 0x7FFFFFFC; i+=0x10000000)
+ {
+ writel(0x89ABCDEF, i);
+ printascii("addr:0x");
+ printhex8(i);
+ printascii("--data:");
+ printascii("0x");
+ printhex8(readl(i));
+ printascii("\r\n");
+ }
+ printascii("Memory test end.\r\n\r\n");
+#endif
+
+}
+#endif
+
static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
{
if (ctrl_no) {
@@ -80,89 +122,63 @@ static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)
static void dmc_init(struct exynos4_dmc *dmc)
{
/*
- * DLL Parameter Setting:
- * Termination: Enable R/W
- * Phase Delay for DQS Cleaning: 180' Shift
- */
- writel(mem.control1, &dmc->phycontrol1);
-
- /*
* ZQ Calibration
* Termination: Disable
* Auto Calibration Start: Enable
*/
writel(mem.zqcontrol, &dmc->phyzqcontrol);
- sdelay(0x100000);
+// sdelay(0x100000);
- /*
- * Update DLL Information:
- * Force DLL Resyncronization
- */
- phy_control_reset(1, dmc);
- phy_control_reset(0, dmc);
+ writel(0x71101008, &dmc->phycontrol0);
+ writel(0x7110100a, &dmc->phycontrol0);
+ writel(0x00000084, &dmc->phycontrol1);
+ writel(0x71101008, &dmc->phycontrol0);
+ writel(0x0000008c, &dmc->phycontrol1);
+ writel(0x00000084, &dmc->phycontrol1);
+ writel(0x0000008c, &dmc->phycontrol1);
+ writel(0x00000084, &dmc->phycontrol1);
- /* Set DLL Parameters */
- writel(mem.control1, &dmc->phycontrol1);
+ writel(0x0fff30ca, &dmc->concontrol);
- /* DLL Start */
- writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0);
-
- writel(mem.control2, &dmc->phycontrol2);
-
- /* Set Clock Ratio of Bus clock to Memory Clock */
- writel(mem.concontrol, &dmc->concontrol);
-
- /*
- * Memor Burst length: 8
- * Number of chips: 2
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 1 Cycle
- */
writel(mem.memcontrol, &dmc->memcontrol);
writel(mem.memconfig0, &dmc->memconfig0);
- writel(mem.memconfig1, &dmc->memconfig1);
+ writel(0x8000001D, &dmc->ivcontrol);
/* Config Precharge Policy */
writel(mem.prechconfig, &dmc->prechconfig);
/*
* TimingAref, TimingRow, TimingData, TimingPower Setting:
* Values as per Memory AC Parameters
*/
- writel(mem.timingref, &dmc->timingref);
- writel(mem.timingrow, &dmc->timingrow);
- writel(mem.timingdata, &dmc->timingdata);
- writel(mem.timingpower, &dmc->timingpower);
+ writel(0x0000005d, &dmc->timingref);
+ writel(0x34498691, &dmc->timingrow);
+ writel(0x36330306, &dmc->timingdata);
+ writel(0x50380365, &dmc->timingpower);
+ sdelay(0x100000);
/* Chip0: NOP Command: Assert and Hold CKE to high level */
- writel(DIRECT_CMD_NOP, &dmc->directcmd);
+ writel(0x07000000, &dmc->directcmd);
sdelay(0x100000);
- /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
- dmc_config_mrs(dmc, 0);
+ writel(0x00071c00, &dmc->directcmd);
sdelay(0x100000);
- /* Chip0: ZQINIT */
- writel(DIRECT_CMD_ZQ, &dmc->directcmd);
+ writel(0x00010bfc, &dmc->directcmd);
sdelay(0x100000);
- writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
- sdelay(0x100000);
+ writel(0x00000488, &dmc->directcmd);
+// sdelay(0x100000);
- /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
- dmc_config_mrs(dmc, 1);
- sdelay(0x100000);
- /* Chip1: ZQINIT */
- writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
- sdelay(0x100000);
+ writel(0x00000810, &dmc->directcmd);
+// sdelay(0x100000);
- phy_control_reset(1, dmc);
- sdelay(0x100000);
+ writel(0x00000c08, &dmc->directcmd);
+// sdelay(0x100000);
/* turn on DREX0, DREX1 */
- writel((mem.concontrol | AREF_EN), &dmc->concontrol);
+ writel(0x0FFF303a, &dmc->concontrol);
}
void mem_ctrl_init(int reset)
@@ -175,13 +191,12 @@ void mem_ctrl_init(int reset)
* 0: full_sync
*/
writel(1, ASYNC_CONFIG);
-#ifdef CONFIG_TARGET_ORIGEN
- /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
- writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
- APB_SFR_INTERLEAVE_CONF_OFFSET);
- /* Update MIU Configuration */
- writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +
- APB_SFR_ARBRITATION_CONF_OFFSET);
+#ifdef CONFIG_EX4412
+ writel(0x13113113, 0x10030000 + 0x10500);
+
+ writel(0x00117713, 0x10040500);
+ writel(0x00000000, 0x10020a00);
+ writel(0x00010905, 0x10040a00);
#else
writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
APB_SFR_INTERLEAVE_CONF_OFFSET);5.修改clock.c
关于mmc和lcd部分，本文未实现这两个外设驱动功能，此处暂且先作修改，网文提到该文件错用struct exynos4_clock结构体，应该改为struct exynos4x12_clock，修改如下：
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -784,8 +784,13 @@ static unsigned long exynos4x12_get_uart_clk(int dev_index)
static unsigned long exynos4_get_mmc_clk(int dev_index)
{
+#ifdef CONFIG_EX4412
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+#else
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
+#endif
unsigned long uclk, sclk;
unsigned int sel, ratio, pre_ratio;
int shift = 0;
@@ -834,8 +839,13 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
+#ifdef CONFIG_EX4412
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+#else
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
+#endif
unsigned int addr, clear_bit, set_bit;
/*
@@ -913,8 +923,13 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
/* get_lcd_clk: return lcd clock frequency */
static unsigned long exynos4_get_lcd_clk(void)
{
+#ifdef CONFIG_EX4412
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+#else
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
+#endif
unsigned long pclk, sclk;
unsigned int sel;
unsigned int ratio;
@@ -923,7 +938,11 @@ static unsigned long exynos4_get_lcd_clk(void)
* CLK_SRC_LCD0
* FIMD0_SEL [3:0]
*/
+#ifdef CONFIG_EX4412
+ sel = readl(&clk->src_lcd);
+#else
sel = readl(&clk->src_lcd0);
+#endif
sel = sel & 0xf;
/*
@@ -944,7 +963,11 @@ static unsigned long exynos4_get_lcd_clk(void)
* CLK_DIV_LCD0
* FIMD0_RATIO [3:0]
*/
+#ifdef CONFIG_EX4412
+ ratio = readl(&clk->div_lcd);
+#else
ratio = readl(&clk->div_lcd0);
+#endif
ratio = ratio & 0xf;
pclk = sclk / (ratio + 1);
@@ -1064,9 +1087,13 @@ static unsigned long exynos5800_get_lcd_clk(void)
void exynos4_set_lcd_clk(void)
{
+#ifdef CONFIG_EX4412
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+#else
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
-
+#endif
/*
* CLK_GATE_BLOCK
* CLK_CAM [0]
@@ -1087,8 +1114,11 @@ void exynos4_set_lcd_clk(void)
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
+#ifdef CONFIG_EX4412
+ clrsetbits_le32(&clk->src_lcd, 0xf, 0x6);
+#else
clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
-
+#endif
/*
* CLK_GATE_IP_LCD0
* CLK_FIMD0 [0]
@@ -1099,8 +1129,11 @@ void exynos4_set_lcd_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
+#ifdef CONFIG_EX4412
+ setbits_le32(&clk->gate_ip_lcd, 1 << 0);
+#else
setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
-
+#endif
/*
* CLK_DIV_LCD0
* FIMD0_RATIO [3:0]
@@ -1111,7 +1144,11 @@ void exynos4_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
+#ifdef CONFIG_EX4412
+ clrsetbits_le32(&clk->div_lcd, 0xf, 0x1);
+#else
clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
+#endif
}
void exynos5_set_lcd_clk(void) 6.修改arch/arm/mach-exynos/lowlevel_init.c
--- a/arch/arm/mach-exynos/lowlevel_init.c
+++ b/arch/arm/mach-exynos/lowlevel_init.c
@@ -39,6 +39,7 @@
#include "common_setup.h"
#include "exynos5_setup.h"
+extern void mem_init(void);
/* These are the things we can do during low-level init */
enum {
DO_WAKEUP = 1 << 0,
@@ -170,10 +171,38 @@ static void secondary_cores_configure(void)
dsb();
sev();
}
-
extern void relocate_wait_code(void);
#endif
-
+/*
+void test_uart()
+ {
+ unsigned int addr = 0x11400000;
+ writel(0x22222222,addr);
+ writel(0x222222,addr+0x20);
+
+ addr = (unsigned int *)0x1003c250;
+ writel(0x666666,addr);
+
+ addr = (unsigned int *)0x1003c250;
+ writel(0x777777,addr);
+
+ addr = (unsigned int *)0x13820000;
+ #define ULCON_OFFSET 0x00
+ #define UCON_OFFSET 0x04
+ #define UFCON_OFFSET 0x08
+ #define UBRDIV_OFFSET 0x28
+ #define UDIVLOT_OFFSET 0x2c
+ #define UTXH_OFFSET 0x20
+ writel(0x111, addr+UFCON_OFFSET);
+ writel(0x03, addr+ULCON_OFFSET);
+ writel(0x3c5, addr+UCON_OFFSET);
+ writel(0x35, addr+UBRDIV_OFFSET);
+ writel(0x3, addr+UDIVLOT_OFFSET);
+ writel(0x4f, addr+UTXH_OFFSET);
+ writel(0x4b, addr+UTXH_OFFSET);
+ return;
+ }
+*/
int do_lowlevel_init(void)
{
uint32_t reset_status;
@@ -200,7 +229,6 @@ int do_lowlevel_init(void)
/* Reconfigure secondary cores */
secondary_cores_configure();
#endif
-
reset_status = get_reset_status();
switch (reset_status) {
@@ -222,14 +250,16 @@ int do_lowlevel_init(void)
if (actions & DO_CLOCKS) {
system_clock_init();
#ifdef CONFIG_DEBUG_UART
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \
- !defined(CONFIG_SPL_BUILD)
- exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+/*#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \
+ !defined(CONFIG_SPL_BUILD) */
+ exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
debug_uart_init();
-#endif
+/*#endif */
+ printascii("do_lowlevel_init ok\r\n");
#endif
mem_ctrl_init(actions & DO_MEM_RESET);
- tzpc_init();
+
+/* tzpc_init(); */
}
return actions & DO_WAKEUP;7.修改电源配置
- 修改与板子exynos4412芯片适配的结构体exynos4x12_power,配置如下：
diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h
index a3d8974..8b706ee 100644
--- a/arch/arm/mach-exynos/include/mach/power.h
+++ b/arch/arm/mach-exynos/include/mach/power.h
@@ -209,6 +209,214 @@ struct exynos4_power {
unsigned int gps_alive_option;
};
+struct exynos4x12_power {
+ unsigned int om_stat;
+ unsigned char res1[0xc];
+ unsigned int rtc_clko_sel;
+ unsigned int gnss_rtc_out_ctrl;
+ unsigned int lpi_denial_mask0;
+ unsigned int lpi_denial_mask1;
+ unsigned int lpi_denial_mask2;
+ unsigned int c2c_ctrl;
+ unsigned char res2[0x1d8];
+ unsigned int central_seq_config;
+ unsigned int res3;
+ unsigned int central_seq_option;
+ unsigned char res4[0x1f4];
+ unsigned int swreset;
+ unsigned int rst_stat;
+ unsigned int auto_wdt_reset_disable;
+ unsigned int mask_wdt_reset_request;
+ unsigned char res5[0x1f0];
+ unsigned int wakeup_stat;
+ unsigned int eint_wakeup_mask;
+ unsigned int wakeup_mask;
+ unsigned char res6[0xf4];
+ unsigned int hdmi_phy_control;
+ unsigned int usbdevice_phy_control;
+ unsigned int hsic_1_phy_control;
+ unsigned int hsic_2_phy_control;
+ unsigned int mipi_phy0_control;
+ unsigned int mipi_phy1_control;
+ unsigned int adc_phy_control;
+ unsigned char res7[0x64];
+ unsigned int body_bias_con0;
+ unsigned int body_bias_con1;
+ unsigned int body_bias_con2;
+ unsigned int body_bias_con3;
+ unsigned char res8[0x70];
+ unsigned int inform0;
+ unsigned int inform1;
+ unsigned int inform2;
+ unsigned int inform3;
+ unsigned int inform4;
+ unsigned int inform5;
+ unsigned int inform6;
+ unsigned int inform7;
+ unsigned char res9[0x1e0];
+ unsigned int pmu_debug;
+ unsigned char res10[0x5fc];
+ unsigned int arm_core0_sys_pwr_reg;
+ unsigned char res11[0xc];
+ unsigned int arm_core1_sys_pwr_reg;
+ unsigned char res12[0x6c];
+ unsigned int arm_common_sys_pwr_reg;
+ unsigned char res13[0x3c];
+ unsigned int arm_cpu_l2_0_sys_pwr_reg;
+ unsigned int arm_cpu_l2_1_sys_pwr_reg;
+ unsigned char res14[0x38];
+ unsigned int cmu_aclkstop_sys_pwr_reg;
+ unsigned int cmu_sclkstop_sys_pwr_reg;
+ unsigned char res15[0x4];
+ unsigned int cmu_reset_sys_pwr_reg;
+ unsigned char res16[0x10];
+ unsigned int apll_sysclk_sys_pwr_reg;
+ unsigned int mpll_sysclk_sys_pwr_reg;
+ unsigned int vpll_sysclk_sys_pwr_reg;
+ unsigned int epll_sysclk_sys_pwr_reg;
+ unsigned char res17[0x8];
+ unsigned int cmu_clkstop_gps_alive_sys_pwr_reg;
+ unsigned int cmu_reset_gps_alive_sys_pwr_reg;
+ unsigned int cmu_clkstop_cam_sys_pwr_reg;
+ unsigned int cmu_clkstop_tv_sys_pwr_reg;
+ unsigned int cmu_clkstop_mfc_sys_pwr_reg;
+ unsigned int cmu_clkstop_g3d_sys_pwr_reg;
+ unsigned int cmu_clkstop_lcd0_sys_pwr_reg;
+ unsigned int cmu_clkstop_isp_sys_pwr_reg;
+ unsigned int cmu_clkstop_maudio_sys_pwr_reg;
+ unsigned int cmu_clkstop_gps_sys_pwr_reg;
+ unsigned int cmu_reset_cam_sys_pwr_reg;
+ unsigned int cmu_reset_tv_sys_pwr_reg;
+ unsigned int cmu_reset_mfc_sys_pwr_reg;
+ unsigned int cmu_reset_g3d_sys_pwr_reg;
+ unsigned int cmu_reset_lcd0_sys_pwr_reg;
+ unsigned int cmu_reset_isp_sys_pwr_reg;
+ unsigned int cmu_reset_maudio_sys_pwr_reg;
+ unsigned int cmu_reset_gps_sys_pwr_reg;
+ unsigned int top_bus_sys_pwr_reg;
+ unsigned int top_retention_sys_pwr_reg;
+ unsigned int top_pwr_sys_pwr_reg;
+ unsigned char res18[0x14];
+ unsigned int logic_reset_sys_pwr_reg;
+ unsigned char res19[0x1c];
+ unsigned int onenandxl_mem_sys_pwr_reg;
+ unsigned int hsi_mem_sys_pwr_reg;
+ unsigned char res20[0x4];
+ unsigned int usbotg_mem_sys_pwr_reg;
+ unsigned int sdmmc_mem_sys_pwr_reg;
+ unsigned int cssys_mem_sys_pwr_reg;
+ unsigned int secss_mem_sys_pwr_reg;
+ unsigned int potator_mem_sys_pwr_reg;
+ unsigned char res21[0x20];
+ unsigned int pad_retention_dram_sys_pwr_reg;
+ unsigned int pad_retention_maudio_sys_pwr_reg;
+ unsigned char res22[0x18];
+ unsigned int pad_retention_gpio_sys_pwr_reg;
+ unsigned int pad_retention_uart_sys_pwr_reg;
+ unsigned int pad_retention_mmca_sys_pwr_reg;
+ unsigned int pad_retention_mmcb_sys_pwr_reg;
+ unsigned int pad_retention_ebia_sys_pwr_reg;
+ unsigned int pad_retention_ebib_sys_pwr_reg;
+ unsigned char res23[0x8];
+ unsigned int pad_isolation_sys_pwr_reg;
+ unsigned char res24[0x1c];
+ unsigned int pad_alv_sel_sys_pwr_reg;
+ unsigned char res25[0x1c];
+ unsigned int xusbxti_sys_pwr_reg;
+ unsigned int xxti_sys_pwr_reg;
+ unsigned char res26[0x38];
+ unsigned int ext_regulator_sys_pwr_reg;
+ unsigned char res27[0x3c];
+ unsigned int gpio_mode_sys_pwr_reg;
+ unsigned char res28[0x3c];
+ unsigned int gpio_mode_maudio_sys_pwr_reg;
+ unsigned char res29[0x3c];
+ unsigned int cam_sys_pwr_reg;
+ unsigned int tv_sys_pwr_reg;
+ unsigned int mfc_sys_pwr_reg;
+ unsigned int g3d_sys_pwr_reg;
+ unsigned int lcd0_sys_pwr_reg;
+ unsigned int isp_sys_pwr_reg;
+ unsigned int maudio_sys_pwr_reg;
+ unsigned int gps_sys_pwr_reg;
+ unsigned int gps_alive_sys_pwr_reg;
+ unsigned char res30[0xc5c];
+ unsigned int arm_core0_configuration;
+ unsigned int arm_core0_status;
+ unsigned int arm_core0_option;
+ unsigned char res31[0x74];
+ unsigned int arm_core1_configuration;
+ unsigned int arm_core1_status;
+ unsigned int arm_core1_option;
+ unsigned char res32[0x37c];
+ unsigned int arm_common_option;
+ unsigned char res33[0x1f4];
+ unsigned int arm_cpu_l2_0_configuration;
+ unsigned int arm_cpu_l2_0_status;
+ unsigned char res34[0x18];
+ unsigned int arm_cpu_l2_1_configuration;
+ unsigned int arm_cpu_l2_1_status;
+ unsigned char res35[0xa00];
+ unsigned int pad_retention_maudio_option;
+ unsigned char res36[0xdc];
+ unsigned int pad_retention_gpio_option;
+ unsigned char res37[0x1c];
+ unsigned int pad_retention_uart_option;
+ unsigned char res38[0x1c];
+ unsigned int pad_retention_mmca_option;
+ unsigned char res39[0x1c];
+ unsigned int pad_retention_mmcb_option;
+ unsigned char res40[0x1c];
+ unsigned int pad_retention_ebia_option;
+ unsigned char res41[0x1c];
+ unsigned int pad_retention_ebib_option;
+ unsigned char res42[0x160];
+ unsigned int ps_hold_control;
+ unsigned char res43[0xf0];
+ unsigned int xusbxti_configuration;
+ unsigned int xusbxti_status;
+ unsigned char res44[0x14];
+ unsigned int xusbxti_duration;
+ unsigned int xxti_configuration;
+ unsigned int xxti_status;
+ unsigned char res45[0x14];
+ unsigned int xxti_duration;
+ unsigned char res46[0x1dc];
+ unsigned int ext_regulator_duration;
+ unsigned char res47[0x5e0];
+ unsigned int cam_configuration;
+ unsigned int cam_status;
+ unsigned int cam_option;
+ unsigned char res48[0x14];
+ unsigned int tv_configuration;
+ unsigned int tv_status;
+ unsigned int tv_option;
+ unsigned char res49[0x14];
+ unsigned int mfc_configuration;
+ unsigned int mfc_status;
+ unsigned int mfc_option;
+ unsigned char res50[0x14];
+ unsigned int g3d_configuration;
+ unsigned int g3d_status;
+ unsigned int g3d_option;
+ unsigned char res51[0x14];
+ unsigned int lcd0_configuration;
+ unsigned int lcd0_status;
+ unsigned int lcd0_option;
+ unsigned char res52[0x14];
+ unsigned int isp_configuration;
+ unsigned int isp_status;
+ unsigned int isp_option;
+ unsigned char res53[0x34];
+ unsigned int gps_configuration;
+ unsigned int gps_status;
+ unsigned int gps_option;
+ unsigned char res54[0x14];
+ unsigned int gps_alive_configuration;
+ unsigned int gps_alive_status;
+ unsigned int gps_alive_option;
+};
+
struct exynos4412_power {
unsigned char res1[0x0704];
unsigned int usbhost_phy_control;- 修改power.c
当写有启动板子时有亮灯效果的程序时，通过锁电，让板子启动时不会只亮一下灯就熄灭，而是一直亮着，但实际测试时writel(0x3, (unsigned int *)0x11000c08);当把0x3改为别的数值时，灯也会是启动后一直亮着。
diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c
index f2a6c00..afccade 100644
--- a/arch/arm/mach-exynos/power.c
+++ b/arch/arm/mach-exynos/power.c
@@ -162,6 +162,28 @@ static void exynos5_set_ps_hold_ctrl(void)
EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
}
+static void exynos4x12_set_ps_hold_ctrl(void)
+{
+ struct exynos4x12_power *power =
+ (struct exynos4x12_power *)samsung_get_base_power();
+
+ /* value: 1000000000B */
+ setbits_le32(&power->ps_hold_control, EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
+ /**
+ * GPX0PUD register
+ *
+ * 0x0 = Disables Pull-up/Pull-down
+ * 0x1 = Enables Pull-down
+ * 0x2 = Reserved
+ * 0x3 = Enables Pull-up
+ * Due to GPX0_2 attached to PMIC's ONO pin,
+ * make GPX0_2 pin PU for high level,
+ * but all other pin default state for low level
+ * otherwise, keep restarting 0x5575
+ */
+ writel(0x3, (unsigned int *)0x11000c08);
+}
+
/*
* Set ps_hold data driving value high
* This enables the machine to stay powered on
@@ -172,6 +194,12 @@ void set_ps_hold_ctrl(void)
{
if (cpu_is_exynos5())
exynos5_set_ps_hold_ctrl();
+ #ifdef CONFIG_EX4412
+ else if (cpu_is_exynos4()){
+/* if (proid_is_exynos4412()) */
+ exynos4x12_set_ps_hold_ctrl();
+ }
+ #endif
}
@@ -213,9 +241,13 @@ static uint32_t exynos5_get_reset_status(void)
static uint32_t exynos4_get_reset_status(void)
{
+#ifdef CONFIG_EX4412
+ struct exynos4x12_power *power =
+ (struct exynos4x12_power *)samsung_get_base_power();
+#else
struct exynos4_power *power =
(struct exynos4_power *)samsung_get_base_power();
-
+#endif
return power->inform1;
}- 新增启动板子时亮灯程序arch/arm/mach-exynos/board.c，用以提示板子是否初始化成功
#include <common.h>
#include <config.h>
#include <asm/io.h>
void s_init(void)
{
/* led test */
writel(0x10, 0x11000060);
writel(0x2, 0x11000064);
writel(0x1, 0x11000100);
writel(0x1, 0x11000104);
}
8.修改arch/arm/mach-exynos/spl_boot.c，拷贝uboot到dram。
diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index f518539..aa4e52a 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c
@@ -18,11 +18,12 @@
#include <asm/arch/power.h>
#include <asm/arch/spl.h>
#include <asm/arch/spi.h>
+#include <debug_uart.h>
#include "common_setup.h"
#include "clock_init.h"
-#ifdef CONFIG_ARCH_EXYNOS5
+#ifdef CONFIG_ARCH_EXYNOS5
#define SECURE_BL1_ONLY
/* Secure FW size configuration */
@@ -31,28 +32,41 @@
#else
#define SEC_FW_SIZE 0
#endif
-
-/* Configuration of BL1, BL2, ENV Blocks on mmc */
-#define RES_BLOCK_SIZE (512)
-#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
-#define BL2_SIZE (512UL << 10UL) /* 512 KB */
-
+#define CONFIG_SERIAL2
+#define CONFIG_SPL_BUILD
+/*
#define BL1_OFFSET (RES_BLOCK_SIZE + SEC_FW_SIZE)
#define BL2_OFFSET (BL1_OFFSET + BL1_SIZE)
+*/
/* U-Boot copy size from boot Media to DRAM.*/
+/*
#define BL2_START_OFFSET (BL2_OFFSET/512)
#define BL2_SIZE_BLOC_COUNT (BL2_SIZE/512)
+*/
+
+#define CONFIG_CLK_1000_400_200
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR 0x42E00000
+#endif
-#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
-#define SPI_FLASH_UBOOT_POS (SEC_FW_SIZE + BL1_SIZE)
+/* #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 */
#elif defined(CONFIG_ARCH_EXYNOS4)
-#define COPY_BL2_SIZE 0x80000
-#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
+#define COPY_UBOOT_SIZE 0x80000
+#define UBOOT_START_OFFSET ((RESERVE_BLOCK_SIZE + BL1_SIZE + BL2_SIZE) /512)
+#define UBOOT_SIZE_BLOC_COUNT (COPY_UBOOT_SIZE /512)
+
+#define COPY_BL2_SIZE 0x4000
+#define BL2_START_OFFSET ((RESERVE_BLOCK_SIZE + BL1_SIZE)/512)
#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
#endif
DECLARE_GLOBAL_DATA_PTR;
+gd_t gdata __attribute__ ((section(".data")));
+
/* Index into irom ptr table */
enum index {
@@ -255,15 +269,21 @@ void copy_uboot_to_ram(void)
break;
#endif
case BOOT_MODE_SD:
+#if defined(CONFIG_EX4412)
+ offset = UBOOT_START_OFFSET;
+ size = UBOOT_SIZE_BLOC_COUNT;
+#else
offset = BL2_START_OFFSET;
size = BL2_SIZE_BLOC_COUNT;
+#endif
copy_bl2 = get_irom_func(MMC_INDEX);
break;
#ifdef CONFIG_SUPPORT_EMMC_BOOT
case BOOT_MODE_EMMC:
/* Set the FSYS1 clock divisor value for EMMC boot */
+ #ifndef CONFIG_EX4412
emmc_boot_clk_div_set();
-
+ #endif
copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
@@ -286,9 +306,31 @@ void copy_uboot_to_ram(void)
default:
break;
}
-
- if (copy_bl2)
+#ifdef CONFIG_TARGET_EX4412
+ if (copy_bl2) {
+ /*
+ * Here I use iram 0x020250000-0x020260000 (64k)
+ * as an buffer, and copy u-boot from sd card to
+ * this buffer, then copy it to dram started
+ * from 0x43e00000.
+ *
+ */
+ unsigned int i, count = 0;
+ unsigned char *buffer = (unsigned char *)0x02050000;
+ unsigned char *dst = (unsigned char *)CONFIG_TEXT_BASE;
+ unsigned int step = (0x10000 / 512);
+
+ for (count = 0; count < size; count += step) {
+ /* copy u-boot from sdcard to iram firstly. */
+ copy_bl2((u32)(offset + count), (u32)step, (u32)buffer);
+ for (i = 0; i < 0x10000; i++) {
+ *dst++ = buffer[i];
+ }
+ }
+ }
+#else
copy_bl2(offset, size, CONFIG_TEXT_BASE);
+#endif
}
void memzero(void *s, size_t n)
@@ -316,6 +358,7 @@ static void setup_global_data(gd_t *gdp)
gd->have_console = 1;
}
+#include <version.h>
void board_init_f(unsigned long bootflag)
{
__aligned(8) gd_t local_gd;
@@ -325,11 +368,17 @@ void board_init_f(unsigned long bootflag)
if (do_lowlevel_init())
power_exit_wakeup();
+#ifdef CONFIG_DEBUG_UART
+/* printascii("\r\nU-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " U_BOOT_TIME ")\r\n"); */
+#endif
copy_uboot_to_ram();
/* Jump to U-Boot image */
uboot = (void *)CONFIG_TEXT_BASE;
+ printascii("finish BL1 copying,Jump to U-Boot image\n\r");
+/* printhex8(uboot); */
+ printascii("\n\r");
(*uboot)();
/* Never returns Here */
}9.修改Makefile，执行CFGCHK u-boot.cfg时出错，屏蔽掉相关代码。
diff --git a/Makefile b/Makefile
index 9a8a7c4..299f548 100644
--- a/Makefile
+++ b/Makefile
@@ -1073,9 +1073,9 @@ cmd_lzma = lzma -c -z -k -9 $< > $@
cfg: u-boot.cfg
-quiet_cmd_cfgcheck = CFGCHK $2
-cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
- $(srctree)/scripts/config_whitelist.txt $(srctree)
+#quiet_cmd_cfgcheck = CFGCHK $2
+#cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
+# $(srctree)/scripts/config_whitelist.txt $(srctree)
quiet_cmd_ofcheck = OFCHK $2
cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \五、编译移植
1.编译
make distclean
make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- ex4412_defconfig
make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- -j4
编译报错
解决：make menuconfig打开配置
[*] Enable SPL │ │
│ │ SPL configuration options --->[*] Support GPIO in SPL 和 [*] Support serial
这里有些奇怪，虽然已经在config/ex4412_defconfig中配置以下内容，但不起作用
在make menuconfig配置后，重新编译，未报错误
另外调试时打开Device Drivers --->[*] Serial ---> [*] Enable an early debug UART for debugging (0x13820000) Base address of UART (0x13820000) Base address of UART for SPL (100000000) UART input clock
上述调试端口在调试时和ARM architecture --->ARM debug ---> [ ] Low-level debugging functions 同时打开时会冲突报错，因此不打开该项配置。
2.使用mkbl2生成bl2.bin
./mkbl2 spl/u-boot-spl.bin bl2.bin 14336
3.把BL1和BL2、uboot及all00_padding生成一个文件
cat E4412.S.BL1.SSCR.EVT1.1.bin bl2.bin all00_padding.bin u-boot.bin> u-boot-ex4412.bin
4、烧写，/dev/sdb为本人虚拟机识别到TF设备标识，以Ubuntu系统实际识别的TF卡设备标识为准。
dd if=/dev/zero of=/dev/sdb bs=512 seek=1 iflag=dsync oflag=dsync count=2048
dd iflag=dsync oflag=dsync if=u-boot-ex4412.bin of=/dev/sdb seek=1
以上编译、烧写过程，可优化整合到脚本里面实现，但由于本人TF卡有时识别异常，只能按部就班为稳妥。
六、成功运行
- 我的博客站点：https://www.cnblogs.com/fengconglin
- 我的csdn博客：https://blog.csdn.net/fengconglin
- 我的GitHub：https://github.com/WindThicket
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