ARM1176JZF-S/S3C6410处理器的操作…

Operating Modes

Eight operating modes are defined under ARM1176JZF-S architecture, they are:

Mode	Mode Type	Comments
User	User	User mode is the usual ARM program execution state, and is used for executing most application programs
FIQ	Privileged	Fast interrupt (FIQ) mode is used for handling fast interrupts
IRQ	Privileged	Interrupt (IRQ) mode is used for general-purpose interrupt handling
Supervisor	Privileged	Supervisor mode is a protected mode for the OS
Abort	Privileged	Abort mode is entered after a data abort or prefetch abort
System	Privileged	System mode is a privileged user mode for the OS
Undefined	Privileged	Undefined mode is entered when an undefined instruction exception occurs.
Secure Monitor	Privileged	Secure Monitor mode is a Secure mode for the TrustZone Secure Monitor code.

Modes other than User mode are collectively known as privileged modes. Privileged modes are used to service interrupts or exceptions, or to access protected resources.

User and System modes are named as normal modes, other modes are exception modes. Why they are called "exception" modes? Because these 6 modes are entered by some kinds of exception, for example IRQ. While system mode is not same, it can be switched into, but not triggered by any exception.

Registers (ARM state only)

ARM1176JZF-S processor has 40 registers totally:

• 33 general-purpose 32-bit registers
• seven 32-bit status registers.

These registers are not all accessible at the same time. The processor state and operating mode determine the registers that are available to the programmer. Here I focus on ARM state registers only.

The ARM state core register set contains 16 directly-accessible registers, R0-R15. Another register, the Current Program Status Register (CPSR), contains condition code flags, status bits, and current mode bits. Registers R0-R12 are general-purpose registers used to hold either data or address values. Registers R13, R14, R15, and the Saved Program Status Register(SPSR) have the following special functions:

Stack PointerRegister R13 is used as the Stack Pointer (SP). R13 is banked for the exception modes. This means that an exception handler can use a different stack to the one in use when the exception occurred.

Link RegisterRegister R14 is used as the subroutine Link Register (LR). Register R14 receives the return address when a Branch with Link (BL or BLX) instruction is executed. You can treat R14 as a general-purpose register at all other times.

Program CounterRegister R15 holds the PC, in ARM state this is word-aligned

Saved Program Status RegisterIn privileged modes, another register, the SPSR, is accessible. This contains the condition code flags, status bits, and current mode bits saved as a result of the exception that caused entry to the current mode.

In ARM state, 16 general registers and one or two status registers are accessible at any time. In privileged modes, mode-specific banked registers become available. The figure below shows the registers that are available in each mode.

'Banked Register' (marked by gray triangle) means that this register has a divided instance under the corresponding exception operating mode, that's a different register than the one in normal mode.

For example, the processor store some data to R13 in User mode; if the process switch from User mode to System mode and read the date of R13, same value will be got; but if the process switch from User mode to any other mode, when it read the data in R13, different value will be got, because that's different register in fact.