arm1176 MMU（一）

1、The MMU features are:
• standard ARMv6 MMU mapping sizes, domains, and access protection scheme
• mapping sizes are 4KB, 64KB, 1MB, and 16MB 映射大小
• the access permissions for 1MB sections and 16MB supersections are specified for the
entire section
• you can specify access permissions for 64KB large pages and 4KB small pages separately
for each quarter of the page, these quarters are called subpages
• 16 domains
• one 64-entry unified TLB and a lockdown region of eight entries
• you can mark entries as a global mapping, or associated with a specific application space
identifier to eliminate the requirement for TLB flushes on most context switches
• access permissions extended to enable Privileged read-only and Privileged or User
read-only modes to be simultaneously supported
• memory region attributes to mark pages shared by multiple processors
• hardware page table walks
• separate Secure and Non-secure entries and page tables
• Non-secure memory attribute

• possibility to restrict the eight lockdown entries to the Secure world

2、This controls if a program has no-access, read-only access, or read/write access
to the memory area.  内存区域可分为 不可访问，只读，读写

3、Enabling the MMU  开启MMU
To enable the MMU in one world you must:
1）. Program all relevant CP15 registers of the corresponding world.配置CP15寄存器
2）. Program first-level and second-level descriptor page tables as required.设置一级和二级页表
3）. Disable and invalidate the Instruction Cache for the corresponding world. You can then
re-enable the Instruction Cache when you enable the MMU. 关闭和使无效指令缓存，使能MMU可以重新开启
4）. Enable the MMU by setting bit 0 in the CP15 Control Register in the corresponding world.

设置CP15bit0，开启MMU

4、Disabling the  MMU关闭MMU
To disable the MMU in one world proceed as follows:
 1. Clear bit 2 to 0 in the CP15 Control Register c1 of the corresponding world, to disable theData Cache. You must disable the Data Cache in the corresponding world before, or at the
same time as, disabling the MMU.
Note
If the MMU is enabled, then disabled, and subsequently re-enabled in the same world, the
contents of the TLBs for this world are preserved. If these are now invalid, you must
invalidate the TLBs in the corresponding world before you re-enable the MMU, 
 2. Clear bit 0 to 0 in the CP15 Control Register c1 of the corresponding world.

5、Domains
 A domain is a collection of memory regions. In compliance with the ARM Architecture and the
TrustZone Security Extensions, the ARM1176JZ-S supports 16 Domains in the Secure world
and 16 Domains in the Non-secure world.支持16个域 

Domains provide support for multi-user operatingsystems. All regions of memory have an associated domain.
A domain is the primary access control mechanism for a region of memory and defines the
conditions when an access can proceed. The domain determines whether:
• access permissions are used to qualify the access  访问时检查权限Client类型
• access is unconditionally permitted to proceed   不检查访问权限Manager类型
• access is unconditionally aborted.   不可访问
 In the latter two cases, the access permission attributes are ignored.
Each page table entry and TLB entry contains a field that specifies the domain that the entry is in. Access to each domain is controlled by a 2-bit field in the Domain Access Control Register,CP15 c3.域的访问控制访问由 CP15 c3寄存器中的两位控制Each field enables very quick access to be achieved to an entire domain, so that wholememory areas can be efficiently swapped in and out of virtual memory. Two kinds of domain
access are supported:
Clients 用户模式，访问时须核对页面映射表项中的访问权限（AP）

Clients are users of domains in that they execute programs and access data. They
are guarded by the access permissions of the TLB entries for that domain.
A client is a domain user, and each access has to be checked against the access
permission settings for each memory block and the system protection bit, the S
bit, and the ROM protection bit, the R bit, in CP15 Control Register c1. 

Managers 管理模式，访问时不核对反问权限

Managers control the behavior of the domain, the current sections and pages in
the domain, and the domain access. They are not guarded by the access
permissions for TLB entries in that domain.
Because a manager controls the domain behavior, each access has only to be
checked to be a manager of the domain.
  One program can be a client of some domains, and a manager of some other domains, and have
no access to the remaining domains. This enables flexible memory protection for programs thataccess different memory resources.

For such OSs the encoding of the Read-Only or Read-Write and the User or Kernel access
permissions are orthogonal:
• APX selects the Read-Only or Read-Write permission
• AP[1] selects the User or Kernel access.

6、Cacheable Write-Through, Cacheable Write-Back, and Noncacheable区域的写缓冲，高速缓存
In addition to marking a region of Normal memory as being Shared or Non-Shared, a region of
memory marked as Normal can also be marked on a per-page basis in an MMU as being one of:
• Cacheable Write-Through
• Cacheable Write-Back
• Noncacheable.

7、MMU aborts MMU中止
Mechanisms that can cause the processor to take an exception because of a memory access are:
1、MMU fault The MMU detects a restriction and signals the processor.
2、Debug abort Monitor debug-mode debug is enabled and a breakpoint or a watchpoint
has been detected.
3、External abort The external memory system signals an illegal or faulting memory access.