1.在Makefile中添加(最好在smdk2410后面增加,保持相似的东西放到一起)
qt2410_config : unconfig
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) arm arm920t qt2410 armzone s3c24x0
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
2.在board/和nand_spl/board下建立目录armzone/qt2410,标准的做法是把nand搬移与后面的sdram中运行的代码分离成两部分,而后在Makefile中用cat file1 file2 > file的方式合到一起,当然file1的大小在nand部分就已经处理成了nand boot自动装入的大小----4KB.具体就看Makefile里的脚本吧.
3.在board/armzone/qt2410下将从board/sumsung/smdk2410复制过来的内容做相应的修改
删除flash相关的,因为是用nand boot,系统中没有使用nor flash.
把程序和文件中相关的名字都改成qt2410(原来是smdk2410).
4.修改include/configs/qt2410.h(先从smdk2410.h复制),注意要增加和删除一些内容,如flash,env,nand flash等.这里2009.06和2009.03的版本有一些变化,nand的驱动是在driver/mtd/nand/里面了,而且需要把该目录下的Makefile中的一个CONFIG_NAND_S3C2410定义在include/configs/qt2410.h中.否则编译的时候会错,而且nand的驱动也编不进去.
5.在nand_spl/board/armzone/qt2410编写程序,完成将u-boot搬移到sdram中的指定位置,并跳转到该位置运行的程序.注意,这里两部分的程序的TEXT_BASE是不一样的,nand搬移部分是0,而后面的那部分(真正的u-boot)的TEXT_BASE是在SDRAM中的某一位置的,因此要视SDRAM的安排而定,同时nand部分搬移的地址也要而这个地址一致,否则程序是运行不起来的(这个程序不是位置无关的).
因为不知道怎么上传文件,所以把我的patch文件帖到下面:
diff -uNr u-boot-2009.06/board/armzone/qt2410/config.mk u-boot-2009.06-qt2410/board/armzone/qt2410/config.mk
--- u-boot-2009.06/board/armzone/qt2410/config.mk 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/board/armzone/qt2410/config.mk 2009-06-23 11:05:51.511952000 +0800
@@ -0,0 +1,25 @@
+#
+# ARMZONE QT2410 board with S3C2410X (ARM920T) cpu
+#
+#
+
+#
+# QT2410 has 1 bank of 64 MB DRAM
+#
+# 3000'0000 to 3400'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# we load ourself to 33F8'0000
+#
+# download area is 3300'0000
+#
+
+ifeq ($(CONFIG_NAND_SPL),y)
+TEXT_BASE = 0x00000000
+else
+#TEXT_BASE = 0x31F80000
+TEXT_BASE = 0x33F80000
+endif
+
diff -uNr u-boot-2009.06/board/armzone/qt2410/lowlevel_init.S u-boot-2009.06-qt2410/board/armzone/qt2410/lowlevel_init.S
--- u-boot-2009.06/board/armzone/qt2410/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/board/armzone/qt2410/lowlevel_init.S 2009-06-23 09:12:41.228322000 +0800
@@ -0,0 +1,167 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
+ *
+ */
+
+#define BWSCON 0x48000000
+
+/* BWSCON */
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/* BANK0CON */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0
+#define B0_PMC 0x0 /* normal */
+
+/* BANK1CON */
+#define B1_Tacs 0x0 /* 0clk */
+#define B1_Tcos 0x0 /* 0clk */
+#define B1_Tacc 0x7 /* 14clk */
+#define B1_Tcoh 0x0 /* 0clk */
+#define B1_Tah 0x0 /* 0clk */
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0 /* 0clk */
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x0 /* 0clk */
+#define B3_Tacp 0x3 /* 6clk */
+#define B3_PMC 0x0 /* normal */
+
+#define B4_Tacs 0x0 /* 0clk */
+#define B4_Tcos 0x0 /* 0clk */
+#define B4_Tacc 0x7 /* 14clk */
+#define B4_Tcoh 0x0 /* 0clk */
+#define B4_Tah 0x0 /* 0clk */
+#define B4_Tacp 0x0
+#define B4_PMC 0x0 /* normal */
+
+#define B5_Tacs 0x0 /* 0clk */
+#define B5_Tcos 0x0 /* 0clk */
+#define B5_Tacc 0x7 /* 14clk */
+#define B5_Tcoh 0x0 /* 0clk */
+#define B5_Tah 0x0 /* 0clk */
+#define B5_Tacp 0x0
+#define B5_PMC 0x0 /* normal */
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1
+#define B6_SCAN 0x1 /* 9bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x1 /* 9bit */
+
+/* REFRESH parameter */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x0 /* 2clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x2 /* 3clk */
+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ ldr r0, =SMRDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add r2, r0, #13*4
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0x32
+ .word 0x30
+ .word 0x30
diff -uNr u-boot-2009.06/board/armzone/qt2410/Makefile u-boot-2009.06-qt2410/board/armzone/qt2410/Makefile
--- u-boot-2009.06/board/armzone/qt2410/Makefile 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/board/armzone/qt2410/Makefile 2009-06-23 10:02:01.143317000 +0800
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := qt2410.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -uNr u-boot-2009.06/board/armzone/qt2410/qt2410.c u-boot-2009.06-qt2410/board/armzone/qt2410/qt2410.c
--- u-boot-2009.06/board/armzone/qt2410/qt2410.c 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/board/armzone/qt2410/qt2410.c 2009-06-23 12:16:22.215958000 +0800
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2410.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV 0xC3
+#define M_PDIV 0x4
+#define M_SDIV 0x1
+#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
+#define M_MDIV 0xA1
+#define M_PDIV 0x3
+#define M_SDIV 0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV 0xA1
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV 0x48
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x2
+#endif
+
+static inline void delay (unsigned long loops)
+{
+ __asm__ volatile ("1:/n"
+ "subs %0, %1, #1/n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->LOCKTIME = 0xFFFFFF;
+
+ /* configure MPLL */
+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ delay (4000);
+
+ /* configure UPLL */
+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ delay (8000);
+
+ /* set up the I/O ports */
+ gpio->GPACON = 0x007FFFFF;
+ gpio->GPBCON = 0x00044555;
+ gpio->GPBUP = 0x000007FF;
+ gpio->GPCCON = 0xAAAAAAAA;
+ gpio->GPCUP = 0x0000FFFF;
+ gpio->GPDCON = 0xAAAAAAAA;
+ gpio->GPDUP = 0x0000FFFF;
+ gpio->GPECON = 0xAAAAAAAA;
+ gpio->GPEUP = 0x0000FFFF;
+ gpio->GPFCON = 0x000055AA;
+ gpio->GPFUP = 0x000000FF;
+ gpio->GPGCON = 0xFF95FFBA;
+ gpio->GPGUP = 0x0000FFFF;
+ gpio->GPHCON = 0x002AFAAA;
+ gpio->GPHUP = 0x000007FF;
+
+ /* arch number of SMDK2410-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_QT2410;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x30000100;
+
+ icache_enable();
+ dcache_enable();
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ printf("/n CPU: S3C2410");
+ printf("/n Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
+ get_FCLK() / 1000000, get_HCLK() / 1000000,
+ get_PCLK() / 1000000);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("/n Board: QT2410/n");
+ return 0;
+}
+#endif
diff -uNr u-boot-2009.06/board/armzone/qt2410/u-boot-nand.lds u-boot-2009.06-qt2410/board/armzone/qt2410/u-boot-nand.lds
--- u-boot-2009.06/board/armzone/qt2410/u-boot-nand.lds 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/board/armzone/qt2410/u-boot-nand.lds 2009-06-23 09:12:41.228322000 +0800
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ _end = .;
+}
diff -uNr u-boot-2009.06/drivers/mtd/nand/Makefile u-boot-2009.06-qt2410/drivers/mtd/nand/Makefile
--- u-boot-2009.06/drivers/mtd/nand/Makefile 2009-06-15 03:30:39.000000000 +0800
+++ u-boot-2009.06-qt2410/drivers/mtd/nand/Makefile 2009-06-23 12:18:30.699978968 +0800
@@ -41,7 +41,7 @@
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
-COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c
+COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
endif
diff -uNr u-boot-2009.06/include/configs/qt2410.h u-boot-2009.06-qt2410/include/configs/qt2410.h
--- u-boot-2009.06/include/configs/qt2410.h 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/include/configs/qt2410.h 2009-06-23 11:05:31.945944000 +0800
@@ -0,0 +1,189 @@
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
+#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
+#define CONFIG_QT2410 1 /* on a ARMZONE QT2410 Board */
+#ifdef CONFIG_QT2410
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#endif
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
+
+
+#define USE_920T_MMU 1
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ *
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
+#define CS8900_BASE 0x19000300
+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
+
+/************************************************************
+ * RTC
+ ************************************************************/
+#define CONFIG_RTC_S3C24X0 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 3
+/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
+/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 10.0.0.110
+#define CONFIG_SERVERIP 10.0.0.1
+/*#define CONFIG_BOOTFILE "elinos-lart" */
+/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "QT2410 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */
+
+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
+/* it to wrap 100 times (total 1562500) to get 1 sec. */
+#define CONFIG_SYS_HZ 1562500
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#if 0
+#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
+#if 0
+#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
+#endif
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#ifdef CONFIG_AMD_LV800
+#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
+#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
+#endif
+#ifdef CONFIG_AMD_LV400
+#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
+#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
+#endif
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+#endif
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (4*1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (256*1024-CONFIG_SYS_NAND_U_BOOT_OFFS)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x33f80000)
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_OFFSET 0x0040000
+
+/* NAND configuration */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_S3C2410
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x4e000000
+#endif
+
+#endif /* __CONFIG_H */
diff -uNr u-boot-2009.06/Makefile u-boot-2009.06-qt2410/Makefile
--- u-boot-2009.06/Makefile 2009-06-15 03:30:39.000000000 +0800
+++ u-boot-2009.06-qt2410/Makefile 2009-06-23 12:19:02.877953836 +0800
@@ -2871,6 +2871,11 @@
smdk2410_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0
+qt2410_config : unconfig
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @$(MKCONFIG) -a $(@:_config=) arm arm920t qt2410 armzone s3c24x0
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
SX1_stdout_serial_config /
SX1_config: unconfig
@mkdir -p $(obj)include
diff -uNr u-boot-2009.06/nand_spl/board/armzone/qt2410/config.mk u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/config.mk
--- u-boot-2009.06/nand_spl/board/armzone/qt2410/config.mk 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/config.mk 2009-06-07 22:29:48.000000000 +0800
@@ -0,0 +1,16 @@
+
+# TEXT_BASE for SPL:
+#
+# On S3C2410 platforms the SPL is located in SRAM at 0.
+#
+# TEXT_BASE = 0
+
+include $(TOPDIR)/board/$(BOARDDIR)/config.mk
+
+# PAD_TO used to generate a 4kByte binary needed for the combined image
+# -> PAD_TO = TEXT_BASE + 4096
+PAD_TO := $(shell expr $$[$(TEXT_BASE) + 4096])
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff -uNr u-boot-2009.06/nand_spl/board/armzone/qt2410/k9f1208u0c.h u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/k9f1208u0c.h
--- u-boot-2009.06/nand_spl/board/armzone/qt2410/k9f1208u0c.h 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/k9f1208u0c.h 2009-06-07 22:29:48.000000000 +0800
@@ -0,0 +1,27 @@
+#ifndef _K9F1208U0C_H_
+#define _K9F1208U0C_H_
+
+#define FLASH_PAGE_SIZE_POWER (9)
+#define FLASH_PAGE_SPARE_SIZE_POWER (4)
+#define FLASH_PAGE_NUMBER_POWER (5)
+#define FLASH_BLOCK_SIZE_POWER (FLASH_PAGE_SIZE_POWER+FLASH_PAGE_NUMBER_POWER)
+#define FLASH_BLOCK_NUMBER_POWER (12)
+#define FLASH_SIZE_POWER (FLASH_BLOCK_SIZE+FLASH_BLOCK_NUMBER_POWER)
+
+#define FLASH_PAGE_SIZE (1<<FLASH_PAGE_SIZE_POWER)//(512)
+#define FLASH_PAGE_SPARE_SIZE (1<<FLASH_PAGE_SPARE_SIZE_POWER)//(16)
+#define FLASH_PAGE_NUMBER (1<<FLASH_PAGE_NUMBER_POWER)//(32)
+#define FLASH_BLOCK_SIZE (1<<FLASH_BLOCK_SIZE_POWER)//(FLASH_PAGE_SIZE)*(FLASH_PAGE_NUMBER)
+#define FLASH_BLOCK_NUMBER (1<<FLASH_BLOCK_NUMBER_POWER)//(4096)
+#define FLASH_SIZE (1<<FLASH_SIZE_POWER)//(FLASH_BLOCK_SIZE)*(FLASH_BLOCK_NUMBER)
+
+extern void NF_Reset(void);
+extern void NF_Init(void);
+extern unsigned short int NF_CheckId(void);
+extern int NF_IsBadBlock(unsigned int block);
+extern int NF_MarkBadBlock(unsigned int block);
+extern int NF_ReadPage(unsigned int block,unsigned int page,unsigned char* buffer);
+extern int NF_EraseBlock(unsigned int block);
+extern int NF_WritePage(unsigned int block,unsigned int page,unsigned char *buffer);
+
+#endif
diff -uNr u-boot-2009.06/nand_spl/board/armzone/qt2410/lowlevel_init.S u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/lowlevel_init.S
--- u-boot-2009.06/nand_spl/board/armzone/qt2410/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/lowlevel_init.S 2009-06-23 11:56:44.183001000 +0800
@@ -0,0 +1,251 @@
+#if 1
+#include "s3c2410_cfg.h"
+
+#define BWSCON (0x48000000) //Bus width & wait status
+#define BANKCON0 (0x48000004) //Boot ROM control
+#define BANKCON1 (0x48000008) //BANK1 control
+#define BANKCON2 (0x4800000c) //BANK2 cControl
+#define BANKCON3 (0x48000010) //BANK3 control
+#define BANKCON4 (0x48000014) //BANK4 control
+#define BANKCON5 (0x48000018) //BANK5 control
+#define BANKCON6 (0x4800001c) //BANK6 control
+#define BANKCON7 (0x48000020) //BANK7 control
+#define REFRESH (0x48000024) //DRAM/SDRAM refresh
+#define BANKSIZE (0x48000028) //Flexible Bank Size
+#define MRSRB6 (0x4800002c) //Mode register set for SDRAM
+#define MRSRB7 (0x48000030) //Mode register set for SDRAM
+
+#define CLKCON (0x4c00000c) //Clock generator control
+
+.text
+.globl lowlevel_init
+
+
+lowlevel_init:
+ // BWSCON 汲沥
+ ldr r0, =BWSCON
+// ldr r1, =BWSCON_VALUE
+ ldr r1, =BWSCON_DEFAULT
+ str r1, [r0]
+
+ // MBC 0 汲沥
+ ldr r0, =BANKCON0
+// ldr r1, =MBC_CS0_VALUE
+ ldr r1, =B0_DEFAULT
+ str r1, [r0]
+ ldr r1, [r0] // must be read after it is written
+
+ // MBC 1 汲沥
+ ldr r0, =BANKCON1
+// ldr r1, =MBC_CS1_VALUE
+ ldr r1, =B1_DEFAULT
+ str r1, [r0]
+ ldr r1, [r0] // must be read after it is written
+
+ // MBC 2 汲沥
+ ldr r0, =BANKCON2
+// ldr r1, =MBC_CS2_VALUE
+ ldr r1, =B2_DEFAULT
+ str r1, [r0]
+ ldr r1, [r0] // must be read after it is written
+
+ // MBC 3 汲沥
+ ldr r0, =BANKCON3
+// ldr r1, =MBC_CS3_VALUE
+ ldr r1, =B3_DEFAULT
+ str r1, [r0]
+ ldr r1, [r0] // must be read after it is written
+
+ // MBC 4 汲沥
+ ldr r0, =BANKCON4
+// ldr r1, =MBC_CS4_VALUE
+ ldr r1, =B4_DEFAULT
+ str r1, [r0]
+ ldr r1, [r0] // must be read after it is written
+
+ // MBC 5 汲沥
+ ldr r0, =BANKCON5
+// ldr r1, =MBC_CS5_VALUE
+ ldr r1, =B5_DEFAULT
+ str r1, [r0]
+ ldr r1, [r0] // must be read after it is written
+
+ // MBC 6 汲沥
+ ldr r0, =BANKCON6
+// ldr r1, =MBC_CS6_VALUE
+ ldr r1, =B6_DEFAULT
+ str r1, [r0]
+ ldr r1, [r0] // must be read after it is written
+
+ // MBC 7 汲沥
+ ldr r0, =BANKCON7
+// ldr r1, =MBC_CS7_VALUE
+ ldr r1, =B7_DEFAULT
+ str r1, [r0]
+ ldr r1, [r0] // must be read after it is written
+
+ // SDRAM Refresh 汲沥 =================================
+ ldr r0, =REFRESH
+// ldr r1, =MRC_REFRESH_VALUE
+ ldr r1, =SDRREF_DEFAULT
+ str r1, [r0]
+
+ // SDRAM Bank Size 汲沥 =================================
+ ldr r0, =BANKSIZE
+ ldr r1, =0xB1
+ str r1, [r0]
+
+ // SDRAM Mode Set [nCS6] 汲沥 ============================
+ ldr r0, =MRSRB6
+ ldr r1, =0x30
+ str r1, [r0]
+
+ // SDRAM Mode Set [nCS7] 汲沥 ============================
+ ldr r0, =MRSRB7
+ ldr r1, =0x30
+ str r1, [r0]
+
+ // CKEN 汲沥
+ ldr r0, =CLKCON
+ ldr r1, =CKEN_VALUE
+ str r1, [r0]
+
+
+ mov r1, #254 @ Wait until SDRAM self refresh is released
+10:
+ subs r1, r1, #1
+ bne 10b
+
+ mov pc, lr
+#else
+//#include <config.h>
+//#include <version.h>
+
+
+#define BWSCON 0x48000000
+
+/* BWSCON */
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B0_BWSCON (0x00<<0x00) // DUMMY
+//#define B1_BWSCON (DW32)
+#define B1_BWSCON (DW16 + WAIT) // CS8900
+#define B2_BWSCON (DW16) // DUMMY
+//#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B3_BWSCON (DW16) // AM29LV320D
+#define B4_BWSCON (DW8 + WAIT) // TW2880
+#define B5_BWSCON (DW16) // DUMMY
+#define B6_BWSCON (DW32) // SDRAM
+#define B7_BWSCON (DW32) // DUMMY
+
+/* BANK0CON */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0
+#define B0_PMC 0x0 /* normal */
+
+/* BANK1CON */
+#define B1_Tacs 0x01 //0x0 /* 0clk */
+#define B1_Tcos 0x02 //0x0 /* 0clk */
+#define B1_Tacc 0x7 /* 14clk */
+#define B1_Tcoh 0x0 /* 0clk */
+#define B1_Tah 0x0 /* 0clk */
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0 /* 0clk */
+#define B3_Tcos 0x00 //0x3 /* 4clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x00 //0x1 /* 1clk */
+#define B3_Tah 0x0 /* 0clk */
+#define B3_Tacp 0x00 //0x3 /* 6clk */
+#define B3_PMC 0x0 /* normal */
+
+#define B4_Tacs 0x0 /* 0clk */
+#define B4_Tcos 0x03 //0x0 /* 0clk */
+#define B4_Tacc 0x7 /* 14clk */
+#define B4_Tcoh 0x0 /* 0clk */
+#define B4_Tah 0x0 /* 0clk */
+#define B4_Tacp 0x0
+#define B4_PMC 0x0 /* normal */
+
+#define B5_Tacs 0x0 /* 0clk */
+#define B5_Tcos 0x0 /* 0clk */
+#define B5_Tacc 0x7 /* 14clk */
+#define B5_Tcoh 0x0 /* 0clk */
+#define B5_Tah 0x0 /* 0clk */
+#define B5_Tacp 0x0
+#define B5_PMC 0x0 /* normal */
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1
+#define B6_SCAN 0x1 /* 9bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x1 /* 9bit */
+
+/* REFRESH parameter */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x0 /* 2clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x2 /* 3clk */
+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+//_TEXT_BASE:
+// .word TEXT_BASE
+// .word 0x30F01000 /* hearing added, yes used */
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ ldr r0, =SMRDATA
+// ldr r1, _TEXT_BASE
+// sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add r2, r0, #13*4
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* everything is fine now */
+// mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+ .word (B0_BWSCON+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0xB1
+ .word 0x30
+ .word 0x30
+#endif
diff -uNr u-boot-2009.06/nand_spl/board/armzone/qt2410/Makefile u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/Makefile
--- u-boot-2009.06/nand_spl/board/armzone/qt2410/Makefile 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/Makefile 2009-06-23 11:11:32.907633000 +0800
@@ -0,0 +1,85 @@
+
+CONFIG_NAND_SPL = y
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+AFLAGS += -I$(TOPDIR)/nand_spl/board/$(BOARDDIR)
+CFLAGS += -I$(TOPDIR)/nand_spl/board/$(BOARDDIR)
+
+SOBJS = start.o lowlevel_init.o
+COBJS = nand_boot.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj := $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) /
+ -Map $(nandobj)u-boot-spl.map /
+ -o $(nandobj)u-boot-spl
+# cd $(LNDIR) && $(OBJDUMP) -D $(nandobj)u-boot-spl > $(nandobj)u-boot-spl-dump.txt
+
+# create symbolic links for common files
+
+# from cpu directory
+#$(obj)start.S:
+# @rm -f $@
+# @ln -s $(TOPDIR)/cpu/arm1176/start.S $@
+
+# from SoC directory
+#$(obj)cpu_init.S:
+# @rm -f $@
+# @ln -s $(TOPDIR)/cpu/arm1176/s3c64xx/cpu_init.S $@
+
+# from board directory
+#$(obj)lowlevel_init.S:
+# @rm -f $@
+# @ln -s $(TOPDIR)/board/samsung/smdk6400/lowlevel_init.S $@
+
+# from nand_spl directory
+#$(obj)nand_boot.c:
+# @rm -f $@
+# @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@
+
+# from drivers/mtd/nand directory
+#$(obj)nand_ecc.c:
+# @rm -f $@
+# @ln -s $(TOPDIR)/drivers/mtd/nand/nand_ecc.c $@
+
+#$(obj)s3c64xx.c:
+# @rm -f $@
+# @ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -uNr u-boot-2009.06/nand_spl/board/armzone/qt2410/nand_boot.c u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/nand_boot.c
--- u-boot-2009.06/nand_spl/board/armzone/qt2410/nand_boot.c 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/nand_boot.c 2009-06-23 12:02:20.858950000 +0800
@@ -0,0 +1,252 @@
+
+/*
+File: Nand_boot.c
+Description: This is a file created from k9f1208u0c nand flash driver
+Platform: ARM s3c2410A
+Author: Hearing.Liu
+*/
+#include <common.h>
+#include <s3c2410.h>
+#include "k9f1208u0c.h"
+
+// NAND flash
+#define rNFCONF (*(volatile unsigned *)0x4e000000) //NAND Flash configuration
+#define rNFCMD (*(volatile unsigned char *)0x4e000004) //NADD Flash command
+#define rNFADDR (*(volatile unsigned char *)0x4e000008) //NAND Flash address
+#define rNFDATA (*(volatile unsigned char *)0x4e00000c) //NAND Flash data
+#define rNFSTAT (*(volatile unsigned *)0x4e000010) //NAND Flash operation status
+#define rNFECC (*(volatile unsigned *)0x4e000014) //NAND Flash ECC
+#define rNFECC0 (*(volatile unsigned char *)0x4e000014)
+#define rNFECC1 (*(volatile unsigned char *)0x4e000015)
+#define rNFECC2 (*(volatile unsigned char *)0x4e000016)
+
+#define NF_CMD(cmd) {rNFCMD=cmd;}
+#define NF_ADDR(addr) {rNFADDR=addr;}
+#define NF_nFCE_L() {rNFCONF&=~(1<<11);}
+#define NF_nFCE_H() {rNFCONF|=(1<<11);}
+#define NF_RSTECC() {rNFCONF|=(1<<12);}
+#define NF_RDDATA() (rNFDATA)
+#define NF_WRDATA(data) {rNFDATA=data;}
+#define NF_WAITRB() {while(!(rNFSTAT&(1<<0)));}
+
+#define BAD_CHECK (0)
+#define ECC_CHECK (0)
+#define WRITEVERIFY (0) //verifing is enable at writing.
+
+#if 1
+// HCLK=100Mhz
+#define TACLS 0 // 1clk(0ns)
+#define TWRPH0 3 // clk(25ns)
+#define TWRPH1 0 // clk(10ns) //TACLS+TWRPH0+TWRPH1>=50ns
+#else
+// HCLK=50Mhz
+#define TACLS 0 // 1clk(0ns)
+#define TWRPH0 1 // clk(25ns)
+#define TWRPH1 0 // clk(10ns)
+#endif
+
+//static unsigned char seBuf[FLASH_PAGE_SPARE_SIZE]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
+//static unsigned char page_buf[FLASH_PAGE_SIZE+FLASH_PAGE_SPARE_SIZE];
+
+void NF_Reset(void)
+{
+ int i;
+ NF_nFCE_L();
+ NF_CMD(0xFF); //reset command
+ for(i=0;i<10;i++); //tWB = 100ns. //??????
+ NF_WAITRB(); //wait 200~500us;
+ NF_nFCE_H();
+}
+
+void NF_Init(void)
+{
+ rNFCONF=(1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0);
+ // 1 1 1 1, 1 xxx, r xxx, r xxx
+ // En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1
+ NF_Reset();
+}
+
+unsigned short int NF_CheckId(void)
+{
+ int i;
+ unsigned short int id;
+ NF_nFCE_L();
+ NF_CMD(0x90);
+ NF_ADDR(0x0);
+ for(i=0;i<10;i++); //wait tWB(100ns)?????
+ id=NF_RDDATA()<<8; // Maker code(K9S1208V:0xec)
+ id|=NF_RDDATA(); // Devide code(K9S1208V:0x76)
+ NF_nFCE_H();
+ return id;
+}
+
+int NF_IsBadBlock(unsigned int block)
+{
+ int i;
+ unsigned int blockPage;
+ unsigned char data;
+ blockPage=(block<<FLASH_PAGE_NUMBER_POWER); // For 2'nd cycle I/O[7:5]
+ NF_nFCE_L();
+ NF_CMD(0x50); // Spare array read command
+ NF_ADDR(517&0xf); // Read the mark of bad block in spare array(M addr=5)
+ NF_ADDR(blockPage&0xff); // The mark of bad block is in 0 page
+ NF_ADDR((blockPage>>8)&0xff); // For block number A[24:17]
+ NF_ADDR((blockPage>>16)&0xff); // For block number A[25]
+ for(i=0;i<10;i++); // wait tWB(100ns) //?????
+ NF_WAITRB(); // Wait tR(max 12us)
+ data=NF_RDDATA();
+ NF_nFCE_H();
+ if(data!=0xff)
+ {
+ //Printf("[block %d has been marked as a bad block(%x)]/n",block,data);
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+int NF_ReadPage(unsigned int block,unsigned int page,unsigned char* buffer)
+{
+ int i;
+ unsigned int blockPage;
+ unsigned char ecc0,ecc1,ecc2;
+ unsigned char* bufPt=buffer;
+ unsigned char se[FLASH_PAGE_SPARE_SIZE];
+ page=page&(FLASH_PAGE_NUMBER-1);//page=page&0x1f;
+ blockPage=(block<<FLASH_PAGE_NUMBER_POWER)+page;//blockPage=(block<<5)+page;//blockPage=(block*FLASH_PAGE_NUMBER)+page;
+ NF_RSTECC(); // Initialize ECC
+ NF_nFCE_L();
+ NF_CMD(0x00); // Read command
+ NF_ADDR(0); // Column = 0
+ NF_ADDR(blockPage&0xff); //
+ NF_ADDR((blockPage>>8)&0xff); // Block & Page num.
+ NF_ADDR((blockPage>>16)&0xff); //
+ for(i=0;i<10;i++); //wait tWB(100ns)/??????
+ NF_WAITRB(); // Wait tR(max 12us)
+ for(i=0;i<FLASH_PAGE_SIZE;i++)
+ {
+ *bufPt++=NF_RDDATA(); // Read one page
+ }
+ ecc0=rNFECC0;
+ ecc1=rNFECC1;
+ ecc2=rNFECC2;
+ for(i=0;i<FLASH_PAGE_SPARE_SIZE;i++)
+ {
+ se[i]=NF_RDDATA(); // Read spare array
+ }
+ //__RdPage528(pPage);
+ NF_nFCE_H();
+ if(ecc0==se[0] && ecc1==se[1] && ecc2==se[2])
+ {
+ //Printf("[ECC OK:%x,%x,%x]/r/n",se[0],se[1],se[2]);
+ return 1;
+ }
+ else
+ {
+ //Printf("[ECC ERROR(RD):read blockPage 0x%x:%x,%x,%x, reg:%x,%x,%x]/r/n",
+ //blockPage,se[0],se[1],se[2],ecc0,ecc1,ecc2);
+ return 0;
+ }
+}
+
+static int nand_load(unsigned int offs,unsigned int uboot_size, uchar *dst)
+{
+ unsigned int block, lastblock;
+ unsigned int page;
+ /*
+ * offs has to be aligned to a page address!
+ */
+ block = offs / FLASH_BLOCK_SIZE;
+ lastblock = (offs + uboot_size - 1) / FLASH_BLOCK_SIZE;
+ page = (offs % FLASH_BLOCK_SIZE) / FLASH_PAGE_SIZE;
+
+ while (block <= lastblock) {
+ if (!NF_IsBadBlock(block)) {
+ /*
+ * Skip bad blocks
+ */
+ while (page < FLASH_PAGE_NUMBER) {
+ NF_ReadPage(block, page,dst);
+ dst += FLASH_PAGE_SIZE;
+ page++;
+ }
+ page = 0;
+ } else {
+ lastblock++;
+ }
+ block++;
+ }
+ return 0;
+}
+#if 0
+void b_init (void)
+{
+ int x,y;
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ /* set up the I/O ports */
+ gpio->GPACON = 0x007FFFFF;
+
+ gpio->GPBCON = (gpio->GPBCON&0xFFFC03FF)|0x00015400;
+// gpio->GPBUP = 0x000007FF;
+
+ do
+ {
+ gpio->GPBDAT = (gpio->GPBDAT&0x7FF)&(~0x1e0);
+ y=10;
+ while(y>0)
+ {
+ x=0x0000ffff;
+ while(x>0)
+ {
+ x--;
+ }
+ y--;
+ }
+ gpio->GPBDAT = (gpio->GPBDAT&0x7FF)|(0x1e0);
+ y=10;
+ while(y>0)
+ {
+ x=0x0000ffff;
+ while(x>0)
+ {
+ x--;
+ }
+ y--;
+ }
+ }
+ while(0);
+}
+#endif
+void relocate_stage2(void)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+ NF_Init();
+ //b_init();
+ /*
+ * Load U-Boot image from NAND into RAM
+ */
+ nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS,CONFIG_SYS_NAND_U_BOOT_SIZE,(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ /*
+ * Jump to U-Boot image
+ */
+ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ (*uboot)();
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff -uNr u-boot-2009.06/nand_spl/board/armzone/qt2410/s3c2410_cfg.h u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/s3c2410_cfg.h
--- u-boot-2009.06/nand_spl/board/armzone/qt2410/s3c2410_cfg.h 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/s3c2410_cfg.h 2009-06-07 22:29:48.000000000 +0800
@@ -0,0 +1,152 @@
+#ifndef _S3C2410_CFG_H_
+#define _S3C2410_CFG_H_
+
+/* BWSCON */
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#if 0
+#define B0_BWSCON (0x00<<0x00) // DUMMY
+//#define B1_BWSCON (DW32)
+#define B1_BWSCON (DW16 + WAIT) // CS8900
+#define B2_BWSCON (DW16) // DUMMY
+#define B3_BWSCON (DW16 + WAIT + UBLB) // CS8900
+//#define B3_BWSCON (DW16) // AM29LV320D
+#define B4_BWSCON (DW8 + WAIT) // TW2880
+#define B4_BWSCON_DW16 (DW16 + WAIT) // TW2880
+#define B5_BWSCON (DW16) // DUMMY
+#define B6_BWSCON (DW32) // SDRAM
+#define B7_BWSCON (DW32) // DUMMY
+#else
+#define B0_BWSCON (0)
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+#endif
+
+
+
+#define BWSCON_DEFAULT (B0_BWSCON+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+#define BWSCON_B4DW8 BWSCON_DEFAULT
+#define BWSCON_B4DW16 (B0_BWSCON+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON_DW16<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+
+/* BANK0CON */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0
+#define B0_PMC 0x0 /* normal */
+
+#define B0_DEFAULT ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+
+/* BANK1CON */
+#define B1_Tacs 0x01 //0x0 /* 0clk */
+#define B1_Tcos 0x02 //0x0 /* 0clk */
+#define B1_Tacc 0x7 /* 14clk */
+#define B1_Tcoh 0x0 /* 0clk */
+#define B1_Tah 0x0 /* 0clk */
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B1_DEFAULT ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B2_DEFAULT ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+
+#define B3_Tacs 0x0 /* 0clk */
+#define B3_Tcos 0x00 //0x3 /* 4clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x00 //0x1 /* 1clk */
+#define B3_Tah 0x0 /* 0clk */
+#define B3_Tacp 0x00 //0x3 /* 6clk */
+#define B3_PMC 0x0 /* normal */
+
+#define B3_DEFAULT ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+
+#define B4_Tacs 0x0 /* 0clk */
+#define B4_Tcos 0x03 //0x0 /* 0clk */
+#define B4_Tacc 0x7 /* 14clk */
+#define B4_Tcoh 0x0 /* 0clk */
+#define B4_Tah 0x0 /* 0clk */
+#define B4_Tacp 0x0
+#define B4_PMC 0x0 /* normal */
+
+#define B4_DEFAULT ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+
+#define B5_Tacs 0x0 /* 0clk */
+#define B5_Tcos 0x0 /* 0clk */
+#define B5_Tacc 0x7 /* 14clk */
+#define B5_Tcoh 0x0 /* 0clk */
+#define B5_Tah 0x0 /* 0clk */
+#define B5_Tacp 0x0
+#define B5_PMC 0x0 /* normal */
+
+#define B5_DEFAULT ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1
+#define B6_SCAN 0x1 /* 9bit */
+
+#define B6_DEFAULT ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x1 /* 9bit */
+
+#define B7_DEFAULT ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+
+/* SDRAM REFRESH parameter */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x0 /* 2clk */
+#define Trc 0x3 /* 7clk */
+//#define Tchr 0x2 /* 3clk */
+//#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+#define REFCNT 0x1D3 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+
+//#define SDRREF_DEFAULT ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+#define SDRREF_DEFAULT ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+REFCNT)
+
+/* CLK configure */
+#define CKEN_SM_BIT (0 <<0 ) // SPECIAL Mode
+#define CKEN_IDLEBIT (0 <<2 ) // IDLE Mode
+#define CKEN_POWEROFF (0 <<3 ) // POWER Off Mode
+#define CKEN_NFC (1 <<4 ) // NAND Flash Controller
+#define CKEN_LCDC (1 <<5 ) // HWUART Clock Enable
+#define CKEN_USBHOST (1 <<6 ) // USBHOST Clock Enable
+#define CKEN_USBDEV (0 <<7 ) // USBDEVICE Clock Enable
+#define CKEN_PWMTIMER (1 <<8 ) // PWMTIMER Clock Enable
+#define CKEN_SDI (0 <<9 ) // SDI Clock Enable
+#define CKEN_UART0 (1 <<10 ) // UART0 Clock Enable
+#define CKEN_UART1 (1 <<11) // UART1 Clock Enable
+#define CKEN_UART2 (1 <<12) // UART2 Clock Enable
+#define CKEN_GPIO (1 <<13) // GPIO Clock Enable
+#define CKEN_RTC (1 <<14) // RTC Clock Enable
+#define CKEN_ADC (0 <<15) // ADC/Touch Screen Clock Enable
+#define CKEN_IIC (1 <<16) // I2C Clock Enable
+#define CKEN_IIS (0 <<17) // I2S Clock Enable
+#define CKEN_SPI (0 <<18) // SPI Clock Enable
+
+#define CKEN_VALUE ( CKEN_SM_BIT | CKEN_IDLEBIT | CKEN_POWEROFF | CKEN_NFC /
+ | CKEN_LCDC | CKEN_USBHOST | CKEN_USBDEV | CKEN_PWMTIMER /
+ | CKEN_SDI | CKEN_UART0 | CKEN_UART1 | CKEN_UART2 /
+ | CKEN_GPIO | CKEN_RTC | CKEN_ADC | CKEN_IIC /
+ | CKEN_IIS | CKEN_SPI )
+
+#endif
diff -uNr u-boot-2009.06/nand_spl/board/armzone/qt2410/start.S u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/start.S
--- u-boot-2009.06/nand_spl/board/armzone/qt2410/start.S 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/start.S 2009-06-23 12:00:17.972980000 +0800
@@ -0,0 +1,215 @@
+/*Stack*/
+#define IRQ_STACK_SIZE (3*8*4)
+
+#define BOOT_STACK 0x33f40000
+/*Clock & Lock Time*/
+#define S3C2410_REG_LOCKTIME 0x4C000000
+#define U_LTIME ( 0xFFF << 12 )
+#define M_UTIME ( 0xFFF << 0 )
+
+#define LOCKTIME_VALUE ( U_LTIME | M_UTIME )
+
+#define S3C2410_REG_CCCR 0x4C000004
+
+//----------------------------------------------
+// Core Clock (MPLL)
+//#define S3C2410_REG_CCCR 0x4C000004
+//----------------------------------------------
+#define MPLL_MDIV_266M (0x7d << 12)
+#define MPLL_MDIV_202M (0xa1 << 12)
+#define MPLL_MDIV_192M (0x58 << 12)
+#define MPLL_MDIV_180M (0x52 << 12)
+#define MPLL_MDIV_147M (0x5a << 12)
+#define MPLL_MDIV_101M (0x7f << 12)
+
+#define MPLL_PDIV_266M (0x1 << 4)
+#define MPLL_PDIV_202M (0x3 << 4)
+#define MPLL_PDIV_192M (0x1 << 4)
+#define MPLL_PDIV_180M (0x1 << 4)
+#define MPLL_PDIV_147M (0x2 << 4)
+#define MPLL_PDIV_101M (0x2 << 4)
+
+#define MPLL_SDIV_266M (0x1 << 0)
+#define MPLL_SDIV_202M (0x1 << 0)
+#define MPLL_SDIV_192M (0x1 << 0)
+#define MPLL_SDIV_180M (0x1 << 0)
+#define MPLL_SDIV_147M (0x1 << 0)
+#define MPLL_SDIV_101M (0x2 << 0)
+
+#define S3C2410_CPU_266M ( MPLL_MDIV_266M | MPLL_PDIV_266M | MPLL_SDIV_266M )
+#define S3C2410_CPU_202M ( MPLL_MDIV_202M | MPLL_PDIV_202M | MPLL_SDIV_202M )
+#define S3C2410_CPU_192M ( MPLL_MDIV_192M | MPLL_PDIV_192M | MPLL_SDIV_192M )
+#define S3C2410_CPU_180M ( MPLL_MDIV_180M | MPLL_PDIV_180M | MPLL_SDIV_180M )
+#define S3C2410_CPU_147M ( MPLL_MDIV_147M | MPLL_PDIV_147M | MPLL_SDIV_147M )
+#define S3C2410_CPU_101M ( MPLL_MDIV_101M | MPLL_PDIV_101M | MPLL_SDIV_101M )
+
+#define CPU_SPEED S3C2410_CPU_202M
+
+.text
+
+.globl _start
+
+_start: b reset
+ b undefined_instruction
+ b software_interrupt
+ b prefetch_abort
+ b data_abort
+ b not_used
+ b IsrIRQ
+ b FIQ
+
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+ /* turn off the watchdog */
+#define pWTCON_START 0x53000000
+#define INTMSK_START 0x4A000008 /* Interupt-Controller base addresses */
+#define INTSUBMSK_START 0x4A00001C
+#define CLKDIVN_START 0x4C000014 /* clock divisor register */
+
+ ldr r0, =pWTCON_START
+ mov r1, #0x0
+ str r1, [r0]
+ /*
+ * mask all IRQs by setting all bits in the INTMR - default
+ */
+ mov r1, #0xffffffff
+ ldr r0, =INTMSK_START
+ str r1, [r0]
+
+ ldr r1, =0x3ff
+ ldr r0, =INTSUBMSK_START
+ str r1, [r0]
+ /* FCLK:HCLK:PCLK = 1:2:4 */
+ /* default FCLK is 120 MHz ! */
+ ldr r0, =CLKDIVN_START
+ mov r1, #3
+ str r1, [r0]
+
+ bl cpu_init_crit
+
+ //-------------------------------------------
+ // 32-bit address mode
+ // 2004斥04岿01老 眠啊
+ //-------------------------------------------
+ mov r0, #0x30
+ mcr p15, 0, r0, c1, c0
+
+ //-------------------------------------------
+ // Set IRQ Stack.
+ //-------------------------------------------
+ ldr r1, =BOOT_STACK
+ sub sp, r1, #0x04
+
+ //-------------------------------------------
+ // Set Supervisor stack.
+ //-------------------------------------------
+ sub r1, r1, #IRQ_STACK_SIZE
+ mov sp,r1
+ nop
+ nop
+ nop
+
+ //-------------------------------------------
+ // To reduce PLL lock time, adjust the LOCKTIME register.
+ //-------------------------------------------
+ ldr r0, =S3C2410_REG_LOCKTIME
+ ldr r1, =LOCKTIME_VALUE
+ str r1, [r0]
+
+#if 1
+ //-------------------------------------------
+ // Configure MPLL ( Fin=12MHz, Fout=202MHz )
+ //-------------------------------------------
+ ldr r0, =S3C2410_REG_CCCR
+ ldr r1, =CPU_SPEED
+ str r1, [r0]
+
+ //-------------------------------------------
+ // Some delay between MPLL and UPLL
+ //-------------------------------------------
+ mov r0,#4000
+1:
+ subs r0,r0,#1
+ bne 1b
+
+#endif
+ //-------------------------------------------
+ // Copy bootloader to SDRAM.
+ //-------------------------------------------
+ bl relocate_stage2
+ nop
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+cpu_init_crit:
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
+ mcr p15, 0, r0, c1, c0, 0
+
+ /*
+ * before relocating, we have to setup RAM timing
+ * because memory timing is board-dependend, you will
+ * find a lowlevel_init.S in your board directory.
+ */
+ mov ip, lr
+#if defined(CONFIG_AT91RM9200EK)
+
+#else
+ bl lowlevel_init
+#endif
+ mov lr, ip
+ mov pc, lr
+
+//------------------------------------------------------------------------------------------------
+//
+// Intterupt process except Reset
+//------------------------------------------------------------------------------------------------
+data_abort:
+ ldr r5, ='D'
+ b data_abort
+undefined_instruction:
+ ldr r5, ='I'
+ b undefined_instruction
+software_interrupt:
+ ldr r5, ='S'
+ b software_interrupt
+prefetch_abort:
+ ldr r5, ='P'
+ b prefetch_abort
+not_used:
+ ldr r5, ='U'
+ b not_used
+IsrIRQ:
+ ldr r5, ='R'
+ b IsrIRQ
+FIQ:
+ ldr r5, ='F'
+ b FIQ
+//------------------------------------------------------------------------
diff -uNr u-boot-2009.06/nand_spl/board/armzone/qt2410/u-boot.lds u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/u-boot.lds
--- u-boot-2009.06/nand_spl/board/armzone/qt2410/u-boot.lds 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-2009.06-qt2410/nand_spl/board/armzone/qt2410/u-boot.lds 2009-06-23 11:11:53.896844000 +0800
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) . = ALIGN(4); }
+ _end = .;
+}
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