关于FIFO之半满信号

这两个星期一直在寻找关于半满信号的定义,今天总算找到一份美国专利,也不知道是什么时候的事了:

RAM based FIFO memory half-full detection apparatus and method
Document Type and Number: United States Patent 5490257
Link to this Page: httpwww.freepatentsonline.com5490257.html
Abstract: A method for detecting a half-full condition of a first-in, first-out memory array. The method of the

invention includes the steps of a) moving a write pointer through the array to write data to alternating rows of

the memory array; b) moving a read pointer through the array to read data from the alternating rows of the memory

array in first-in, first-out order; and c) providing a half-full indication when the read pointer and the write

pointer point to adjacent rows in the memory array. This method eliminates the need to route lines across the array

to detect a half-full condition, thereby reducing die and power requirements and offering an increase in speed.

大致意思是分别移出读地址和写地址来做判断,

对于同步的FIFO,只需判断非空满判断位的那一位,如12bit的信号,12位为空满判断用的,那么11位,可以用做半满判决.

而对于在异步的FIFO中,应该可以根据读写地址来判断半满信号,verilog程序就比较简单了,采用assign语句吧,免得和读时钟有联系