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本文以U-boot 2018.09源码 mips mt7621进行举例说明。
此预期的理论初始化流程适用于全U-boot和SPL(Secondary Program Loader)
这里解释下SPL,SPL是一种U-Boot功能。它将原始u-boot镜像分为两个独立的部分。第一部分用于初始化DRAM(动态随机存取存储器)和其他必要的外围设备,然后将第二部分加载到内存中,然后运行它。第二部分包含u-boot所有剩余的功能。第二部分称为"辅助程序”,第一部分称为"辅助程序加载器"。
所以uboot的启动是分为两级加载的。
目前,SPL部分大多使用单独的代码路径,但函数名和函数的功能都是相同的。某些板级或架构可能与此不符。至少大多数ARM框架的板级使用CONFIG_SPL_FRAMEWORK这个宏来控制这一点。
uboot的目录层次结构:
Directory Hierarchy:
====================
/arch Architecture specific files
/arc Files generic to ARC architecture
/arm Files generic to ARM architecture
/m68k Files generic to m68k architecture
/microblaze Files generic to microblaze architecture
/mips Files generic to MIPS architecture
/nds32 Files generic to NDS32 architecture
/nios2 Files generic to Altera NIOS2 architecture
/openrisc Files generic to OpenRISC architecture
/powerpc Files generic to PowerPC architecture
/riscv Files generic to RISC-V architecture
/sandbox Files generic to HW-independent "sandbox"
/sh Files generic to SH architecture
/x86 Files generic to x86 architecture
/api Machine/arch independent API for external apps
/board Board dependent files
/cmd U-Boot commands functions
/common Misc architecture independent functions
/configs Board default configuration files
/disk Code for disk drive partition handling
/doc Documentation (don't expect too much)
/drivers Commonly used device drivers
/dts Contains Makefile for building internal U-Boot fdt.
/examples Example code for standalone applications, etc.
/fs Filesystem code (cramfs, ext2, jffs2, etc.)
/include Header Files
/lib Library routines generic to all architectures
/Licenses Various license files
/net Networking code
/post Power On Self Test
/scripts Various build scripts and Makefiles
/test Various unit test files
/tools Tools to build S-Record or U-Boot images, etc.
常用比较重要的几个目录:
DTS配置文件:/arch/your_architecture/dts/xxxx.dts
板级实现/board/xxx
板子默认配置/configs/xxx_defconfig 各种功能宏
板级常规配置/include/configs/xxx.h
uboot固件编译的链接配置文件为u-boot.lds和u-boot-spl.lds,路径如下
suvine@ubuntu:~/workspace/source_code/mtk-openwrt-lede-4.2.1.0/bootloader/u-boot-mt7621-2018.09-gitb178829-20200526$ find ./ -name "u-boot.lds"
./arch/m68k/cpu/u-boot.lds
./arch/nds32/cpu/n1213/u-boot.lds
./arch/arm/cpu/armv8/u-boot.lds
./arch/arm/cpu/u-boot.lds
./arch/arm/mach-zynq/u-boot.lds
./arch/microblaze/cpu/u-boot.lds
./arch/powerpc/cpu/mpc83xx/u-boot.lds
./arch/powerpc/cpu/mpc85xx/u-boot.lds
./arch/powerpc/cpu/mpc86xx/u-boot.lds
./arch/sandbox/cpu/u-boot.lds
./arch/x86/cpu/u-boot.lds
./arch/nios2/cpu/u-boot.lds
./arch/xtensa/cpu/u-boot.lds
./arch/sh/cpu/u-boot.lds
./arch/arc/cpu/u-boot.lds
./arch/riscv/cpu/ax25/u-boot.lds
./arch/mips/cpu/u-boot.lds
./board/birdland/bav335x/u-boot.lds
./board/cssi/MCR3000/u-boot.lds
./board/cirrus/edb93xx/u-boot.lds
./board/compulab/cm_t335/u-boot.lds
./board/vscom/baltos/u-boot.lds
./board/qualcomm/dragonboard410c/u-boot.lds
./board/qualcomm/dragonboard820c/u-boot.lds
./board/ti/am335x/u-boot.lds
./u-boot.lds
suvine@ubuntu:~/workspace/source_code/mtk-openwrt-lede-4.2.1.0/bootloader/u-boot-mt7621-2018.09-gitb178829-20200526$ find ./ -name "u-boot-spl.lds"
./arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
./arch/arm/cpu/armv8/u-boot-spl.lds
./arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
./arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds
./arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
./arch/arm/cpu/u-boot-spl.lds
./arch/arm/cpu/arm1136/u-boot-spl.lds
./arch/arm/mach-at91/armv7/u-boot-spl.lds
./arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
./arch/arm/mach-zynq/u-boot-spl.lds
./arch/arm/mach-omap2/u-boot-spl.lds
./arch/microblaze/cpu/u-boot-spl.lds
./arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
./arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
./arch/sandbox/cpu/u-boot-spl.lds
./arch/x86/cpu/u-boot-spl.lds
./arch/mips/cpu/u-boot-spl.lds
./tpl/u-boot-spl.lds
./spl/u-boot-spl.lds
U-boot的执行通常从特定于体系架构(可能是
特定于CPU的)start.S文件开始,例如:
-arch/arm/cpu/armv7/start.S
-arch/powerpc/cpu/mpc83xx/start.S
-arch/mips/cpu/start.S
我们例举arch/mips/cpu/start.S源码:
#ifndef CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_SP_OFFSET)
#endif
#ifdef CONFIG_32BIT
# define MIPS_RELOC 3
# define STATUS_SET 0
#endif
#ifdef CONFIG_64BIT
# ifdef CONFIG_SYS_LITTLE_ENDIAN
# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
# else
# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
# endif
# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
# define STATUS_SET ST0_KX
#endif
.set noreorder
.macro init_wr sel
MTC0 zero, CP0_WATCHLO,\sel
mtc0 t1, CP0_WATCHHI,\sel
mfc0 t0, CP0_WATCHHI,\sel
bgez t0, wr_done
nop
.endm
.macro uhi_mips_exception
move k0, t9 # preserve t9 in k0
move k1, a0 # preserve a0 in k1
li t9, 15 # UHI exception operation
li a0, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
.endm
.macro setup_stack_gd
li t0, -16
PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
and sp, t1, t0 # force 16 byte alignment
PTR_SUBU \
sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0 # force 16 byte alignment
move k0, sp # save gd pointer
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_SUBU \
sp, sp, t2 # reserve space for early malloc
and sp, sp, t0 # force 16 byte alignment
#endif
move fp, sp
/* Clear gd */
move t0, k0
1:
PTR_S zero, 0(t0)
blt t0, t1, 1b
PTR_ADDIU t0, PTRSIZE
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif
.endm
ENTRY(_start)
/* U-Boot entry point */
b reset
mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
/*
* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
* access external NOR flashes. If the board boots from NOR flash the
* internal BootROM does a blind read at address 0xB0000010 to read the
* initial configuration for that EBU in order to access the flash
* device with correct parameters. This config option is board-specific.
*/
.org 0x10
.word CONFIG_SYS_XWAY_EBU_BOOTCFG
.word 0x0
#endif
#if defined(CONFIG_MALTA)
/*
* Linux expects the Board ID here.
*/
.org 0x10
.word 0x00000420 # 0x420 (Malta Board with CoreLV)
.word 0x00000000
#endif
#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
/*
* Exception vector entry points. When running from ROM, an exception
* cannot be handled. Halt execution and transfer control to debugger,
* if one is attached.
*/
.org 0x200
/* TLB refill, 32 bit task */
uhi_mips_exception
.org 0x280
/* XTLB refill, 64 bit task */
uhi_mips_exception
.org 0x300
/* Cache error exception */
uhi_mips_exception
.org 0x380
/* General exception */
uhi_mips_exception
.org 0x400
/* Catch interrupt exceptions */
uhi_mips_exception
.org 0x480
/* EJTAG debug exception */