iTop-4412精英版的u-boot-2017.11移植教程（三）

接着上一节iTop-4412精英版的u-boot-2017.11移植教程（二）

（一）修改clock.c

经过上面两节的修改，我们发现还是有些问题，就是u-boot启动后会停留在MMC: ，其实这是由于在clock.c文件中关于mmc和lcd部分的结构体用错了

exynos4_get_mmc_clk()

exynos4_set_mmc_clk()

exynos4_get_lcd_clk()


exynos4_set_lcd_clk()


根据文档资料，exynos4412芯片属于4x12系列，而不是4系列，所以要改一下

（二）修改lowlevel_init.c

由于itop-4412开发板用的串口是串口2，所以改一下；还有就是tzpc的初始化，u-boot-2017.11默认的tzpc是exynos5系列芯片的，其实exynos4412已经有tzpc了，关于exynos的tzpc相关的知识，大家可以去网上学习，由于我移植的u-boot又不是用于高大上的商业机密啥的，就把它注释了，如果自己想加上tzpc的话，自己参考讯为提供的三星原厂exynos4412芯片文档，在第14章。

讯为提供的三星原厂exynos4412芯片文档第14章

（三）修改power.c

（1）为power.h文件增加exynos4x12_power
这是由于exynos4412芯片属于exynos4x12类型

这个结构体来源与讯为提供的三星原厂exynos4412芯片资料的8.8 Register Description

代码

struct exynos4x12_power {
    unsigned int    om_stat;
    unsigned char   res1[0xc];
    unsigned int    rtc_clko_sel;
    unsigned int    gnss_rtc_out_ctrl;
    unsigned int    lpi_denial_mask0;
    unsigned int    lpi_denial_mask1;
    unsigned int    lpi_denial_mask2;
    unsigned int    c2c_ctrl;
    unsigned char   res2[0x1d8];
    unsigned int    central_seq_config;
    unsigned int    res3;
    unsigned int    central_seq_option;
    unsigned char   res4[0x1f4];
    unsigned int    swreset;
    unsigned int    rst_stat;
    unsigned int    auto_wdt_reset_disable;
    unsigned int    mask_wdt_reset_request;
    unsigned char   res5[0x1f0];
    unsigned int    wakeup_stat;
    unsigned int    eint_wakeup_mask;
    unsigned int    wakeup_mask;
    unsigned char   res6[0xf4];
    unsigned int    hdmi_phy_control;
    unsigned int    usbdevice_phy_control;
    unsigned int    hsic_1_phy_control;
    unsigned int    hsic_2_phy_control;
    unsigned int    mipi_phy0_control;
    unsigned int    mipi_phy1_control;
    unsigned int    adc_phy_control;
    unsigned char   res7[0x64];
    unsigned int    body_bias_con0;
    unsigned int    body_bias_con1;
    unsigned int    body_bias_con2;
    unsigned int    body_bias_con3;
    unsigned char   res8[0x70];
    unsigned int    inform0;
    unsigned int    inform1;
    unsigned int    inform2;
    unsigned int    inform3;
    unsigned int    inform4;
    unsigned int    inform5;
    unsigned int    inform6;
    unsigned int    inform7;
    unsigned char   res9[0x1e0];
    unsigned int    pmu_debug;
    unsigned char   res10[0x5fc];
    unsigned int    arm_core0_sys_pwr_reg;
    unsigned char   res11[0xc];
    unsigned int    arm_core1_sys_pwr_reg;
    unsigned char   res12[0x6c];
    unsigned int    arm_common_sys_pwr_reg;
    unsigned char   res13[0x3c];
    unsigned int    arm_cpu_l2_0_sys_pwr_reg;
    unsigned int    arm_cpu_l2_1_sys_pwr_reg;
    unsigned char   res14[0x38];
    unsigned int    cmu_aclkstop_sys_pwr_reg;
    unsigned int    cmu_sclkstop_sys_pwr_reg;
    unsigned char   res15[0x4];
    unsigned int    cmu_reset_sys_pwr_reg;
    unsigned char   res16[0x10];
    unsigned int    apll_sysclk_sys_pwr_reg;
    unsigned int    mpll_sysclk_sys_pwr_reg;
    unsigned int    vpll_sysclk_sys_pwr_reg;
    unsigned int    epll_sysclk_sys_pwr_reg;
    unsigned char   res17[0x8];
    unsigned int    cmu_clkstop_gps_alive_sys_pwr_reg;
    unsigned int    cmu_reset_gps_alive_sys_pwr_reg;
    unsigned int    cmu_clkstop_cam_sys_pwr_reg;
    unsigned int    cmu_clkstop_tv_sys_pwr_reg; 
    unsigned int    cmu_clkstop_mfc_sys_pwr_reg;
    unsigned int    cmu_clkstop_g3d_sys_pwr_reg;
    unsigned int    cmu_clkstop_lcd0_sys_pwr_reg;
    unsigned int    cmu_clkstop_isp_sys_pwr_reg;
    unsigned int    cmu_clkstop_maudio_sys_pwr_reg;
    unsigned int    cmu_clkstop_gps_sys_pwr_reg;
    unsigned int    cmu_reset_cam_sys_pwr_reg;
    unsigned int    cmu_reset_tv_sys_pwr_reg;
    unsigned int</