【VHDL】基本组合电路的设计

最新推荐文章于 2024-08-12 14:49:03 发布

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最新推荐文章于 2024-08-12 14:49:03 发布

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文章标签： VHDL 组合电路

本文链接：https://blog.csdn.net/icurious/article/details/58257059

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基本门电路

基本门电路可以调用基本的库，也可以自己动手写而后封装。

XOR异或门

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY XOR_gate is
port (  x,y : in std_logic;
        fxor: out std_logic);
end XOR_gate;

ARCHITECTURE Boolean_function of XOR_gate is
begin 
fxor<=x xor y;
-- fxor=(not x and y) or (x and not y);
end Boolean_function;

NAND

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NAND_gate IS PORT
(x,y:in STD_LOGIC;
fnand:out STD_LOGIC);
END NAND_gate;

ARCHITECTURE Boolean_function of NAND_gate is
BEGIN 
fnand<=x nand y;
end Boolean_function;

BUFFER

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BUFFER_gate IS PORT
(x:in STD_LOGIC;
fbuf:out STD_LOGIC);
END BUFFER_gate;

ARCHITECTURE Boolean_function of BUFFER_gate is
BEGIN 
fbuf<=x;
end Boolean_function;

用标准形式给出的任意布尔函数的VHDL设计

VHDL设计可以任意凡事得布尔函数获得：
1. 得到该函数的真值表或者紧凑的最小项或者最大项表达式
2. 写出函数的规范形式，及规范的SOP（CSOP，规范与或式）形式，或者规范的POS（CPOS，标准或于式）
3. 写出VHDL中的布尔函数的赋值语句

F(A, B, C)=(~ A ●B ● C) +(A ●~B ● C) +(A ●B ●~C)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TWO_1S IS PORT
(a,b,c:in STD_LOGIC;
f_1s,f_0s:out STD_LOGIC);
END TWO_1S;

ARCHITECTURE Boolean_function of TWO_1S is
BEGIN
-- the canonical SOP form for the 1s for the function f
f_1s<=(not a and b and c) or 
      (a and not b and c) or 
      (a and b and not c);
END Boolean_function;